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ORCIDVishnu P. Nambiar
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2020 – today
- 2024
[c20]Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do:
PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications. HCS 2024: 1- [c19]Yi Sheng Chong, Hongyu Cao, Wang Ling Goh, Patrick Bore, Yuanzheng Paul Tan
, Yung Szen Yap, Rainer Dumke, Vishnu P. Nambiar, Anh Tuan Do:
Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature. ISCAS 2024: 1-5 - [c18]Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do:
A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. ISCAS 2024: 1-5 - [c17]Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar:
Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. ISCAS 2024: 1-5 - [c16]Zhangyi Pei, Vishnu P. Nambiar, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do:
3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications. ISCAS 2024: 1-5 - 2022
- [j10]Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do:
A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1662-1666 (2022) - [c15]Jingjing Lan, Vishnu P. Nambiar, Ming Ming Wong, Fei Li, Yuan Gao, Kevin Tshun Chuan Chai, Anh Tuan Do:
A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS. ISCAS 2022: 2433-2437 - [c14]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications. ISCAS 2022: 2680-2684 - [c13]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training. ISCAS 2022: 2958-2962 - 2021
- [j9]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Ming Ming Wong, Anh Tuan Do:
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5081-5094 (2021) - [j8]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do:
A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 471-475 (2021) - [j7]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Yi Sheng Chong, Anh Tuan Do:
A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1398-1402 (2021) - [j6]Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do:
Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3148-3152 (2021) - [c12]Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSCIRC 2021: 95-98 - [c11]Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSDERC 2021: 95-98 - [c10]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. ISCAS 2021: 1-5 - [c9]Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
Efficient Implementation of Activation Functions for LSTM accelerators. VLSI-SoC 2021: 1-5 - 2020
- [c8]Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Tao Luo, L. Yang, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do:
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. A-SSCC 2020: 1-4 - [c7]Yun Kwan Lee, Vishnu P. Nambiar, Kim Seng Goh, Anh Tuan Do:
Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware. IECON 2020: 3836-3840 - [c6]Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do:
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c5]Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh:
Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm. ISCAS 2019: 1-5 - [c4]Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do:
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. SoCC 2019: 27-32 - [c3]Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do:
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. SoCC 2019: 242-247 - 2017
- [j5]Yee Hui Lee, Mohamed Khalil Hani, Rabia Bakhteri, Vishnu P. Nambiar:
A real-time near infrared image acquisition system based on image quality assessment. J. Real Time Image Process. 13(1): 103-120 (2017) - 2014
- [j4]Vishnu P. Nambiar, Mohamed Khalil Hani, Riadh Sahnoun, Muhammad N. Marsono:
Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function. Neurocomputing 140: 228-241 (2014) - [j3]Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad N. Marsono, Chen Wei Sia:
Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm. Neurocomputing 145: 285-302 (2014) - 2013
- [j2]Vishnu P. Nambiar, Sathivellu Balakrishnan, Mohamed Khalil Hani, Muhammad N. Marsono:
HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems. Computing 95(9): 863-896 (2013) - [c2]Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono:
Co-simulation methodology for improved design and verification of hardware neural networks. IECON 2013: 2226-2231 - 2012
- [c1]Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono:
GA-based parameter tuning in finger-vein biometric embedded systems for information security. ICCC 2012: 236-241
2000 – 2009
- 2009
- [j1]Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad Munim Ahmad Zabidi:
Accelerating the AES encryption function in OpenSSL for embedded systems. Int. J. Inf. Commun. Technol. 2(1/2): 83-93 (2009)
Coauthor Index
aka: Anh Tuan Do
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