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2020 – today
- 2024
[c12]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim
, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256- 2020
- [j8]Indira Nair, William M. Bulleit:
Pragmatism and Care in Engineering Ethics. Sci. Eng. Ethics 26(1): 65-87 (2020)
2010 – 2019
- 2013
- [j7]Martin Ohmacht, Amy Wang, Thomas Gooding, Ben J. Nathanson, Indira Nair, Geert Janssen, Marcel Schaal, Burkhard D. Steinmacher-Burow:
IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory. IBM J. Res. Dev. 57(1/2): 7 (2013) - 2012
- [c11]Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger:
Power management of multi-core chips: Challenges and pitfalls. DATE 2012: 977-982 - 2010
- [j6]Howard Chen, Indira Nair, Benjamin Mashak:
The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise. J. Low Power Electron. 6(1): 173-180 (2010) - [c10]Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban:
Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304
2000 – 2009
- 2009
- [c9]Howard Chen, Indira Nair:
Power Management and Its Impact on Power Supply Noise. PATMOS 2009: 106-115 - 2008
- [c8]Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer:
Exploring power management in multi-core systems. ASP-DAC 2008: 708-713 - 2007
- [c7]Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han:
Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214 - 2005
- [j5]Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin:
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Des. Autom. Embed. Syst. 10(2-3): 105-125 (2005) - 2004
- [c6]Valentina Salapura, Christos J. Georgiou, Indira Nair:
An efficient system-on-a-chip design methodology for networking applications. CASES 2004: 212-219 - 2003
- [c5]Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal:
SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155 - 2002
- [j4]John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin:
Early analysis tools for system-on-a-chip design. IBM J. Res. Dev. 46(6): 691-708 (2002)
1990 – 1999
- 1997
- [j3]Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan:
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 82-100 (1997) - 1995
- [j2]Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal:
AVPGEN-A test generator for architecture verification. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 188-200 (1995) - 1994
- [c4]Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen:
Architectural Verification of Processors Using Symbolic Instruction Graphs. ICCD 1994: 454-459 - 1992
- [c3]Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy:
A Small Test Generator for Large Designs. ITC 1992: 30-40 - 1991
- [c2]Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar:
Symbolic implication in test generation. EURO-DAC 1991: 492-496
1980 – 1989
- 1986
- [j1]Max Henrion, M. Granger Morgan, Indira Nair, Charles Wiecha:
Evaluating an information system for policy modeling and uncertainty analysis. J. Am. Soc. Inf. Sci. 37(5): 319-330 (1986) - [c1]Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman:
Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529
Coauthor Index
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