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ORCIDToshiro Hiramoto
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2020 – today
- 2024
[c21]Masaharu Kobayashi, Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka:
Performance and Reliability of Nanosheet Oxide Semiconductor FETs with ALD-Grown InGaO for 3D Integration (Invited). IRPS 2024: 9- [c20]Kaito Hikake, Xingyu Huang, Sung-Hun Kim, Kota Sakai, Zhuo Li, Tomoko Mizutani, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi:
Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration-ALD Material Engineering, High-Field Transport, Statistical Variability. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c19]Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi:
A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c18]Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi
, Hiroshi Toshiyoshi, Toshiro Hiramoto:
3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers. Imaging Sensors and Systems 2022: 1-4 - 2021
- [c17]Toshiro Hiramoto, Takuya Saraya:
Recent Progress of Double/Dual-Gate Silicon IGBT Technologies. ASICON 2021: 1-4 - 2020
- [c16]Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto:
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS 2020: 305-309
2010 – 2019
- 2019
- [c15]Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. 3DIC 2019: 1-4 - [c14]Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa:
Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON 2019: 1-3 - [c13]Masaharu Kobayashi, Chengji Jin, Toshiro Hiramoto:
Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model. ASICON 2019: 1-4 - [c12]Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi:
Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method. NVMTS 2019: 1-5 - 2018
- [c11]Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai:
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC 2018: 26-29 - [c10]Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration. ISCAS 2018: 1-4 - [c9]Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai:
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits 2018: 105-106 - 2017
- [c8]Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi:
Parallel nonvolatile programming of power-up states of SRAM cells. ASICON 2017: 418-421 - [c7]Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai:
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON 2017: 1137-1140 - 2015
- [j11]Kosmas Galatsis, Paolo Gargini, Toshiro Hiramoto, Dirk Beernaert, Roger DeKeersmaecker, Joachim Pelka, Lothar Pfitzner:
Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) [Commentary]. IEEE Technol. Soc. Mag. 34(2): 21-30 (2015) - [c6]Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers. 3DIC 2015: TS9.2.1-TS9.2.4 - 2013
- [j10]Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto:
NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM. IEICE Trans. Electron. 96-C(5): 620-623 (2013) - [j9]Tomoko Mizutani, Anil Kumar, Toshiro Hiramoto:
Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs. IEICE Trans. Electron. 96-C(5): 630-633 (2013) - [j8]Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano:
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress. IEICE Trans. Electron. 96-C(6): 759-765 (2013) - 2011
- [c5]Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya:
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs. CICC 2011: 1-4 - [c4]Toshiro Hiramoto:
Ultra-low-voltage operation: device perspective. ISLPED 2011: 59-60 - 2010
- [j7]George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida:
Nanoelectronics Research for Beyond CMOS Information Processing. Proc. IEEE 98(12): 1986-1992 (2010) - [j6]Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida:
Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. Proc. IEEE 98(12): 1993-2004 (2010)
2000 – 2009
- 2007
- [j5]Toshiro Hiramoto, Toshiharu Nagumo, Tetsu Ohtou, Kouki Yokoyama:
Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations. IEICE Trans. Electron. 90-C(4): 836-841 (2007) - 2006
- [j4]Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui:
Emerging nanoscale silicon devices taking advantage of nanostructure physics. IBM J. Res. Dev. 50(4-5): 411-418 (2006) - 2003
- [j3]Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai:
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 755-761 (2003) - 2001
- [c3]Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai:
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. ISLPED 2001: 123-128 - [c2]Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai:
Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED 2001: 201-206 - 2000
- [c1]Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai:
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. CICC 2000: 409-412
1990 – 1999
- 1994
- [j2]Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima:
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits 29(4): 419-425 (1994) - [j1]Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda:
A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates. IEEE J. Solid State Circuits 29(11): 1344-1352 (1994)
Coauthor Index
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