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2020 – today
- 2020
[c10]Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi
, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto:
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS 2020: 305-309
2010 – 2019
- 2010
- [j3]Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. IEICE Trans. Electron. 93-C(3): 332-339 (2010)
2000 – 2009
- 2008
- [c9]Sungdae Choi, Katsuyuki Ikeuchi, Hyunkyung Kim, Kenichi Inagaki, Masami Murakata, Nobuyuki Nishiguchi, Makoto Takamiya, Takayasu Sakurai:
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node. ESSCIRC 2008: 50-53 - [c8]Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. ISLPED 2008: 117-122 - [c7]Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. ISQED 2008: 133-136 - 2006
- [j2]Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi:
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. IEICE Trans. Electron. 89-C(3): 263-270 (2006) - [j1]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006)
1990 – 1999
- 1998
- [c6]Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design. ASP-DAC 1998: 307-312 - [c5]Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata:
A DRAM module generator with an expandable cell array scheme. CICC 1998: 287-290 - 1997
- [c4]Masako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi:
Layout Driven Re-synthesis for Low Power Consumption LSIs. DAC 1997: 666-669 - 1996
- [c3]Takashi Mitsuhashi, Masami Murakata, Kenji Yoshida, Takahiro Aoki:
Physical design CAD in deep sub-micron era. EURO-DAC 1996: 350-355 - [c2]Taku Uchino, Fumihiro Minami, Masami Murakata, Takashi Mitsuhashi:
Switching activity analysis for sequential circuits using Boolean approximation method. ISLPED 1996: 79-84 - 1995
- [c1]T. Aoki, Masami Murakata, Takashi Mitsuhashi, Nobuyuki Goto:
Fanout-tree restructuring algorithm for post-placement timing optimization. ASP-DAC 1995
Coauthor Index
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