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ORCIDUlrich Ramacher
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2010 – 2019
- 2011
[c21]Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington:
Architecture and implementation of a Software-Defined Radio baseband processor. ISCAS 2011: 2193-2196
2000 – 2009
- 2007
- [j13]Ulrich Ramacher:
Software-Defined Radio Prospects for Multistandard Mobile Phones. Computer 40(10): 62-69 (2007) - [j12]Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf:
Roundtable: Envisioning the Future for Multiprocessor SoC. IEEE Des. Test Comput. 24(2): 174-183 (2007) - [c20]Ulrich Ramacher:
Challenges and prospects of SDR for mobile phones. ICCD 2007: 215 - 2005
- [j11]Peter Benkart, Alexander Kaiser, Andreas Munding
, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher:
3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Des. Test Comput. 22(6): 512-518 (2005) - [j10]Joachim M. Buhmann, Tilman Lange, Ulrich Ramacher:
Image Segmentation by Networks of Spiking Neurons. Neural Comput. 17(5): 1010-1031 (2005) - [c19]Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt:
Wireless platforms: GOPS for cents and MilliWatts. DAC 2005: 351-352 - [c18]Axel Techmer, Hans-Martin Blüthgen, Cyprian Grassmann, J. A. Ulrich Hachmann, Wolfgang Raab, Ulrich Ramacher:
Embedded vision platform for video surveillance systems. Electronic Imaging: Image and Video Communications and Processing 2005 - [c17]Werner Hemmert, Marcus Holmberg, Ulrich Ramacher:
Temporal Sound Processing by Cochlear Nucleus Octopus Neurons. ICANN (1) 2005: 583-588 - [c16]Marcus Holmberg, David Gelbart, Ulrich Ramacher, Werner Hemmert:
Automatic speech recognition with neural spike trains. INTERSPEECH 2005: 1253-1256 - 2004
- [c15]Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny:
Pulse coupled neural networks with adaptive synapses for image segmentation. ARCS Workshops 2004: 275-282 - [c14]Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny:
Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. Image Processing: Algorithms and Systems 2004: 290-296 - [c13]Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher:
A low-power memory hierarchy for a fully programmable baseband processor. WMPI 2004: 102-106 - 2003
- [j9]Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer:
A 100-GOPS Programmable Processor for Vehicle Vision Systems. IEEE Des. Test Comput. 20(1): 8-16 (2003) - [j8]Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer:
100 GOPS vision processor for automotive applications. SIGARCH Comput. Archit. News 31(1): 60-68 (2003) - [c12]Hans-Martin Blüthgen, Cyprian Grassmann, Wolfgang Raab, Ulrich Ramacher:
A programmable platform for software-defined radio. SoC 2003 - [c11]Arne Heittmann, Ulrich Ramacher:
Correlation-based feature detection using pulsed neural networks. NNSP 2003: 479-488 - 2002
- [c10]Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny:
An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. ICANN 2002: 1293-1298 - [c9]Ulrich Ramacher:
Application Specific Embedded Processors for Next Generation Communication Systems. ICCD 2002 - [c8]Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, D. Matolini, René Schüffny:
Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. NNSP 2002: 657-666 - 2001
- [c7]Chr. Werner, Ralf Goettsche, A. Wörner, Ulrich Ramacher:
Crosstalk noise in future digital CMOS circuits. DATE 2001: 331-335
1990 – 1999
- 1999
- [c6]Ulrich Ramacher, Wolfgang Raab, Wolfgang Kabatzke:
Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik. PEARL 1999: 102-110 - 1996
- [c5]Ulrich Ramacher:
SEE-1 - A Vision System for Use in Real World Environments. ICANN 1996: 17 - 1995
- [c4]Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer:
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. IPPS 1995: 774-781 - 1993
- [j7]Ulrich Ramacher, Peter Schildberg:
Recent Developments In Neurodynamics And Their Impact On The Design Of Neuro-Chips. Int. J. Neural Syst. 4(4): 309-316 (1993) - [j6]Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz:
Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. Int. J. Neural Syst. 4(4): 333-336 (1993) - [j5]Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar:
Design of a general-purpose neural signal processor. Neurocomputing 5(1): 17-23 (1993) - [j4]Ulrich Ramacher:
Hamiltonian dynamics of neural networks. Neural Networks 6(4): 547-557 (1993) - [j3]Ulrich Ramacher, Jörg Beichter, Nico Brüls:
A general-purpose signal processor architecture for neurocomputing and preprocessing applications. J. VLSI Signal Process. 6(1): 45-56 (1993) - [c3]Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder:
Architecture and VLSI Design of a VLSI Neural Signal Processor. ISCAS 1993: 1975-1978 - 1992
- [j2]Karl Goser, Ulrich Ramacher:
Mikroelektronische Realisierung von künstlichen neuronalen Netzen / Microelectronic Realizations of artificial neural networks. it Inf. Technol. 34(4): 241-247 (1992) - [j1]Ulrich Ramacher:
SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine. J. Parallel Distributed Comput. 14(3): 306-318 (1992) - 1990
- [c2]Ulrich Ramacher, Wolfgang Raab:
Fine-grain system architectures for systolic emulation of neural algorithms. ASAP 1990: 554-566
1980 – 1989
- 1989
- [c1]Matthias Wesseling, Ulrich Ramacher, Karl Goser:
Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area. Fehlertolerierende Rechensysteme 1989: 74-84
Coauthor Index
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