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ORCIDFukashi Morishita
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2020 – today
- 2023
[c8]Yoichi Iizuka, Akihide Maezono, Wataru Saito
, Atsushi Yamane, Kazuhiko Takami, Fukashi Morishita:
A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System. A-SSCC 2023: 1-3- 2022
- [j20]Fukashi Morishita, Wataru Saito, Norihito Kato, Yoichi Iizuka, Masao Ito:
High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor. IEICE Trans. Electron. 105-C(7): 316-323 (2022) - [j19]Fukashi Morishita, Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Masao Ito:
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera. IEEE J. Solid State Circuits 57(10): 3103-3113 (2022) - [j18]Norihito Kato, Fukashi Morishita, Satoshi Okubo, Masao Ito:
Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor. Sensors 22(16): 6040 (2022) - 2021
- [c7]Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Fukashi Morishita:
A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator. A-SSCC 2021: 1-3 - [c6]Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo:
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems. VLSI Circuits 2021: 1-2 - 2020
- [c5]Fukashi Morishita, Masanori Otsuka, Wataru Saito:
An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor. ATS 2020: 1-6
2010 – 2019
- 2015
- [j17]Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita:
A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. IEEE J. Solid State Circuits 50(4): 1016-1024 (2015) - 2014
- [c4]Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Masanori Tachibana, Fukashi Morishita:
A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit. VLSIC 2014: 1-2 - 2013
- [j16]Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto:
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits 48(11): 2608-2617 (2013)
2000 – 2009
- 2009
- [j15]Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto:
On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. 92-C(3): 356-363 (2009) - 2007
- [j14]Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. 90-C(4): 765-771 (2007) - [j13]Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto:
A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Trans. Electron. 90-C(10): 1927-1935 (2007) - [j12]Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto:
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42(4): 853-861 (2007) - [j11]Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi:
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42(11): 2611-2619 (2007) - 2006
- [j10]Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba:
An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Trans. Electron. 89-C(11): 1519-1525 (2006) - [j9]Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto:
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. 89-C(11): 1612-1619 (2006) - [c3]Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka:
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC 2006: 429-432 - 2005
- [j8]Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara:
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. 88-C(10): 2020-2027 (2005) - [j7]Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits 40(1): 204-212 (2005) - [j6]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005) - [j5]Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto:
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits 40(11): 2296-2304 (2005) - [c2]Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC 2005: 435-438 - [c1]Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto:
A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. CICC 2005: 451-454 - 2003
- [j4]Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki:
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2991-3000 (2003) - 2000
- [j3]Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara:
High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits 35(8): 1169-1178 (2000)
1990 – 1999
- 1996
- [j2]Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto:
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits 31(4): 586-591 (1996) - 1994
- [j1]Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara:
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits 29(11): 1323-1329 (1994)
Coauthor Index
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