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ORCIDJürgen Schlöffel
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2010 – 2019
- 2017
[j8]Pascal Vivet
, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel:
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits 52(1): 33-49 (2017)- 2016
- [c25]Jean Durupt, Pascal Vivet, Juergen Schloeffel:
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system. ETS 2016: 1-6 - 2015
- [c24]Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel:
3D DFT Challenges and Solutions. ISVLSI 2015: 603-608 - 2014
- [j7]Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast:
Cell-Aware Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1396-1409 (2014) - [c23]Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski:
Cell-aware experiences in a high-quality automotive test suite. ETS 2014: 1-6 - [c22]Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel:
2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI 2014: 386-391 - 2012
- [c21]Friedrich Hapke, Jürgen Schlöffel:
Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates. ETS 2012: 1-6 - [c20]Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski:
Cell-aware Production test results from a 32-nm notebook processor. ITC 2012: 1-9 - 2011
- [c19]Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers:
Cell-aware analysis for small-delay effects and production test results from different fault models. ITC 2011: 1-8 - 2010
- [j6]Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler:
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26(3): 307-322 (2010) - [c18]Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler:
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS 2010: 176-181 - [c17]Friedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger:
Defect-oriented cell-internal testing. ITC 2010: 285-294
2000 – 2009
- 2009
- [j5]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille:
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51(2): 102-111 (2009) - [j4]Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian:
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4): 56:1-56:21 (2009) - [c16]Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson:
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. ITC 2009: 1-10 - [c15]Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz:
Restrict Encoding for Mixed-Mode BIST. VTS 2009: 179-184 - 2008
- [j3]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1329-1333 (2008) - [c14]Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker:
Resistive Bridging Fault Simulation of Industrial Circuits. DATE 2008: 628-633 - 2007
- [j2]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic logic BIST for transition fault testing. IET Comput. Digit. Tech. 1(3): 180-186 (2007) - [c13]Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel:
Computation and Application of Absolute Dominators in Industrial Designs. ETS 2007: 137-144 - [c12]Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers:
Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI 2007: 287-292 - [c11]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6 - [c10]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef:
Programmable deterministic Built-In Self-Test. ITC 2007: 1-9 - [c9]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187 - 2006
- [j1]Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke:
X-masking during logic BIST and its impact on defect coverage. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 193-202 (2006) - [c8]Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke:
Fault detection and diagnosis with parity trees for space compaction of test responses. DAC 2006: 1095-1098 - [c7]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic Logic BIST for Transition Fault Testing. ETS 2006: 123-130 - 2005
- [c6]Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium 2005: 22-27 - [c5]Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217 - [c4]Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel:
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design 2005: 354-359 - [c3]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel:
Implementing a Scheme for External Deterministic Self-Test. VTS 2005: 101-106 - 2004
- [c2]Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel:
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT 2004: 174-182 - 2000
- [c1]Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel:
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS 2000: 306-315
Coauthor Index
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