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ORCIDISVLSI 2015: Montpellier, France
- 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-8719-1
Session 01: Computer Aided Design and Verification
- Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große
, Rolf Drechsler:
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. 1-6 - Rajdeep Mukherjee, Daniel Kroening, Tom Melham:
Hardware Verification Using Software Analyzers. 7-12 - Rajdeep Mukherjee, Daniel Kroening, Tom Melham, Mandayam K. Srivas:
Equivalence Checking Using Trace Partitioning. 13-18
Session 02: Efficient Digital Designs
- Ivan Ratkovic, Oscar Palomar, Milan Stanic, Milovan Duric, Djordje Peic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. 19-26 - Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel:
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. 27-32 - Mohammad Haji Seyed Javadi, Hamid Reza Mahdiani:
Efficient Utilization of Imprecise Blocks for Hardware Implementation of a Gaussian Filter. 33-37
Session 03: Physical Design and Testing
- Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat:
A Detailed Routing-Aware Detailed Placement Technique. 38-43 - Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young:
An Effective Chemical Mechanical Polishing Filling Approach. 44-49 - Niels Thole, Görschwin Fey, Alberto García Ortiz:
Conservatively Analyzing Transient Faults. 50-55
Session 04: FPGA and NoC Based Designs
- Ali Ibrahim, Maurizio Valle, Luca Noli, Hussein Chible:
Assessment of FPGA Implementations of One Sided Jacobi Algorithm for Singular Value Decomposition. 56-61 - Masoud Oveis Gharan, Gul N. Khan:
Index-Based Round-Robin Arbiter for NoC Routers. 62-67
Session 05: Poster Session
- Arathi Ajay, R. Mary Lourde:
VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications. 68-73 - Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi:
Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power. 74-79 - Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay:
FPGA Based Novel High Speed DAQ System Design with Error Correction. 80-85 - Ali Dadashi, Yngvar Berg, Omid Mirmotahari:
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter. 86-90 - Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis:
Modulo 2n ± 1 Fused Add-Multiply Units. 91-96 - Peter Malík:
High Throughput Floating Point Exponential Function Implemented in FPGA. 97-100 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli:
Exploiting Circuit Duality to Speed up SAT. 101-106 - Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
A New Method for Defining Monotone Staircases in VLSI Floorplans. 107-112 - Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski:
Logic Debugging of Arithmetic Circuits. 113-118 - Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros:
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. 119-124 - Donald M. Chiarulli, Brandon B. Jennings, Yan Fang, Andrew J. Seel, Steven P. Levitan:
A Computational Primitive for Convolution based on Coupled Oscillator Arrays. 125-130 - M. Tarek Ibn Ziad, Amr Al-Anwar, Yousra Alkabani, M. Watheq El-Kharashi, Hassan Bedour:
Homomorphic Data Isolation for Hardware Trojan Protection. 131-136 - Rajshekar Kalayappan, Smruti R. Sarangi:
SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators. 137-142 - Matthias Hiller, Ludwig Kurzinger, Georg Sigl, Sven Müelich, Sven Puchinger, Martin Bossert:
Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs. 143-148 - Hamzeh Ahangari, Gulay Yalcin, Ozcan Ozturk, Osman S. Unsal, Adrián Cristal:
JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories. 149-154 - Irith Pomeranz:
Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence. 155-160 - Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Horácio C. Neto, Eduardo Augusto Bezerra:
A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow. 161-166 - Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake:
Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. 167-171 - Santanu Sarkar, Swapna Banerjee:
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. 172-177 - Anush Bekal, Rohit Joshi, Manish Goswami, Babu R. Singh, Ashok Srivatsava:
An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC. 178-182
Session 06: Ph.D. Forum
- Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. 183-186 - Lafifa Jamal, Hafiz Md. Hasan Babu:
Design and Implementation of a Reversible Central Processing Unit. 187-190 - Zhou Zhao, Ashok Srivastava, Shaoming Chen, Saraju P. Mohanty:
An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip. 191-194 - Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal:
Validating SPARK: High Level Synthesis Compiler. 195-198
Keynote 1
- Tanya Nigam, Andreas Kerber:
Enabling Scaling of Advanced CMOS Technologies: A Reliability Perspective. 199
Session 07: Special Session: IP Protection
- Jérôme Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario Barbareschi:
Digital Right Management for IP Protection. 200-203 - Shweta Malik, Georg T. Becker, Christof Paar, Wayne P. Burleson:
Development of a Layout-Level Hardware Obfuscation Tool. 204-209 - Brice Colombier, Lilian Bossuet, David Hély:
Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection. 210-215 - Edward Jung, Seonho Choi:
Identification of IP Control Units by State Encoding. 216-220
Session 08: Special Session: Biosignal Processing Embedded Systems
- John Taylor, Benjamin Metcalfe, Chris Clarke, Daniel Chew, Thomas Nielsen, Nick Donaldson:
A Summary of Current and New Methods in Velocity Selective Recording (VSR) of Electroneurogram (ENG). 221-226 - Yannick Bornat, Adam Quotb, Noëlle Lewis, Sylvie Renaud:
Resource Optimized Processor for Real-Time Neural Activity Monitoring. 227 - Olivier Rossel, Fabien Soulier, Serge Bernard, David Guiraud, Guy Cathébras:
In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber. 228-230
Session 09: Mixed-Signal and Optimization
- Yan Fang, Victor V. Yashin, Donald M. Chiarulli, Steven P. Levitan:
A Simplified Phase Model for Oscillator Based Computing. 231-236 - Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
A Statistical Approach to Probe Chaos from Noise in Analog and Mixed Signal Designs. 237-242 - Alireza Mahzoon, Bijan Alizadeh:
Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. 243-248
Session 10: Digital Designs
- Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So:
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. 249-254 - Zenghua Cheng, Xuchong Zhang, Huisheng Peng, Baolu Zhai, Hongbin Sun, Nanning Zheng:
VLSI Design of Edge-Preserving Coding Artifacts Reduction for Display Processing. 255-261 - Christian Brugger, Valentin Grigorovici, Matthias Jung, Christian Weis, Christian de Schryver, Katharina Anna Zweig, Norbert Wehn:
A Custom Computing System for Finding Similarties in Complex Networks. 262-267
Session 11: Special Session: Minimizing Energy Consumption of Computing to the Limit
- Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, David Atienza:
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices. 268-273 - Francesco Orfei, Luca Gammaitoni:
Logic Switches Operating at the Minimum Energy of Computing. 274-279 - Giuseppe Tagliavini, Davide Rossi, Luca Benini, Andrea Marongiu:
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. 280-285
Session 12: Special Session: Unconventional Computing
- Mario Cofano, Giulia Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni:
Logic-in-Memory: A Nano Magnet Logic Implementation. 286-291 - Shital Joshi, Elias Kougianos, Saraju P. Mohanty:
Simscape Based Ultra-Fast Design Exploration of Graphene-Nanoelectronic Systems. 292-296 - Mozammel H. A. Khan, Himanshu Thapliyal:
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression. 297-302
Session 13: Emerging Device Based Designs
- Moon Seok Kim, William Cane-Wissing, Jack Sampson, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta:
Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs. 303-308 - David Cavalheiro, Francesc Moll, Stanimir Stoyanov Valtchev:
Novel UHF Passive Rectifier with Tunnel FET Devices. 309-314 - Christophe Layer, Kotb Jabeur, Laurent Becker, Bernard Dieny, Stephane Gros, Virgile Javerliac, Pierre Paoli, Fabrice Bernard-Granger:
Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC. 315-320
Session 14: Special Session: Emerging Non-Volatile Memories
- Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres:
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures. 321-326 - Cristian Zambelli, Alessandro Grossi, Piero Olivo, Christian Walczyk, Christian Wenger:
RRAM Reliability/Performance Characterization through Array Architectures Investigations. 327-332 - Ahmedullah Aziz, William Cane-Wissing, Moon Seok Kim, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta:
Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective. 333-338
Session 15: Post-CMOS Computing Systems
- Kaisheng Ma, Nandhini Chandramoorthy, Xueqing Li, Sumeet Kumar Gupta, John Sampson, Yuan Xie, Vijaykrishnan Narayanan:
Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing. 339-344 - Mayukh Sarkar, Prasun Ghosal:
Implementing Data Structure Using DNA: An Alternative in Post CMOS Computing. 345-349 - Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy:
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits. 350-355
Session 16: Secure and Trusted Systems
- Jérémie Clément, Bruno Mussard, David Naccache, Lionel Torres:
Implementation of AES Using NVM Memories Based on Comparison Function. 356-361 - Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre:
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. 362-367 - Yun Cheng, Ying Wang, Huawei Li, Xiaowei Li:
A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. 368-373
Session 17: Special Session: Software Engineering for VLSI and Embedded Systems
- Ciaran MacNamee, Donal Heffernan:
On-Chip Instrumentation for Runtime Verification in Deeply Embedded Processors. 374-379 - Raluca Marinescu, Eduard Paul Enoiu, Cristina Seceleanu:
Statistical Analysis of Resource Usage of Embedded Systems Modeled in EAST-ADL. 380-385 - Giuseppe Airo Farulla, Ludovico Orlando Russo, Vincenzo Gallifuoco, Marco Indaco:
A Novel Architectural Pattern to Support the Development of Human-Robot Interaction (HRI) Systems Integrating Haptic Interfaces and Gesture Recognition Algorithms. 386-391
Session 18: 3D and NoC Based Systems
- Kanchan Manna, Vadapalli Shanmukha Sri Teja, Santanu Chattopadhyay, Indranil Sengupta:
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning. 392-397 - Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen:
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. 398-403 - Alberto Saggio, Gaoming Du, Xueqian Zhao, Zhonghai Lu:
Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls. 404-409
Session 19: Embeded System Design
- Arthur Francisco Lorenzon, Anderson Luiz Sartor, Márcia C. Cera, Antonio Carlos Schneider Beck:
Optimized Use of Parallel Programming Interfaces in Multithreaded Embedded Architectures. 410-415 - Daniel Gregorek, Alberto García Ortiz:
The DRACON Embedded Many-Core: Hardware-Enhanced Run-Time Management Using a Network of Dedicated Control Nodes. 416-421 - Xueqian Zhao, Zhonghai Lu:
Backlog Bound Analysis for Virtual-Channel Routers. 422-427
Session 20: Digital System Design
- Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh:
A Timing Error Mitigation Technique for High Performance Designs. 428-433 - Hao Liu, Clement Devigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner:
RWT: Suppressing Write-Through Cost When Coherence is Not Needed. 434-439 - Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau:
Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). 440-445
Keynote 2
- Heike Riel:
The Future of Nanoelectronics: New Materials, Architectures and Devices. 446
Session 21: Special Session: Carbon-Based Materials for THz Nanoelectronics
- Sergey A. Maksimenko, Mikhail V. Shuba, P. P. Kuzhir, K. G. Batrakov, G. Y. Slepyan:
Challenges and Perspectives of Nanoelectromagnetics in the THz Range. 447-449 - Antonio Maffucci:
Semi-Classical Modelling of the Electron Transport in Carbon Nanotubes and Graphene Nanoribbons for THz Range Applications. 450-455 - M. E. Portnoi, V. A. Saroka, R. R. Hartmann, O. V. Kibis:
Terahertz Applications of Carbon Nanotubes and Graphene Nanoribbons. 456-459
Session 22: Special Session: Memory and Computing Units in Emerging Paradigm
- Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard:
Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture. 460 - Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao:
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. 461-466 - Elena-Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto:
STT-MRAM-Based Strong PUF Architecture. 467-472
Session 23: Special Session: Techniques and Trends for Energy Efficient and Ultra Low Power Digital
- Kaushik Roy, Anand Raghunathan:
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications. 473-475 - Jeremy Schlachter, Vincent Camus, Christian C. Enz:
Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems. 476-480 - Christian Piguet, Marc Pons, Daniel Séverac:
Sub-Threshold Design and Architectural Choices. 481-484
Session 24: Fault-Tolerant Design
- Anderson Luiz Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Gusmão de Lima Kastensmidt, Stephan Wong, Antonio Carlos Schneider Beck:
A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors. 485-490 - Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. 491-496 - Saha Mousumi, Biplab K. Sikdar:
A Cellular Automata Based Fault Tolerant Approach in Designing Test Hardware for L1 Cache Module. 497-502
Session 25: Test for Digital Design
- Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis of Delay Faults Considering Hazards. 503-508 - Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
DONUT: A Double Node Upset Tolerant Latch. 509-514 - Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch:
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. 515-520
Session 26: Reliable Design Techniques
- Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis:
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops. 521-526 - Marjan Asadinia, Hamid Sarbazi-Azad:
Using Intra-Line Level Pairing for Graceful Degradation Support in PCMs. 527-532 - Thiago Berticelli Lo, Fernanda Lima Kastensmidt, Antonio Carlos Schneider Beck:
Using Configurable Bit-Width Voters to Mask Multiple Errors in Integrated Circuits. 533-538
Session 27: Special Session: Efficient Design of Manycore Embedded Systems
- Imran Ashraf, Koen Bertels, Nader Khammassi, Jean-Christophe Le Lann:
Communication-Aware Parallelization Strategies for High Performance Applications. 539-544 - Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch, Guangjun Li:
Design of Fault-Tolerant and Reliable Networks-on-Chip. 545-550 - Anastasiia Butko, Abdoulaye Gamatié, Gilles Sassatelli, Lionel Torres, Michel Robert:
Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures. 551-556
Session 28: Special Session: Energy-Efficient Design Methods for Emerging Technologies
- Ghizlane Mouslih, Aida Todri-Sanial, Pascal Nouet:
On Analysis of On-chip DC-DC Converters for Power Delivery Networks. 557-560 - Zhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre, Ian O'Connor:
Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics. 561-566 - Elias Kougianos, Shital Joshi, Saraju P. Mohanty:
Multi-swarm Optimization of a Graphene FET Based Voltage Controlled Oscillator Circuit. 567-572
Session 29: Reliable Circuits and Systems
- Prateek Puri, Michael S. Hsiao:
Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization. 573-578 - Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Khalid Latif:
On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. 579-584 - Elena K. Weinberg, Mircea R. Stan:
SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications. 585-590
Session 30: Power and Noise Aware Systems
- Fernando Cladera Ojeda, Matthieu Gautier, Olivier Sentieys:
Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers. 591-596 - Yasuhiro Sugimoto:
The Solar Cells and the Battery Charger System Using the Fast and Precise Analog Maximum Power Point Tracking Circuits. 597-602
Session 31: Special Session: 3D Design Challenges and Perspectives
- Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel:
3D DFT Challenges and Solutions. 603-608 - Christian Weis, Matthias Jung, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson:
Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. 609-614 - Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy:
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. 615-620
Session 32: Special Session: Test, Calibration and Tuning of Analog/RF Circuits
- Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy. 621-626 - Athanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Salvador Mir:
Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors. 627 - Yichuan Lu, Kiruba S. Subramani, He Huang, Nathan Kupp, Yiorgos Makris:
Silicon Demonstration of Statistical Post-Production Tuning. 628-633
Session 33: Signal Converter Circuits
- Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard:
Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. 634-639 - Yanghyeok Choi, Seonghyun Park, Jieun Yoo, Seol Namgung, Minkyu Song:
A Full-Swing CMOS Current Steering DAC with an Adaptive Cell and a Quaternary Driver. 640-645 - Yngvar Berg, Omid Mirmotahari:
Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV. 646-651
Session 34: Analog Design and Test
- Afshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev:
A Linear Comparator-Based Fully Digital Delay Element. 652-655 - Jiafan Wang, Congyin Shi, Edgar Sánchez-Sinencio, Jiang Hu:
Built-In Self Optimization for Variation Resilience of Analog Filters. 656-661
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