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ORCIDHiroomi Hikawa
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2020 – today
- 2024
[j22]Takahiro Kawaguchi, Koki Ono, Hiroomi Hikawa
:
Electroencephalogram-Based Facial Gesture Recognition Using Self-Organizing Map. Sensors 24(9): 2741 (2024)- 2023
- [j21]Slavisa Jovanovic, Hiroomi Hikawa:
A Survey of Hardware Self-Organizing Maps. IEEE Trans. Neural Networks Learn. Syst. 34(11): 8154-8173 (2023) - 2021
- [j20]Hiroomi Hikawa:
Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1245-1258 (2021) - [c48]Yasuaki Kuroe, Seiji Miyoshi, Hiroomi Hikawa, Hidetaka Ito, Kimiko Motonaka, Yutaka Maeda:
A Synthesis Method of Spiking Neural Oscillators with Considering Asymptotic Stability. IJCNN 2021: 1-6 - 2020
- [c47]Hiroomi Hikawa:
Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors. ICECS 2020: 1-4
2010 – 2019
- 2019
- [c46]Hiroomi Hikawa:
Nested Hardware Architecture for Self-Organizing Map. IJCNN 2019: 1-7 - 2018
- [j19]Hiroomi Hikawa, Masayuki Tamaki, Hidetaka Ito:
Off-Chip Training with Additive Perturbation for FPGA-Based Hand Sign Recognition System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 499-506 (2018) - [j18]Yuto Kurosaki, Masayoshi Ohta, Hidetaka Ito, Hiroomi Hikawa:
SOM-Based Vector Recognition with Pre-Grouping Functionality. IEICE Trans. Inf. Syst. 101-D(6): 1657-1665 (2018) - [j17]Hidetaka Ito, Hiroomi Hikawa, Yutaka Maeda:
A Subspace Newton-Type Method for Approximating Transversely Repelling Chaotic Saddles. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1127-1131 (2018) - [c45]Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda:
A New Hardware Self-Organizing Map Architecture with High Expandability. IPAS 2018: 238-243 - [c44]Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda:
Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop. ISCAS 2018: 1-5 - [c43]Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda:
A New Self-Organizing Map with Continuous Learning Capability. SSCI 2018: 2163-2168 - 2016
- [c42]Hiroomi Hikawa:
Improved winner-take-all circuit for neural network based on frequency-modulated signals. ICECS 2016: 85-88 - [c41]Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa:
Gesture Spotting by Using Vector Distance of Self-organizing Map. ICONIP (2) 2016: 419-426 - [c40]Masayuki Tamaki, Hiroomi Hikawa:
Live demonstration: Off-chip learning for hardware hand-sign recognition system. ISCAS 2016: 451 - [c39]Masayuki Tamaki, Hiroomi Hikawa:
Off-chip learning for hardware hand-sign recognition system. ISCAS 2016: 2575-2578 - [c38]Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa:
Real time gesture recognition system with gesture spotting function. SSCI 2016: 1-7 - [c37]Masayoshi Ohta, Yuto Kurosaki, Hidetaka Ito, Hiroomi Hikawa:
Effect of grouping in vector recognition system based on SOM. SSCI 2016: 1-8 - 2015
- [j16]Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa:
Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting. IEICE Trans. Electron. 98-C(4): 356-363 (2015) - [j15]Masaki Azuma, Hiroomi Hikawa:
Scalable Hardware Winner-Take-All Neural Network with DPLL. IEICE Trans. Inf. Syst. 98-D(10): 1838-1846 (2015) - [j14]Hiroomi Hikawa, Keishi Kaida:
Novel FPGA Implementation of Hand Sign Recognition System With SOM-Hebb Classifier. IEEE Trans. Circuits Syst. Video Technol. 25(1): 153-166 (2015) - [j13]Hiroomi Hikawa, Yutaka Maeda:
Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function. IEEE Trans. Neural Networks Learn. Syst. 26(11): 2861-2873 (2015) - [c36]Hiroomi Hikawa:
Vector classification by a winner-take-all neural network with digital frequency-locked loop. IJCNN 2015: 1-8 - [c35]Hiroomi Hikawa:
Winner-take-all neural network with digital frequency-locked loop. ISCAS 2015: 2517-2520 - 2014
- [c34]Masaki Azuma, Hiroomi Hikawa:
Supervised learning of DPLL based winner-take-all neural network. ICES 2014: 117-124 - [c33]Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa:
Low-power wiring method in CMOS logics circuits by segmentation coding and pseudo majority voting. ISCAS 2014: 590-593 - 2013
- [c32]Hiroomi Hikawa:
DPLL based hardware SOM with a new winner-take-all circuit. IJCNN 2013: 1-8 - [c31]Naoki Terahara, Yoshiro Oba, Hiroomi Hikawa:
Color-space image compression with hardware Self-organizing map. ISPACS 2013: 11-16 - [c30]Masaki Azuma, Hiroomi Hikawa:
A new winner-take-all neural network using DPLL and phase modulated signal. ISPACS 2013: 345-350 - 2012
- [c29]Yusuke Araga, Makoto Shirabayashi, Keishi Kaida, Hiroomi Hikawa:
Real time gesture recognition system using posture classifier and Jordan recurrent neural network. IJCNN 2012: 1-8 - [c28]Yusuke Araga, Zuiko Rikuhashi, Hiroomi Hikawa:
Sequential vector classifier based on SOM and feedback Hebbian network. ISPACS 2012: 854-859 - 2011
- [j12]Hiroomi Hikawa:
ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(7): 1581-1584 (2011) - [c27]Yutaka Maeda, Takahiro Yamada, Seiji Miyoshi, Hiroomi Hikawa:
Learning Scheme for Complex Neural Networks Using Simultaneous Perturbation. ICANN (2) 2011: 462-469 - [c26]Hiroomi Hikawa, Yusuke Araga:
Study on gesture recognition system using posture classifier and Jordan recurrent neural network. IJCNN 2011: 405-412 - [c25]Yoshiro Oba, Kota Yamamoto, Takahiro Nagai, Hiroomi Hikawa:
Hardware design of a color quantization with self-organizing map. ISPACS 2011: 1-6 - [c24]Kota Yamamoto, Yoshiro Oba, Zuiko Rikuhashi, Hiroomi Hikawa:
Automatic generation of hardware self-organizing map for FPGA implementation. ISPACS 2011: 1-6 - [c23]Hiroomi Hikawa, Keishi Kaida:
Hand sign recognition system based on SOM-Hebb hybrid network. SMC 2011: 265-270 - 2010
- [c22]Hiroomi Hikawa, Kenji Doumoto, Simone Miyoshi, Yutaka Maeda:
Image compression with hardware self-organizing map. IJCNN 2010: 1-8 - [c21]Hiroomi Hikawa, Seito Yamazaki, Tatsuya Ando, Simone Miyoshi, Yutaka Maeda:
Comparison of range check classifier and hybrid network classifier for hand sign recognition system. IJCNN 2010: 1-8 - [c20]Hiroomi Hikawa, Taketo Namba:
Phase amplitude converter with conditional shift operation. ISCAS 2010: 3008-3011
2000 – 2009
- 2009
- [j11]Seiji Miyoshi, Hiroomi Hikawa, Yutaka Maeda:
Statistical Mechanical Analysis of Simultaneous Perturbation Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1743-1746 (2009) - [c19]Yutaka Maeda, Naoto Matsushita, Seiji Miyoshi, Hiroomi Hikawa:
On simultaneous perturbation particle swarm optimization. IEEE Congress on Evolutionary Computation 2009: 3271-3276 - [c18]Akira Onoo, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda:
On automatic generation of VHDL code for self-organizing map. IJCNN 2009: 2366-2373 - [c17]Yuuki Taki, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda:
Hand sign recognition system based on hybrid network classifier. IJCNN 2009: 3074-3081 - [c16]Hiroomi Hikawa:
DDFS with New Sinusoid Approximation based on Harmonics Removal. ISCAS 2009: 1751-1754 - 2008
- [c15]Hiroomi Hikawa, Hirotada Fujimura:
Hardware Design of Japanese Hand Sign Recognition System. ICONIP (2) 2008: 835-842 - 2007
- [j10]Hiroomi Hikawa, Kazutoshi Harada, Takenori Hirabayashi:
Hardware Feedback Self-Organizing Map and its Application to Mobile Robot Location Identification. J. Adv. Comput. Intell. Intell. Informatics 11(8): 937-945 (2007) - [c14]Hiroomi Hikawa, Kaori Kugimiya:
A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers. ICONIP (2) 2007: 137-146 - [c13]Hirotada Fujimura, Yuuichi Sakai, Hiroomi Hikawa:
Japanese Hand Sign Recognition System. ICONIP (1) 2007: 983-992 - [c12]Hiroomi Hikawa, Shigeki Matsubara:
Pseudo RBF Network for Position Independent Hand Posture Recognition System. IJCNN 2007: 1049-1054 - [c11]Hiroomi Hikawa, Taku Miyanishi, Kousuke Tamaya:
Performance Comparison of SOM Based Hybrid Hardware Classifiers. IJCNN 2007: 1091-1096 - 2006
- [c10]Hiroomi Hikawa:
Vector Quantization System Based on Scalar SOM/AND-OR Hybrid Network. IJCNN 2006: 1489-1496 - 2005
- [j9]Hiroomi Hikawa:
FPGA implementation of self organizing map with digital phase locked loops. Neural Networks 18(5-6): 514-522 (2005) - [c9]Shigeki Matsubara, Hiroomi Hikawa:
Hardware friendly vector quantization algorithm. ISCAS (4) 2005: 3623-3626 - 2004
- [c8]Hiroomi Hikawa:
Direct digital frequency synthesizer with multi-stage linear interpolation. ISCAS (4) 2004: 233-236 - 2003
- [j8]Hiroomi Hikawa:
A multilayer neural network with pulse position modulation. Syst. Comput. Jpn. 34(13): 36-46 (2003) - [j7]Hiroomi Hikawa:
A new digital pulse-mode neuron with adjustable activation function. IEEE Trans. Neural Networks 14(1): 236-242 (2003) - [j6]Hiroomi Hikawa:
A digital hardware pulse-mode neuron with piecewise linear activation function. IEEE Trans. Neural Networks 14(5): 1028-1037 (2003) - [c7]Hiroomi Hikawa:
Pulse mode neuron with leakage integrator and additive random noise. ISCAS (5) 2003: 821-824 - 2001
- [c6]Hiroomi Hikawa:
Digital pulse mode neural network with simple synapse multiplier. ISCAS (3) 2001: 569-572 - 2000
- [j5]Hiroomi Hikawa:
An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation. Syst. Comput. Jpn. 31(4): 43-51 (2000) - [c5]Hiroomi Hikawa:
Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning. IJCNN (2) 2000: 71-80 - [c4]Hiroomi Hikawa:
Pulse mode multilayer neural network based on floating point number representation. ISCAS 2000: 145-148
1990 – 1999
- 1999
- [j4]Kazuo Sato, Hiroomi Hikawa:
Implementation of multilayer neural network with threshold neurons and its analysis. Artif. Life Robotics 3(3): 170-175 (1999) - [j3]Hiroomi Hikawa:
Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics. IEEE Trans. Neural Networks 10(3): 545-553 (1999) - [c3]Hiroomi Hikawa:
An efficient pulse mode multilayer neural network. ISCAS (5) 1999: 367-370 - 1995
- [c2]Hiroomi Hikawa:
Implementation of simplified multilayer neural networks with on-chip learning. ICNN 1995: 1633-1637 - 1994
- [c1]Vijay K. Jain, Hiroomi Hikawa:
Parallel Architecture for Universal Digital Signal Processing. HICSS (1) 1994: 114-123 - 1992
- [j2]Vijay K. Jain, Hiroomi Hikawa, David C. Keezer:
An Architecture for WSI Rapid Prototyping. Computer 25(4): 71-75 (1992) - [j1]Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa:
A radix-8 wafer scale FFT processor. J. VLSI Signal Process. 4(2-3): 165-176 (1992)
Coauthor Index
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last updated on 2024-10-07 21:23 CEST by the dblp team
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