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ORCIDLoganathan Lingappan
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2010 – 2019
- 2018
[c16]Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan:
An online framework for diagnosis of multiple defects in scan chains. ISQED 2018: 162-168- [c15]I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram:
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. ITC 2018: 1-10 - 2017
- [c14]Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan:
A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults. ACM Great Lakes Symposium on VLSI 2017: 455-458 - 2016
- [c13]Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan:
Hardware-in-the-loop model-less diagnostic test generation. HLDVT 2016: 128-135 - 2015
- [c12]Sarmad Tanwir, Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan:
Information-theoretic and statistical methods of failure log selection for improved diagnosis. ITC 2015: 1-10 - 2013
- [c11]Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
Test generation for circuits with embedded memories using SMT. ETS 2013: 1 - 2012
- [c10]Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
A Novel SMT-Based Technique for LFSR Reseeding. VLSI Design 2012: 394-399 - [c9]Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
A SMT-based diagnostic test generation method for combinational circuits. VTS 2012: 215-220 - 2011
- [j7]Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan:
Strategies for scalable symbolic execution-driven test generation for programs. Sci. China Inf. Sci. 54(9): 1797-1812 (2011) - [c8]Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy:
An Efficient 2-Phase Strategy to Achieve High Branch Coverage. Asian Test Symposium 2011: 167-174 - 2010
- [c7]Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan:
Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs. Asian Test Symposium 2010: 59-64
2000 – 2009
- 2009
- [j6]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty:
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 697-708 (2009) - 2007
- [j5]Loganathan Lingappan, Niraj K. Jha:
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1339-1345 (2007) - [j4]Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 24-36 (2007) - [j3]Loganathan Lingappan, Niraj K. Jha:
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 518-530 (2007) - [c6]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha:
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design 2007: 504-512 - 2006
- [j2]Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 544-557 (2006) - [j1]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan
, Niraj K. Jha, Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2193-2206 (2006) - [c5]Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
Test generation for combinational quantum cellular automata (QCA) circuits. DATE 2006: 311-316 - [c4]Loganathan Lingappan, Niraj K. Jha:
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. VLSI Design 2006: 431-436 - 2005
- [c3]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70 - [c2]Loganathan Lingappan, Niraj K. Jha:
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. VTS 2005: 418-423 - 2003
- [c1]Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD 2003: 187-193
Coauthor Index
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