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2020 – today
- 2025
[j68]Aasish Boora
, Bharatha Kumar Thangarasu, Kiat Seng Yeo:
A dB-Linear Programmable Gain Amplifier With Mixed-Signal Control for Wide-Gain Range and Low-Power Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 72(1): 61-70 (2025)- 2024
- [j67]Zenglong Zhao, Xianghui Chen, Fanyi Meng, Kaixue Ma, Kiat Seng Yeo:
A 211.4-to-234.8 GHz 25.6-dB Differential Amplifier With Compact Terminal Multi-Coupled and Auxiliary Interstage-Coupled Matching Networks. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1017-1021 (2024) - [j66]Genyin Ma, Fanyi Meng, Keping Wang, Kaixue Ma, Kiat Seng Yeo:
A S/C-Band 5-Bit Passive Attenuator With Phase-Lead Compensation in 55-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1082-1085 (2024) - [j65]Bing Liu, Fanyi Meng, Zonglin Ma, Kiat Seng Yeo, Kaixue Ma:
A 28/39 GHz Tri-Mode Frequency-Reconfigurable LNA for Multiband 5G Communications. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4036-4040 (2024) - [c90]Sezin Kircali Ata, Zhi-Hui Kong, Anusha James, Lile Cai, Kiat Seng Yeo, Khin Mi Mi Aung, Chuan Sheng Foo, Ashish James:
Towards Safe and Efficient Analog Circuit Design: Active Learning for Feasibility Region Exploration. APCCAS 2024: 193-197 - [c89]Sezin Kircali Ata, Zhi-Hui Kong, Anusha James, Lile Cai, Kiat Seng Yeo, Khin Mi Mi Aung, Chuan Sheng Foo, Ashish James:
The Initialization Factor: Understanding its Impact on Active Learning for Analog Circuit Design. ISCAS 2024: 1-5 - 2023
- [j64]J. Jithish, Bithin Alangot, Nagarajan Mahalingam, Kiat Seng Yeo:
Distributed Anomaly Detection in Smart Grids: A Federated Learning-Based Approach. IEEE Access 11: 7157-7179 (2023) - [j63]Liying Cai, Xiong Song, Zhenghao Lu, Xiao-Peng Yu, Kiat Seng Yeo, Jer-Ming Chen, Bharatha Kumar Thangarasu:
A Linear-in-Decibel Automatic Gain Control Amplifier With Dual Mode Continuous Gain Tuning. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2752-2761 (2023) - [c88]Peerapat Phetpadriew, Bharatha Kumar Thangarasu, Nagarajan Mahalingam, Zhenghao Lu, Cher Ming Tan, Kiat Seng Yeo:
Concurrent Multiband CMOS Low Noise Amplifier Design for Internet of Things Applications. ASICON 2023: 1-4 - 2021
- [j62]Lang Chen, Hang Liu, Jefferson A. Hora, J. Andrew Zhang, Kiat Seng Yeo, Xi Zhu:
A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off. IEEE J. Solid State Circuits 56(5): 1553-1564 (2021) - [j61]Haowei Lu, Xiao-Peng Yu, Si-Qi Wang, Yu-Yan Liu, Zhenyan Huang, Zhenghao Lu, Kiat Seng Yeo, Jer-Ming Chen:
A digital background calibration scheme for non-linearity of SAR ADC using back-propagation algorithm. Microelectron. J. 114: 105113 (2021) - [j60]Hang Liu, Xi Zhu, Yisheng Wang, Kai Men, Kiat Seng Yeo:
A 60 GHz 8-Way Combined Power Amplifier in 0.18 μm SiGe BiCMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1847-1851 (2021) - [j59]Bithin Alangot, Daniël Reijsbergen, Sarad Venugopalan, Pawel Szalachowski, Kiat Seng Yeo:
Decentralized and Lightweight Approach to Detect Eclipse Attacks on Proof of Work Blockchains. IEEE Trans. Netw. Serv. Manag. 18(2): 1659-1672 (2021) - [c87]Thurein Aung, Mahalingam Nagarajan, Kiat Seng Yeo:
A New Degeneration Technique for 60 GHz Triple Cascode Wideband Low Noise Amplifier. ASICON 2021: 1-4 - 2020
- [j58]Haowei Lu, Xiao-Peng Yu, Zhenghao Lu, Kiat Seng Yeo, Jer-Ming Chen:
A data-dependent energy reduction algorithm for SAR ADC using self-adaptive window. Microelectron. J. 100: 104754 (2020) - [j57]Lingshan Kong, Hang Liu, Xi Zhu, Chirn Chye Boon, Chenyang Li, Zhe Liu, Kiat Seng Yeo:
Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. 67-I(12): 4187-4198 (2020) - [c86]Aasish Boora, Bharatha Kumar Thangarasu, Kiat Seng Yeo:
An Ultra-Low Power 900 MHz Intermediate Frequency Low Noise Amplifier For Low-Power RF Receivers. SoCC 2020: 163-167
2010 – 2019
- 2019
- [j56]Nagarajan Mahalingam, Kaixue Ma, Kiat Seng Yeo:
A Multi-Mode Multi-Coil Coupled Tuned Inductive Peaking ILFD for Low Injected Power With Compact Size. IEEE Access 7: 59059-59068 (2019) - [j55]Xiong Song, Zhenghao Lu, Liying Cai, Xiaopeng Yu, Kiat Seng Yeo, Jer-Ming Chen:
A Wideband dB-Linear VGA With Temperature Compensation and Active Load. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3279-3287 (2019) - [j54]Yun Fang, Zhong Tang, Xiao-Peng Yu, Zheng Shi, Kiat Seng Yeo:
A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2954-2958 (2019) - [c85]Bai Song Samuel Lee, Hang Liu, Xiaopeng Yu, Jer-Ming Chen, Kiat Seng Yeo:
An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS. ASICON 2019: 1-4 - [c84]Bai Song Samuel Lee, Hang Liu, Kiat Seng Yeo:
An Inductorless 6-GHz Variable Gain Differential Transimpedance Amplifier in 0.18-μm SiGe BiCMOS. ISCAS 2019: 1-5 - [c83]Xi Sung Loo, Kiat Seng Yeo, Moe Z. Win, Zhichao Li, Xiaopeng Yu, Jer-Ming Chen:
A K-Band Differential SiGe Stacked Power Amplifier Based on Capacitive Compensation Techniques for Gain Enhancements. MWSCAS 2019: 295-298 - [c82]Xi Sung Loo, Moe Z. Win, Kiat Seng Yeo, Wanlan Yang:
Millimeter-wave Sine Corrugated Fermi Tapered Slot Antenna Array Based on Partial Synthesized Dielectric. RWS 2019: 1-4 - 2018
- [j53]Yun Fang, Xiaopeng Yu, Zheng Shi, Kiat Seng Yeo:
A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS. Integr. 63: 87-92 (2018) - [j52]Qi-Lin Qiu, Xiaopeng Yu, Wen-quan Sui, Kiat Seng Yeo:
Design and optimization of the ring oscillator based injection locked frequency dividers. Microelectron. J. 72: 40-48 (2018) - [c81]Denise Lee, Mei Yu Soh, Tee Hui Teo, Kiat Seng Yeo:
Evaluation of Low Voltage Rectifier Design Using IGBT, MOSFET, and GaN FETs. TENCON 2018: 389-393 - [c80]Mei Yu Soh, Wen Xian Ng, Qiong Zou, Denise Lee, Tee Hui Teo, Kiat Seng Yeo:
Low-cost Real-time Video Streaming System Using Off-the-Shelf LEDs. TENCON 2018: 1774-1777 - [c79]Denise Lee, Mei Yu Soh, Tee Hui Teo, Kiat Seng Yeo:
Precompliance Test Setup for Pyroelectric Sensor Devices in IoT Applications. TENCON 2018: 2075-2079 - [c78]Mei Yu Soh, Wen Xian Ng, Qiong Zou, Denise Lee, Tee Hui Teo, Kiat Seng Yeo:
Real-Time Audio Transmission Using Visible Light Communication. TENCON 2018: 2223-2226 - 2017
- [j51]Xiaopeng Yu, Zhe Liu, De Zhang Fan, Kiat Seng Yeo:
The Investigation and Optimisation of Phase-Induced Amplitude Attenuation in the Injection-Locked Ring Oscillators-Based Receiver. Circuits Syst. Signal Process. 36(5): 1818-1835 (2017) - [c77]Kiat Seng Yeo, Wen Xian Ng, Mei Yu Soh, Tee Hui Teo:
Micro-LED arrays for display and communication: Device structure and driver architecture. ASICON 2017: 993-996 - [c76]Jinna Yan, Bharatha Kumar Thangarasu, Kiat Seng Yeo:
RF mixer design techniques using GaAs process. ASICON 2017: 1013-1016 - 2016
- [j50]Xiaopeng Yu, Wen Lin Xu, Chen Feng, Zhenghao Lu, Wei Meng Lim, Kiat Seng Yeo:
A 11.2 mW 48-62 GHz Low Noise Amplifier in 65 nm CMOS Technology. Circuits Syst. Signal Process. 35(5): 1531-1543 (2016) - [j49]Fanyi Meng, Kaixue Ma, Kiat Seng Yeo, Shanshan Xu:
A 57-to-64-GHz 0.094-mm2 5-bit Passive Phase Shifter in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1917-1925 (2016) - [c75]Bai Song Samuel Lee, Yung Sern Tan, Bharatha Kumar Thangarasu, Kiat Seng Yeo, Zhichao Li, Xiaopeng Yu:
An inductorless transimpedance amplifier design for 10 Gb/s optical communication using 0.18-µm CMOS. ISIC 2016: 1-4 - [c74]Zhichao Li, Bharatha Kumar Thangarasu, Xiaopeng Yu, Kiat Seng Yeo:
A 60-GHz power amplifier with efficiency enhancement at power back-off. ISIC 2016: 1-3 - [c73]Muting Lu, Bharatha Kumar Thangarasu, Dawei Zhang, Xiaopeng Yu, Kiat Seng Yeo:
A wideband digital variable gain amplifier with DC offset cancellation in SiGe 0.18µm BiCMOS technology. ISIC 2016: 1-3 - [c72]Bo Yu, Kaixue Ma, Fanyi Meng, Bharatha Kumar Thangarasu, Kiat Seng Yeo:
DC-50 GHz low loss switch matrix design in high resistivity trap-rich SOI. ISIC 2016: 1-3 - [c71]Dawei Zhang, Hongxi Yu, Bharatha Kumar Thangarasu, Kai Men, Muting Lu, Xiaopeng Yu, Kiat Seng Yeo:
Design of millimeter-wave transformer balun with isolation circuit in silicon based technology. ISIC 2016: 1-3 - [c70]Xi Sung Loo, Kok Wai Johnny Chew, Michael Cheng, Kiat Seng Yeo:
Millimetre-wave performance of passive microstrip bandpass filters based on 40nm CMOS technology. MWSCAS 2016: 1-4 - 2015
- [j48]Qiong Zou, Kaixue Ma, Kiat Seng Yeo:
A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 554-563 (2015) - [j47]Wanxin Ye, Kaixue Ma, Kiat Seng Yeo, Qiong Zou:
A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2533-2543 (2015) - [c69]Peng Siew Chew, Kiat Seng Yeo, Kaixue Ma, Zhi-Hui Kong:
A 57 to 66 GHz novel six-port correlator. ASICON 2015: 1-4 - [c68]Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. ISCAS 2015: 794-797 - [c67]Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation. ISCAS 2015: 2553-2556 - [c66]Fanyi Meng, Kaixue Ma, Kiat Seng Yeo:
2.3 A 130-to-180GHz 0.0035mm2 SPDT switch with 3.3dB loss and 23.7dB isolation in 65nm bulk CMOS. ISSCC 2015: 1-3 - [c65]Wanxin Ye, Kaixue Ma, Kiat Seng Yeo:
2.5 A 2-to-6GHz Class-AB power amplifier with 28.4% PAE in 65nm CMOS supporting 256QAM. ISSCC 2015: 1-3 - 2014
- [j46]Y. X. Zhang, Chirn Chye Boon, Kiat Seng Yeo:
Design and Analysis of a 2.4 GHz Hybrid Type Automatic amplitude Control VCO with Forward noise Reduction. J. Circuits Syst. Comput. 23(4) (2014) - [j45]Anh-Tuan Do, Chun Yin, Kavitha Velayudhan, Zhao Chuan Lee, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance. IEEE J. Solid State Circuits 49(7): 1487-1498 (2014) - [j44]Wei Fei, Hao Yu, Haipeng Fu, Junyan Ren, Kiat Seng Yeo:
Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 699-711 (2014) - [j43]Bo Yu Hu, Xiaopeng Yu, Wei Meng Lim, Kiat Seng Yeo:
Analysis and Design of Ultra-Wideband Low-Noise Amplifier With Input/Output Bandwidth Optimization and Single-Ended/Differential-Input Reconfigurability. IEEE Trans. Ind. Electron. 61(10): 5672-5680 (2014) - [c64]Anh-Tuan Do, Kiat Seng Yeo:
A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications. ISCAS 2014: 2393-2396 - [c63]Kiat Seng Yeo, Mojy Curtis Chian, Tony Chon Wee Ng, Anh-Tuan Do:
Internet of Things: Trends, challenges and applications. ISIC 2014: 568-571 - [c62]Xiwei Huang, Fei Wang, Jing Guo, Mei Yan, Hao Yu, Kiat Seng Yeo:
A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing. VLSIC 2014: 1-2 - 2013
- [j42]Xiaopeng Yu, Zhenghao Lu, Bo Yu Hu, Wei Meng Lim, Er Tai Duo, Kiat Seng Yeo:
A 12-mW 40-60-GHz 0.18- $\mu {\hbox {m}}$ BiCMOS Oscillator-Less Self-Demodulator for Short-Range Software-Defined Transceivers. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(4): 521-530 (2013) - [j41]Mahalingam Nagarajan, Kaixue Ma, Kiat Seng Yeo, Wei Meng Lim:
A Low Power Push-Push VCO using Multi-Coupled LC Tanks. J. Circuits Syst. Comput. 22(10) (2013) - [j40]Keping Wang, Xuemei Lei, Kaixue Ma, Kiat Seng Yeo, Xiang Cao, Zhigong Wang:
A CMOS Low-Power temperature-robust RSSI using Weak-Inversion limiting amplifiers. J. Circuits Syst. Comput. 22(10) (2013) - [j39]Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo:
A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 37-50 (2013) - [j38]Nagarajan Mahalingam, Kaixue Ma, Kiat Seng Yeo, Wei Meng Lim:
K-band High-PAE Wide-Tuning-Range VCO Using Triple-Coupled LC Tanks. IEEE Trans. Circuits Syst. II Express Briefs 60-II(11): 736-740 (2013) - [j37]Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 151-156 (2013) - [j36]Dandan Chen, Kiat Seng Yeo, Xiaomeng Shi, Manh Anh Do, Chirn Chye Boon, Wei Meng Lim:
Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1516-1525 (2013) - [c61]Nagarajan Mahalingam, Yisheng Wang, Kaixue Ma, Shouxian Mou, Kiat Seng Yeo:
A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPAN. ASICON 2013: 1-4 - [c60]Anh Tuan Do, Chun Yin, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design of a power-efficient CAM using automated background checking scheme for small match line swing. ESSCIRC 2013: 209-212 - [c59]Anh-Tuan Do, Karthik G. Jayaraman, Pushpapraj Singh, Chua Geng Li, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset. ESSDERC 2013: 284-287 - [c58]Anh-Tuan Do, Yung Sern Tan, Gordon M. Xiong, Cleo Choong, Zhi-Hui Kong, Kiat Seng Yeo:
A current-mode stimulator circuit with two-step charge balancing background calibration. ISCAS 2013: 409-412 - [c57]Anh-Tuan Do, Karthik G. Jayaraman, Vincent Pott, Chua Geng Li, Pushpapraj Singh, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory. ISCAS 2013: 1456-1459 - [c56]Lih Chieh Png, Long Xiao, Kiat Seng Yeo, Thin Sek Wong, Yong Liang Guan:
MIMO-diversity switching techniques for digital transmission in visible light communication. ISCC 2013: 576-582 - [c55]Lih Chieh Png, Kiat Seng Yeo:
Optical infrastructure for visible light communication for public housing and commercial buildings. ISCC 2013: 934-939 - [c54]Whye Seng Chong, Yung Sern Tan, Kiat Seng Yeo:
A low power wideband differential transimpedance amplifier for optical receivers in 0.18-μm CMOS. NEWCAS 2013: 1-4 - 2012
- [j35]Pak Kwong Chan, Chip-Hong Chang, Kiat Seng Yeo:
Foreword. J. Circuits Syst. Comput. 21(8) (2012) - [j34]Shouxian Mou, Kaixue Ma, Kiat Seng Yeo:
A robust 900 MHz RFID Reader Chip with RC-Calibration. J. Circuits Syst. Comput. 21(8) (2012) - [j33]Juan Xie, Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo:
A low power low phase noise dual-band multiphase VCO. Microelectron. J. 43(12): 1016-1022 (2012) - [j32]Qiong Zou, Kaixue Ma, Kiat Seng Yeo, Wei Meng Lim:
Design of a Ku-band Low-Phase-Noise VCO Using the Dual LC Tanks. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 262-266 (2012) - [j31]Yung Sern Tan, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do:
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1156-1167 (2012) - [j30]Anh-Tuan Do, Truc Quynh Nguyen, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 868-872 (2012) - [j29]Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo:
A Low-Power Single-Phase Clock Multiband Flexible Divider. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 376-380 (2012) - [j28]Wei Fei, Hao Yu, Wei Zhang, Kiat Seng Yeo:
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1012-1025 (2012) - [c53]Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Lei Yao, Meng Tong Tan, Minkyu Je:
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. APCCAS 2012: 1-4 - [c52]Tongxi Wang, Xiwei Huang, Mei Yan, Hao Yu, Kiat Seng Yeo, Ismail Cevik, Suat U. Ay:
A 96×96 1V ultra-low power CMOS image sensor for biomedical application. APCCAS 2012: 13-16 - [c51]Xiaodan Zou, Lei Liu, Yung Sern Tan, Minkyu Je, Kiat Seng Yeo:
Integrated circuits design for neural recording sensor interface. APCCAS 2012: 17-20 - [c50]Bharatha Kumar Thangarasu, Kaixue Ma, Kiat Seng Yeo, Wei Meng Lim:
A 12-GHz high output power amplifier using 0.18µm SiGe BiCMOS for low power applications. APCCAS 2012: 180-183 - [c49]Jiang An Han, Zhi-Hui Kong, Kaixue Ma, Kiat Seng Yeo:
Recent progress in silicon-based millimeter-wave power amplifier. APCCAS 2012: 184-187 - [c48]Kaixue Ma, Shouxian Mou, Kiat Seng Yeo, Wei Meng Lim:
On-chip tunable low pass filter with improved stopband using new cross coupled topology. APCCAS 2012: 188-191 - [c47]Qiong Zou, Kaixue Ma, Wanxin Ye, Kiat Seng Yeo:
A low power millimetre-wave VCO in 0.18 µm SiGe BiCMOS technology. APCCAS 2012: 244-247 - [c46]Fanyi Meng, Kaixue Ma, Shanshan Xu, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim, Manh Anh Do:
Design of quarter-wavelength resonator filters with coupling controllable paths. APCCAS 2012: 248-251 - [c45]Wanlan Yang, Kaixue Ma, Kiat Seng Yeo, Wei Meng Lim:
A 60GHz on-chip antenna in standard CMOS silicon Technology. APCCAS 2012: 252-255 - [c44]Keping Wang, Kaixue Ma, Kiat Seng Yeo:
Low-power high-speed dual-modulus prescaler for Gb/s applications. APCCAS 2012: 256-259 - [c43]Tongxi Wang, Xiwei Huang, Qixiang Jia, Mei Yan, Hao Yu, Kiat Seng Yeo:
A super-resolution CMOS image sensor for bio-microfluidic imaging. BioCAS 2012: 388-391 - [c42]Mei Yan, Xiwei Huang, Qixiang Jia, Revanth Nadipalli, Tongxi Wang, Yang Shang, Hao Yu, Minkyu Je, Kiat Seng Yeo:
High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system. Sensors, Cameras, and Systems for Industrial and Scientific Applications 2012: 829804 - [c41]Lih Chieh Png, Nhat Le Minh, Liangquan Chen, Kiat Seng Yeo:
Designs of a free-space white-LED mass-storage transceiver for SD-card file transfer. GLOBECOM Workshops 2012: 1260-1263 - [c40]Zhong Qiang Ding, Kiat Seng Yeo:
An optimum RF link for implantable devices with rectification of transmission errors. ISOCC 2012: 379-382 - [c39]Haitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu:
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. ISOCC 2012: 383-386 - [c38]Anh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo:
Low power implantable neural recording front-end. ISOCC 2012: 387-390 - [c37]Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Xiaodan Zou, Lei Yao, Kuang-Wei Cheng, Minkyu Je:
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. NEWCAS 2012: 525-528 - 2011
- [j27]Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo:
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1252-1263 (2011) - [j26]Keping Wang, Zhigong Wang, Xuemei Lei, Xiang Cao, Peng Han, Geliang Yang, Kaixue Ma, Kiat Seng Yeo:
A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 729-733 (2011) - [j25]Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo:
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 1-9 (2011) - [j24]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low:
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 196-204 (2011) - [c36]Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo:
A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. A-SSCC 2011: 141-144 - [c35]Xiaoliang Tan, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo, Zhi-Hui Kong:
A new match line sensing technique in Content Addressable Memory. COOL Chips 2011: 1-3 - [c34]Anh-Tuan Do, Xiaoliang Tan, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. ACM Great Lakes Symposium on VLSI 2011: 371-374 - [c33]Ali Meaamar, Chirn Chye Boon, Xiaomeng Shi, Wei Meng Lim, Kiat Seng Yeo, Manh Anh Do:
A 3.1-8 GHz CMOS UWB front-end receiver. ISCAS 2011: 1556-1559 - [c32]Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A low-power CAM with efficient power and delay trade-off. ISCAS 2011: 2573-2576 - [c31]Kaixue Ma, Shouxian Mou, Yang Lu, Kok Meng Lim, Kiat Seng Yeo:
A 60GHz defected ground power divider using SiGe BiCMOS technology. ISOCC 2011: 1-4 - [c30]Keping Wang, Kaixue Ma, Kiat Seng Yeo:
Design consideration for 60 GHz SiGe power amplifier with ESD protection. ISOCC 2011: 5-8 - [c29]Bharatha Kumar Thangarasu, Kaixue Ma, Kiat Seng Yeo, Shouxian Mou, Mahalingam Nagarajan:
A DC to 14GHz fully differential amplifier for wideband low power applications. ISOCC 2011: 9-12 - [c28]Renjing Pan, Jiangmin Gu, Kiat Seng Yeo, Wei Meng Lim, Kaixue Ma:
SiGe BiCMOS power amplifiers for 60GHz ISM band applications. ISOCC 2011: 13-16 - [c27]Fanyi Meng, Kiat Seng Yeo, Shanshan Xu, Kaixue Ma, Chee Chong Lim:
Wide center-tape balun for 60 GHz silicon RF ICs. ISOCC 2011: 17-19 - [c26]Jinna Yan, Kok Meng Lim, Jiangmin Gu, Keping Wang, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo:
A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process. ISOCC 2011: 246-249 - [c25]Kok Meng Lim, Jiangmin Gu, Jinna Yan, Wei Meng Lim, Yang Lu, Kiat Seng Yeo:
Ultra low power active 60 GHz Bi-CMOS down-conversion mixer. ISOCC 2011: 254-257 - [c24]Zhenghao Lu, Xiaopeng Yu, Kiat Seng Yeo, Wei Meng Lim, Jinna Yan, Renjing Pan:
A 60GHz BiCMOS self-demodulator with injection locked oscillator. ISOCC 2011: 258-261 - [c23]Ning Zhu, Wang Ling Goh, Kiat Seng Yeo:
Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications. ISOCC 2011: 393-396 - [c22]Fanyi Meng, Kiat Seng Yeo, Shanshan Xu, Kaixue Ma, Chee Chong Lim:
Wide center-tape balun for 60 GHz silicon RF ICs. ISOCC 2011: 454-456 - [c21]Shouxian Mou, Kaixue Ma, Kiat Seng Yeo, Nagarajan Mahalingam, Bharatha Kumar Thangarasu:
A low power wide tuning range VCO with coupled LC tanks. SoCC 2011: 52-56 - [c20]Myat Thu Linn Aung, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo:
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. VLSI-SoC 2011: 66-71 - 2010
- [j23]Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim:
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 72-82 (2010) - [j22]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo:
Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 83-92 (2010) - [j21]Ali Meaamar, Chirn Chye Boon, Kiat Seng Yeo, Manh Anh Do:
A Wideband Low Power Low-Noise Amplifier in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(4): 773-782 (2010) - [j20]Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk:
An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2675-2684 (2010) - [j19]Zhenghao Lu, Kiat Seng Yeo, Wei Meng Lim, Manh Anh Do, Chirn Chye Boon:
Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 461-472 (2010) - [j18]Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat Seng Yeo, Zhi-Hui Kong:
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1225-1229 (2010) - [c19]Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong:
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. APCCAS 2010: 704-707 - [c18]Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
Low IR drop and low power parallel CAM design using gated power transistor technique. APCCAS 2010: 708-711 - [c17]Kok Meng Lim, Jiangmin Gu, Yang Lu, Jinna Yan, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo:
Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power. ICECS 2010: 511-514 - [c16]Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo:
A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. VLSI-SoC (Selected Papers) 2010: 1-21 - [c15]Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do:
A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4. VLSI-SoC (Selected Papers) 2010: 69-99 - [c14]Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk:
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. VLSI-SoC 2010: 381-386 - [c13]Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do:
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. VLSI-SoC 2010: 387-391
2000 – 2009
- 2008
- [j17]Kiat Seng Yeo, Zhi-Hui Kong, Nukala Nishant, Haitao Fu, Wei Zeng:
Integrated Circuit Design Research Ranking for Worldwide Universities. J. Circuits Syst. Comput. 17(1): 141-167 (2008) - [j16]Kiat Seng Yeo, Zhi-Hui Kong:
Spicesoft: Automated Tool for Sensitivity Analysis, Performance Analysis, and Inverse Performance Analysis of Digital Circuits. J. Circuits Syst. Comput. 17(2): 221-238 (2008) - [j15]Shan Jiang, Manh Anh Do, Kiat Seng Yeo, Wei Meng Lim:
An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1430-1440 (2008) - [j14]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo:
Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 986-990 (2008) - [j13]Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 922-926 (2008) - [c12]Liang-Yu Loy, Weija Zhang, Zhi-Hui Kong, Wang Ling Goh, Kiat Seng Yeo:
Body-bootstrapped-buffer circuit for CMOS static power reduction. APCCAS 2008: 842-845 - [c11]Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo, Joshua Yung Low Yung Lih:
A full current-mode sense amplifier for low-power SRAM applications. APCCAS 2008: 1402-1405 - 2007
- [j12]Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do:
Distortion of pulsed signals in carbon nanotube interconnects. Microelectron. J. 38(3): 365-370 (2007) - [j11]Zhenghao Lu, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Wei Meng Lim, Xueying Chen:
Broad-Band Design Techniques for Transimpedance Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(3): 590-600 (2007) - 2006
- [j10]J. J. Liu, Manh Anh Do, Xiaopeng Yu, Kiat Seng Yeo, Shan Jiang, Jianguo Ma:
Cmos Even Harmonic Switching mixer for Direct Conversion Receivers. J. Circuits Syst. Comput. 15(2): 183-196 (2006) - [j9]Yang Lu, Kiat Seng Yeo, Alper Cabuk, Jianguo Ma, Manh Anh Do, Zhenghao Lu:
A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(8): 1683-1692 (2006) - [c10]Shan Jiang, Manh Anh Do, Kiat Seng Yeo:
A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. VLSI-SoC (Selected Papers) 2006: 81-99 - [c9]Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo:
A New Phase Noise Model for TSPC based divider. VLSI-SoC 2006: 348-351 - [c8]Shan Jiang, Manh Anh Do, Kiat Seng Yeo:
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. VLSI-SoC 2006: 352-356 - 2005
- [j8]Zhi-Hui Kong, Kiat Seng Yeo, Chip-Hong Chang:
An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. J. Circuits Syst. Comput. 14(5): 939-952 (2005) - [j7]Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma:
Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1042-1048 (2005) - [j6]Shouxian Mou, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do:
A modified architecture used for input matching in CMOS low-noise amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 52-II(11): 784-788 (2005) - [j5]Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li:
Equivalent circuit model of on-wafer CMOS interconnects for RFICs. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1060-1071 (2005) - [j4]Xiaopeng Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo:
Design of a low power wide-band high resolution programmable frequency divider. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1098-1103 (2005) - [c7]Lin Jia, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do:
A novel methodology for the design of LC tank VCO with low phase noise. ISCAS (1) 2005: 376-379 - [c6]Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo:
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. ISCAS (3) 2005: 2429-2432 - [c5]Wei Meng Lim, Han Guo Ma, Manh Anh Do, Kiat Seng Yeo:
A 5GHz to 6GHz integrated differential LNA. ISCAS (5) 2005: 4815-4818 - [c4]Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo:
A new 5 GHz CMOS dual-modulus prescaler. ISCAS (5) 2005: 5027-5030 - 2004
- [j3]Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma, Xiaoling Zhang:
RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor. IEEE Trans. Circuits Syst. II Express Briefs 51-II(2): 85-90 (2004) - [c3]Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. SLIP 2004: 31-38 - 2003
- [c2]Lin Jia, Alper Cabuk, Jianguo Ma, Kiat Seng Yeo:
A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology. IWSOC 2003: 264-269 - 2002
- [c1]Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo:
An interconnect optimized floorplanning of a scalar product macrocell. ISCAS (1) 2002: 465-468
1990 – 1999
- 1999
- [j2]Chong-Fatt Law, Samir S. Rofail, Kiat Seng Yeo:
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. IEEE J. Solid State Circuits 34(10): 1395-1399 (1999) - 1998
- [j1]Kiat Seng Yeo, Samir S. Rofail:
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. IEEE J. Solid State Circuits 33(1): 164-168 (1998)
Coauthor Index
Anh-Tuan Do
aka: Anh Tuan Do
aka: Anh Tuan Do
Nagarajan Mahalingam
aka: Mahalingam Nagarajan
aka: Mahalingam Nagarajan
Xiaopeng Yu
aka: Xiao-Peng Yu
aka: Xiao-Peng Yu
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