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2020 – today
- 2024
[j25]Toshiyuki Inoue
, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. 145: 106120 (2024)- [j24]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura:
A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2514-2518 (2024) - [c60]Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC 2024: 1-4 - [c59]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. SOCC 2024: 1-6 - 2023
- [j23]Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express 20(14): 20230238 (2023) - [j22]Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express 20(18): 20230339 (2023) - [c58]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON 2023: 1-2 - [c57]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS 2023: 1-4 - [c56]Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC 2023: 13-14 - 2022
- [c55]Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. ASP-DAC 2022: 96-97 - [c54]Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine:
Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems. ICEIC 2022: 1-4 - [c53]Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine:
A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver. ICEIC 2022: 1-4 - [c52]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura:
Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC 2022: 1-4 - [c51]Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine:
Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion. ICEIC 2022: 1-4 - [c50]Masataka Inoue, Shinya Nakashioya, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band. ICECS 2022 2022: 1-4 - [c49]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 2022: 1-4 - [c48]Masanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA. ISOCC 2022: 55-56 - [c47]Yuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Smart Computational Resource Distribution System with Automatic Classification Interface for CPS. ISOCC 2022: 101-102 - [c46]Shungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing. ISOCC 2022: 338-339 - [c45]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS 2022: 1-4 - [c44]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura:
A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS 2022: 1-4 - 2021
- [c43]Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. ASP-DAC 2021: 15-16 - [c42]Yudai Ichii, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS. ICEIC 2021: 1-4 - [c41]Ukyo Yoshimura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA. ICEIC 2021: 1-4 - [c40]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS 2021: 1-6 - 2020
- [j21]Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. IEICE Trans. Electron. 103-C(10): 489-496 (2020) - [c39]Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Processing Time Reduction for JPEG Compression Using Pixel Array Conversion. ISOCC 2020: 111-112
2010 – 2019
- 2019
- [j20]Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera:
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. IEICE Trans. Electron. 102-C(7): 573-579 (2019) - [c38]Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara, Keiji Kishine:
Optimization Technique of Memory Traffic for FPGA-Based Image Processing System. ISOCC 2019: 46-47 - [c37]Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Frequency Discriminator Using a Simple AD Converter for Interface Systems. ISOCC 2019: 128-129 - [c36]Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS. ISOCC 2019: 210-211 - [c35]Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. SoCC 2019: 150-154 - [c34]Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine:
Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. SoCC 2019: 161-164 - 2018
- [c33]Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. A-SSCC 2018: 69-72 - [c32]Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion. ICECS 2018: 49-52 - [c31]Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. MWSCAS 2018: 751-754 - [c30]Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka:
A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS. VLSI-DAT 2018: 1-4 - 2017
- [c29]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura:
Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS. ISOCC 2017: 77-78 - [c28]Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Compact implementation IIR filter in FPGA for noise reduction of sensor signal. ISOCC 2017: 258-259 - [c27]Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
FPGA-based transceiver circuit for labeling signal transmission system. ISOCC 2017: 310-311 - [c26]Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera:
Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication. MWSCAS 2017: 795-798 - 2016
- [c25]Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya:
36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. ISOCC 2016: 61-62 - 2015
- [j19]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage. IEICE Trans. Electron. 98-C(6): 504-511 (2015) - [j18]Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera:
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1288-1295 (2015) - [c24]Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura:
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. A-SSCC 2015: 1-4 - [c23]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera:
Energy reduction by built-in body biasing with single supply voltage operation. ISQED 2015: 181-185 - 2014
- [j17]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 734-740 (2014) - [j16]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 768-776 (2014) - [j15]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure. IEICE Trans. Electron. 97-C(4): 325-331 (2014) - [c22]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera:
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation. A-SSCC 2014: 53-56 - [c21]Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai:
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS 2014: 2704-2707 - 2013
- [c20]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. ASP-DAC 2013: 105-106 - [c19]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Perturbation-immune radiation-hardened PLL with a switchable DMR structure. IOLTS 2013: 128-132 - 2012
- [j14]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 479-486 (2012) - [c18]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. ASP-DAC 2012: 561-562 - 2011
- [c17]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
An area effective forward/reverse body bias generator for within-die variability compensation. A-SSCC 2011: 217-220 - [c16]Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera:
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. ISOCC 2011: 36-39 - [c15]Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. ISOCC 2011: 223-226 - 2010
- [j13]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. Inf. Media Technol. 5(2): 424-433 (2010) - [j12]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. IPSJ Trans. Syst. LSI Des. Methodol. 3: 130-139 (2010) - [c14]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. CICC 2010: 1-4 - [c13]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
A design procedure of predictive RF MOSFET model for compatibility with ITRS. SoCC 2010: 396-399
2000 – 2009
- 2009
- [j11]Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Statistical Gate Delay Model for Multiple Input Switching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3070-3078 (2009) - [c12]Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng:
High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390 - [c11]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ISQED 2009: 195-200 - 2008
- [j10]Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3474-3480 (2008) - [j9]Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. Inf. Media Technol. 3(4): 729-738 (2008) - [j8]Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. IPSJ Trans. Syst. LSI Des. Methodol. 1: 116-125 (2008) - [c10]Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Statistical gate delay model for Multiple Input Switching. ASP-DAC 2008: 286-291 - [c9]Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng:
On-chip high performance signaling using passive compensation. ICCD 2008: 182-187 - 2007
- [j7]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Trans. Electron. 90-C(6): 1267-1273 (2007) - [j6]Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera:
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. IEICE Trans. Electron. 90-C(6): 1274-1281 (2007) - [c8]Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera:
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. ASP-DAC 2007: 120-121 - [c7]Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration. CICC 2007: 869-872 - [c6]Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Worst-case delay analysis considering the variability of transistors and interconnects. ISPD 2007: 35-42 - 2006
- [j5]Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. IEICE Trans. Electron. 89-C(3): 327-333 (2006) - [j4]Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3560-3568 (2006) - [j3]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3585-3593 (2006) - [c5]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520 - 2005
- [j2]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 885-891 (2005) - [c4]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081 - [c3]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Design guideline for resistive termination of on-chip high-speed interconnects. CICC 2005: 613-616 - 2004
- [c2]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696 - [c1]Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera:
Performance limitation of on-chip global interconnects for high-speed signaling. CICC 2004: 489-492 - 2003
- [j1]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Representative Frequency for Interconnect R(f)L(f)C Extraction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2942-2951 (2003)
Coauthor Index
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