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ORCIDISPD 2007: Austin, Texas, USA
- Patrick H. Madden, David Z. Pan:
Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007. ACM 2007, ISBN 978-1-59593-613-4
Keynote talk
- Jim Kahle:
Cell architecture: key physical design features and methodology. 1
Multicore and DFM
- Timothy Johnson, Umesh Nawathe:
An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2). 2 - Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
:
Dummy fill density analysis with coupling constraints. 3-10 - Vishal Khandelwal, Ankur Srivastava:
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. 11-18 - Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is your layout density verification exact?: a fast exact algorithm for density calculation. 19-26 - Shiyan Hu, Jiang Hu:
Pattern sensitive placement for manufacturability. 27-34
Circuit analysis and optimization
- Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Worst-case delay analysis considering the variability of transistors and interconnects. 35-42 - Anand Ramalingam, Giri Devarayanadurg, David Z. Pan:
Accurate power grid analysis with behavioral transistor network modeling. 43-50 - Yiyu Shi, Lei He:
Empire: an efficient and compact multiple-parameterized model order reduction method. 51-58 - Salim Chowdhury, John Lillis:
Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. 59-66 - Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari:
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. 67-74
Panel
- Louis Scheffer, Lars Liebmann, Riko Rakojcic, David White:
Rules vs tools: what's the right way to address IC manufacturing complexity? 75-76
Future interconnects
- Azad Naeemi, James D. Meindl:
Carbon nanotube interconnects. 77-84 - Ray T. Chen:
Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec. 85-86
Placement
- Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
X-architecture placement based on effective wire models. 87-94 - Philip Chong, Christian Szegedy:
A morphing approach to address placement stability. 95-102 - Zhong Xiu, Rob A. Rutenbar:
Mixed-size placement with fixed macrocells using grid-warping. 103-110 - Jianhua Li, Laleh Behjat, Jie Huang:
An effective clustering algorithm for mixed-size placement. 111-118 - Song Chen, Takeshi Yoshimura:
A stable fixed-outline floorplanning method. 119-126
Routing
- Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Efficient obstacle-avoiding rectilinear steiner tree construction. 127-134 - Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Maze routing steiner trees with effective critical sink optimization. 135-142 - Fan Mo, Robert K. Brayton:
Semi-detailed bus routing with variation reduction. 143-150 - Keith So:
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space. 151-158 - Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten:
Algorithms for automatic length compensation of busses in analog integrated circuits. 159-166
ISPD'07 global routing contest and placement contest updates
- Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden:
ISPD placement contest updates and ISPD 2007 global routing contest. 167
Statistical and physical design for manufacturability
- Noel Menezes:
The good, the bad, and the statistical. 168 - Chandu Visweswariah:
Fear, uncertainty and statistics. 169 - Shankar Krishnamoorthy:
Variation and litho driven physical implementation system. 170 - David Cross, Eric Nequist, Louis Scheffer:
A DFM aware, space based router. 171-172
Clock and interconnect
- Hao Yu, Yu Hu, Chunchen Liu, Lei He:
Minimal skew clock embedding considering time variant temperature gradient. 173-180 - Rupesh S. Shelar:
An efficent clustering algorithm for low power clock tree synthesis. 181-188 - Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri:
A methodology for interconnect dimension determination. 189-195
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