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2020 – today
- 2024
[j85]Chung-Yu Wu
, Chi-Wei Huang, Yu-Wei Chen, Chin-Kai Lai, Chung-Chih Hung, Ming-Dou Ker:
Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications. IEEE Trans. Biomed. Circuits Syst. 18(3): 539-551 (2024)- [c101]Chen-Wei Hsu, Ming-Dou Ker, Ping-Lin Chung, Chin-Tung Cheng, Chih-Ping Chen:
Embedded Deep-Nwell Collector Used to Improve Latch-Up Immunity of Multi-Functional I/O Buffer with Indirect Power-Connected N-Well. IRPS 2024: 1-4 - [c100]Kuan-Ting Lin, Ming-Dou Ker:
A Versatile 8-Channel High Voltage Stimulator for Comprehensive Neural Stimulation. ISCAS 2024: 1-5 - 2023
- [j84]Chia-Chi Hsieh, Yi-Hui Wu, Ming-Dou Ker:
Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation. IEEE Trans. Biomed. Circuits Syst. 17(2): 273-285 (2023) - [j83]Chi-Wei Huang, Chin-Kai Lai, Chung-Chih Hung, Chung-Yu Wu, Ming-Dou Ker:
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2257-2270 (2023) - [c99]Chao-Yang Ke, Yu-Chia Tsui, Bing-Yue Tsui, Ming-Dou Ker:
Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods. IRPS 2023: 1-4 - 2022
- [c98]I-Hsuan Wu, Ming-Dou Ker:
Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control. VLSI-DAT 2022: 1-4 - 2021
- [j82]Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. IEEE J. Solid State Circuits 56(10): 3062-3076 (2021) - [j81]Chia-Chi Hsieh, Ming-Dou Ker:
Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 15(3): 568-579 (2021) - [c97]Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker:
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. IRPS 2021: 1-4 - [c96]Shane Harrigan, Sonya A. Coleman, Ming-Dou Ker, Pratheepan Yogarajah, Zheng Fang, Chengdong Wu:
ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection. MVA 2021: 1-6 - [c95]Han-Sheng Huang, Ming-Dou Ker:
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events. VLSI-DAT 2021: 1-4 - 2020
- [j80]Ting-Yang Yen, Ming-Dou Ker:
Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 14(5): 961-970 (2020) - [j79]Shiau-Pin Lin, Ming-Dou Ker:
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation. IEEE Trans. Circuits Syst. 67-I(11): 4122-4131 (2020) - [c94]Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. A-SSCC 2020: 1-4 - [c93]Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker:
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals. EMBC 2020: 5188-5191 - [c92]Chao-Yang Ke, Ming-Dou Ker:
Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events. IRPS 2020: 1-5
2010 – 2019
- 2019
- [j78]Ming-Dou Ker, Maurizio Valle, Matthew L. Johnston:
Guest Editorial: Special Issue on Selected Papers From IEEE ISCAS 2019. IEEE Trans. Biomed. Circuits Syst. 13(6): 1125-1127 (2019) - [j77]Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. IEEE Trans. Biomed. Eng. 66(11): 3156-3167 (2019) - [j76]Chi-Wei Liu, Yi-Lun Chen, Pei-Chun Liao, Shiau-Pin Lin, Ting-Wei Wang, Ming-Jie Chung, Po-Hung Chen, Ming-Dou Ker, Chung-Yu Wu:
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 788-792 (2019) - [j75]Zhicong Luo, Li-Chin Yu, Ming-Dou Ker:
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3437-3444 (2019) - [c91]Chun-Cheng Chen, Ming-Dou Ker:
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process. IRPS 2019: 1-4 - [c90]Tao-Yi Hung, Ming-Dou Ker:
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications. ISCAS 2019: 1-5 - 2018
- [j74]Zhicong Luo, Ming-Dou Ker:
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(2): 178-186 (2018) - [j73]Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu:
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. IEEE J. Solid State Circuits 53(11): 3314-3326 (2018) - [j72]Wen-Chieh Chen, Ming-Dou Ker:
Surge protection design with surge-to-digital converter for microelectronic circuits and systems. Microelectron. Reliab. 88-90: 2-5 (2018) - [c89]Shiau-Pin Lin, Ming-Dou Ker:
Design of Multiple-Charge-Pump System for Implantable Biomedical Applications. BioCAS 2018: 1-4 - [c88]Chia-Chi Hsieh, Ming-Dou Ker:
Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications. MWSCAS 2018: 1-4 - 2017
- [j71]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee:
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 275-282 (2017) - [j70]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan:
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation. IEICE Trans. Electron. 100-C(8): 675-683 (2017) - [j69]Chun-Yu Lin, Rui-Hong Liu, Ming-Dou Ker:
Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process. Microelectron. Reliab. 78: 258-266 (2017) - [j68]Zhicong Luo, Ming-Dou Ker, Tzu-Yi Yang, Wan-Hsueh Cheng:
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 11(5): 1087-1096 (2017) - [j67]Zhicong Luo, Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen:
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3): 528-536 (2017) - [c87]Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw:
Design considerations and clinical applications of closed-loop neural disorder control SoCs. ASP-DAC 2017: 295-298 - 2016
- [j66]Zhicong Luo, Ming-Dou Ker:
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 10(6): 1087-1099 (2016) - [c86]Jie-Ting Chen, Chun-Yu Lin, Rong-Kun Chang, Ming-Dou Ker, Tzu-Chien Tzeng, Tzu-Chiang Lin:
ESD protection design for high-speed applications in CMOS technology. MWSCAS 2016: 1-4 - [c85]Zhicong Luo, Ming-Dou Ker:
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator. NEWCAS 2016: 1-4 - 2015
- [c84]Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin:
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. ECCTD 2015: 1-4 - [c83]Hui-Wen Tsai, Ming-Dou Ker:
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits. ECCTD 2015: 1-4 - [c82]Chia-Tsen Dai, Ming-Dou Ker:
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC. SoCC 2015: 380-383 - [c81]Federico A. Altolaguirre, Ming-Dou Ker:
Active ESD protection for input transistors in a 40-nm CMOS process. VLSI-DAT 2015: 1-4 - 2014
- [j65]Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu:
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE J. Solid State Circuits 49(1): 232-247 (2014) - [j64]Po-Yen Chiu, Ming-Dou Ker:
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit. Microelectron. Reliab. 54(1): 64-70 (2014) - [j63]Ming-Dou Ker, Wan-Yen Lin, Cheng-Cheng Yen:
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance. Microelectron. Reliab. 54(1): 71-78 (2014) - [j62]Che-Hao Chuang, Ming-Dou Ker:
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection. IEEE Trans. Ind. Electron. 61(10): 5615-5621 (2014) - [c80]Kuan-Yu Lin, Ming-Dou Ker, Chun-Yu Lin:
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. ISCAS 2014: 237-240 - [c79]Li-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jeng-Chou Tseng, Chewnpu Jou, Ming-Hsien Tsai:
ESD protection design for wideband RF applications in 65-nm CMOS process. ISCAS 2014: 1480-1483 - [c78]Federico A. Altolaguirre, Ming-Dou Ker:
Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process. MWSCAS 2014: 250-253 - 2013
- [j61]Chih-Ting Yeh, Ming-Dou Ker:
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Microelectron. Reliab. 53(2): 208-214 (2013) - [j60]Chun-Yu Lin, Wei-Ling Chen, Ming-Dou Ker:
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability. IEEE Trans. Biomed. Circuits Syst. 7(2): 196-203 (2013) - [j59]Ming-Dou Ker, Po-Yen Chiu:
Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2549-2560 (2013) - [c77]Federico A. Altolaguirre, Ming-Dou Ker:
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. ISCAS 2013: 2638-2641 - [c76]Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu:
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. ISSCC 2013: 286-287 - [c75]Po-Yen Chiu, Ming-Dou Ker:
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. SoCC 2013: 33-36 - [c74]Federico A. Altolaguirre, Ming-Dou Ker:
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. VLSI-DAT 2013: 1-4 - [c73]Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang:
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. VLSI-DAT 2013: 1-4 - [c72]Chih-Ting Yeh, Ming-Dou Ker:
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. VLSI-DAT 2013: 1-4 - 2012
- [j58]Chih-Ting Yeh, Ming-Dou Ker:
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. Microelectron. Reliab. 52(6): 1020-1030 (2012) - [j57]Chun-Yu Lin, Tang-Long Chang, Ming-Dou Ker:
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process. Microelectron. Reliab. 52(11): 2627-2631 (2012) - [j56]Chih-Ting Yeh, Ming-Dou Ker:
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 178-182 (2012) - [j55]Ming-Dou Ker, Cheng-Cheng Yen:
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels. IEEE Trans. Ind. Electron. 59(2): 1278-1287 (2012) - [c71]Shiang-Yu Tsai, Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker:
Design of ESD protection for RF CMOS power amplifier with inductor in matching network. APCCAS 2012: 467-470 - [c70]Ya-Chun Huang, Ming-Dou Ker, Chun-Yu Lin:
Design of negative high voltage generator for biphasic stimulator with soc integration consideration. BioCAS 2012: 29-32 - [c69]Ming-Dou Ker, Wei-Ling Chen, Chun-Yu Lin:
Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability. BioCAS 2012: 78 - [c68]Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewnpu Jou, Tse-Hua Lu, Jeng-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang:
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. ISCAS 2012: 2127-2130 - [c67]Ming-Dou Ker, Wan-Yen Lin:
New design of transient-noise detection circuit with SCR device for system-level ESD protection. NEWCAS 2012: 81-84 - [c66]Chun-Yu Lin, Yi-Ju Li, Ming-Dou Ker:
High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process. NEWCAS 2012: 125-128 - [c65]Chih-Ting Yeh, Ming-Dou Ker:
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT 2012: 1-4 - 2011
- [j54]Ming-Dou Ker, Wen-Yi Chen, Wuu-Trong Shieh, I-Ju Wei:
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs. IEEE J. Solid State Circuits 46(2): 537-545 (2011) - [j53]Yi-Hsin Weng, Hui-Wen Tsai, Ming-Dou Ker:
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process. Microelectron. Reliab. 51(5): 871-878 (2011) - [j52]Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker:
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process. Microelectron. Reliab. 51(8): 1315-1324 (2011) - [c64]Chun-Yu Lin, Li-Wei Chu, Shiang-Yu Tsai, Ming-Dou Ker, Tse-Hua Lu, Tsun-Lai Hsu, Ping-Fang Hung, Ming-Hsiang Song, Jeng-Chou Tseng, Tzu-Heng Chang, Ming-Hsien Tsai:
Modified LC-tank ESD protection design for 60-GHz RF applications. ECCTD 2011: 57-60 - [c63]Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker:
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. ISCAS 2011: 1403-1406 - 2010
- [j51]Chih-Ting Yeh, Ming-Dou Ker:
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. IEEE J. Solid State Circuits 45(11): 2476-2486 (2010) - [j50]Hui-Wen Tsai, Ming-Dou Ker:
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation. Microelectron. Reliab. 50(1): 48-56 (2010) - [j49]Shih-Hung Chen, Ming-Dou Ker:
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology. Microelectron. Reliab. 50(6): 821-830 (2010) - [j48]Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao:
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme. Microelectron. Reliab. 50(6): 831-838 (2010) - [j47]Wen-Yi Chen, Ming-Dou Ker:
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 1039-1047 (2010) - [j46]Ming-Dou Ker, Cheng-Cheng Yen:
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance. IEEE Trans. Ind. Electron. 57(10): 3533-3543 (2010) - [c62]Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen:
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. ISCAS 2010: 989-992 - [c61]Chun-Yu Lin, Ming-Dou Ker:
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. ISCAS 2010: 3417-3420
2000 – 2009
- 2009
- [j45]Ming-Dou Ker, Yuan-Wen Hsiao:
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits. IEICE Trans. Electron. 92-C(3): 341-351 (2009) - [j44]Chang-Tzu Wang, Ming-Dou Ker:
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. IEEE J. Solid State Circuits 44(3): 956-964 (2009) - [j43]Yuan-Wen Hsiao, Ming-Dou Ker:
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process. Microelectron. Reliab. 49(6): 650-659 (2009) - [j42]Shih-Hung Chen, Ming-Dou Ker:
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 359-363 (2009) - [j41]Tzu-Ming Wang, Ming-Dou Ker, Hung-Tai Liao:
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 966-974 (2009) - [c60]Ming-Dou Ker, Yan-Liang Lin:
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices. CICC 2009: 539-542 - [c59]Ming-Dou Ker, Chang-Tzu Wang:
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS. CICC 2009: 689-696 - [c58]Wen-Yi Chen, Ming-Dou Ker, Yeh-Ning Jou, Yeh-Jen Huang, Geeng-Lih Lin:
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection. ISCAS 2009: 385-388 - [c57]Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang:
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. ISCAS 2009: 2281-2284 - 2008
- [j40]Jung-Sheng Chen, Ming-Dou Ker:
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process. IEICE Trans. Electron. 91-C(3): 378-384 (2008) - [j39]Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng:
Low-Capacitance and Fast Turn-on SCR for RF ESD Protection. IEICE Trans. Electron. 91-C(8): 1321-1330 (2008) - [j38]Ming-Dou Ker, Cheng-Cheng Yen:
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. IEEE J. Solid State Circuits 43(11): 2533-2545 (2008) - [c56]Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin:
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. APCCAS 2008: 61-64 - [c55]Yuan-Wen Hsiao, Ming-Dou Ker:
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process. CICC 2008: 233-236 - [c54]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu:
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process. CICC 2008: 721-724 - [c53]Tzu-Ming Wang, Yu-Hsuan Li, Ming-Dou Ker:
On-glass digital-to-analog converter with gamma correction for panel data driver. ICECS 2008: 202-205 - [c52]Shih-Hung Chen, Ming-Dou Ker:
Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology. ICECS 2008: 666-669 - [c51]Ming-Dou Ker, Tzu-Ming Wang, Fang-Ling Hu:
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process. ICECS 2008: 1047-1050 - [c50]Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao:
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. ISCAS 2008: 820-823 - [c49]Ming-Dou Ker, Chun-Yu Lin, Guo-Xuan Meng:
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. ISCAS 2008: 1292-1295 - 2007
- [j37]Ming-Dou Ker, Shih-Hung Chen:
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology. IEEE J. Solid State Circuits 42(5): 1158-1168 (2007) - [j36]Ming-Dou Ker, Wei-Jen Chang:
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. Microelectron. Reliab. 47(1): 27-35 (2007) - [j35]Shih-Hung Chen, Ming-Dou Ker:
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits. Microelectron. Reliab. 47(9-11): 1502-1505 (2007) - [j34]Shih-Lun Chen, Ming-Dou Ker:
An Output Buffer for 3.3-V Applications in a 0.13- μħbox m 1/2.5-V CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 14-18 (2007) - [j33]Ming-Dou Ker, Shih-Lun Chen:
Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 47-51 (2007) - [c48]Tzu-Ming Wang, Wan-Yi Shen, Ming-Dou Ker:
A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes. ICECS 2007: 206-209 - [c47]Yu-Da Shiu, Bo-Shih Huang, Ming-Dou Ker:
CMOS Power Amplifier with ESD Protection Design Merged in Matching Network. ICECS 2007: 825-828 - [c46]Hui-Wen Tsai, Ming-Dou Ker:
Design of 2�?VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation. ICECS 2007: 1240-1243 - [c45]Ming-Dou Ker, Hung-Tai Liao:
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. ISCAS 2007: 1121-1124 - [c44]Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng:
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. SoCC 2007: 277-280 - 2006
- [j32]Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. IEEE J. Solid State Circuits 41(5): 1100-1107 (2006) - [j31]Ming-Dou Ker, Shih-Lun Chen:
Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique. IEEE J. Solid State Circuits 41(10): 2324-2333 (2006) - [j30]Ming-Dou Ker, Jia-Huei Chen:
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices. IEEE J. Solid State Circuits 41(11): 2601-2609 (2006) - [j29]Kun-Hsien Lin, Ming-Dou Ker:
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board. Microelectron. Reliab. 46(2-4): 301-310 (2006) - [j28]Shih-Hung Chen, Ming-Dou Ker:
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. Microelectron. Reliab. 46(7): 1042-1049 (2006) - [j27]Chih-Kang Deng, Ming-Dou Ker:
ESD robustness of thin-film devices with different layout structures in LTPS technology. Microelectron. Reliab. 46(12): 2067-2073 (2006) - [j26]Ming-Dou Ker, Kun-Hsien Lin:
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 235-246 (2006) - [j25]Ming-Dou Ker, Jung-Sheng Chen:
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 667-671 (2006) - [j24]Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1934-1945 (2006) - [j23]Ming-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu:
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(10): 2187-2193 (2006) - [c43]Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih:
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs. CICC 2006: 361-364 - [c42]Tzu-Ming Wang, Ming-Dou Ker, Steve Yeh, Ya-Chun Chang:
Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory. ICECS 2006: 220-223 - [c41]Cheng-Cheng Yen, Ming-Dou Ker, Pi-Chia Shih:
System-Level ESD Protection Design with On-Chip Transient Detection Circuit. ICECS 2006: 616-619 - [c40]Zi-Ping Chen, Che-Hao Chuang, Ming-Dou Ker:
Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage application. ISCAS 2006 - [c39]Bo-Shih Huang, Ming-Dou Ker:
New matching methodology of low-noise amplifier with ESD protection. ISCAS 2006 - [c38]Ming-Dou Ker, Chien-Hua Wu:
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. ISCAS 2006 - [c37]Hsin-Chyh Hsu, Ming-Dou Ker:
Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. ISQED 2006: 503-506 - [c36]Tai-Xiang Lai, Ming-Dou Ker:
Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. ISQED 2006: 597-602 - [c35]Ming-Dou Ker, Wei-Jen Chang, Chang-Tzu Wang, Wen-Yi Chen:
ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS. ISSCC 2006: 2230-2237 - 2005
- [j22]Ming-Dou Ker, Kun-Hsien Lin, Che-Hao Chuang:
MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process. IEICE Trans. Electron. 88-C(3): 429-436 (2005) - [j21]Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu:
A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device. IEICE Trans. Electron. 88-C(11): 2150-2155 (2005) - [j20]Ming-Dou Ker, Kun-Hsien Lin:
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs. IEEE J. Solid State Circuits 40(8): 1751-1759 (2005) - [j19]Ming-Dou Ker, Kun-Hsien Lin:
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology. IEEE J. Solid State Circuits 40(11): 2329-2338 (2005) - [j18]Shih-Hung Chen, Ming-Dou Ker:
Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology. Microelectron. Reliab. 45(9-11): 1311-1316 (2005) - [j17]Ming-Dou Ker, Hsin-Chyh Hsu:
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 44-53 (2005) - [j16]Shih-Lun Chen, Ming-Dou Ker:
A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals. IEEE Trans. Circuits Syst. II Express Briefs 52-II(7): 361-365 (2005) - [c34]Kun-Hsien Lin, Ming-Dou Ker:
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. ISCAS (2) 2005: 1182-1185 - [c33]Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. ISCAS (2) 2005: 1859-1862 - [c32]Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu:
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation. ISCAS (4) 2005: 3861-3864 - 2004
- [j15]Ming-Dou Ker, Kun-Hsien Lin:
Design on ESD protection scheme for IC with power-down-mode operation. IEEE J. Solid State Circuits 39(8): 1378-1382 (2004) - [j14]Chih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker:
Design optimization of ESD protection and latchup prevention for a serial I/O IC. Microelectron. Reliab. 44(2): 213-221 (2004) - [c31]Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu:
A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device. ISCAS (1) 2004: 41-44 - [c30]Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes. ISCAS (1) 2004: 321-324 - [c29]Shih-Lun Chen, Ming-Dou Ker:
A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals. ISCAS (2) 2004: 573-576 - [c28]Che-Hao Chuang, Ming-Dou Ker:
Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology. ISCAS (2) 2004: 577-580 - [c27]Ming-Dou Ker, Kun-Hsien Lin:
ESD protection design for IC with power-down-mode operation. ISCAS (2) 2004: 717-720 - [c26]Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo:
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. ISQED 2004: 433-438 - [c25]Ming-Dou Ker, Wen-Yi Chen:
Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. ISQED 2004: 445-450 - 2003
- [j13]Ming-Dou Ker, Tung-Yang Chen:
Substrate-triggered ESD protection circuit without extra process modification. IEEE J. Solid State Circuits 38(2): 295-302 (2003) - [j12]Ming-Dou Ker, Kuo-Chun Hsu:
Latchup-free ESD protection design with complementary substrate-triggered SCR devices. IEEE J. Solid State Circuits 38(8): 1380-1392 (2003) - [j11]I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker:
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. Microelectron. Reliab. 43(8): 1295-1301 (2003) - [j10]Wen-Yu Lo, Ming-Dou Ker:
Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC. Microelectron. Reliab. 43(9-11): 1583-1588 (2003) - [c24]Ming-Dou Ker, Chia-Sheng Tsai:
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. ISCAS (5) 2003: 97-100 - [c23]Ming-Dou Ker, Chien-Ming Lee:
Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. ISCAS (1) 2003: 297-300 - [c22]Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang:
Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. ISQED 2003: 241-246 - [c21]Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng:
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. ISQED 2003: 363-368 - 2002
- [j9]Ming-Dou Ker, Chien-Hui Chuang:
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers. IEEE J. Solid State Circuits 37(8): 1046-1055 (2002) - [j8]Ming-Dou Ker, Chyh-Yih Chang:
ESD protection design for CMOS RF integrated circuits using polysilicon diodes. Microelectron. Reliab. 42(6): 863-872 (2002) - [c20]Ming-Dou Ker, Kuo-Chun Hsu:
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. ISCAS (5) 2002: 529-532 - [c19]Ming-Dou Ker, Che-Hao Chuang:
ESD protection circuits with novel MOS-bounded diode structures. ISCAS (5) 2002: 533-536 - [c18]Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang:
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. ISCAS (5) 2002: 537-540 - [c17]Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo:
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. ISQED 2002: 331-336 - 2001
- [j7]Ming-Dou Ker, Tung-Yang Chen, Tai-Ho Wang, Chung-Yu Wu:
On-chip ESD protection design by using polysilicon diodes in CMOS process. IEEE J. Solid State Circuits 36(4): 676-686 (2001) - [j6]Ming-Dou Ker, Yu-Yu Sung:
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard. Microelectron. Reliab. 41(3): 417-429 (2001) - [c16]Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh:
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. ICECS 2001: 113-116 - [c15]Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo:
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. ICECS 2001: 361-364 - [c14]Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang:
ESD test methods on integrated circuits: an overview. ICECS 2001: 1011-1014 - [c13]Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win:
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. ISCAS (4) 2001: 754-757 - [c12]Ming-Dou Ker, Tung-Yang Chen:
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. ISCAS (4) 2001: 758-761 - [c11]Tung-Yang Chen, Ming-Dou Ker:
Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. ISQED 2001: 247-248 - [c10]Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang:
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. ISQED 2001: 267-272 - 2000
- [j5]Ming-Dou Ker, Wen-Yu Lo:
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process. IEEE J. Solid State Circuits 35(4): 601-611 (2000) - [j4]Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang:
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications. IEEE J. Solid State Circuits 35(8): 1194-1199 (2000) - [c9]Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang:
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications. ISCAS 2000: 61-64 - [c8]Ming-Dou Ker, Wen-Yu Lo, Hun-Hsien Chang:
Mew diode string design with very low leakage current for using in power supply ESD clamp circuits. ISCAS 2000: 69-72
1990 – 1999
- 1999
- [c7]Ming-Dou Ker, Wen-Yu Lo, Chung-Yu Wu:
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. CICC 1999: 143-146 - [c6]Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen:
ESD buses for whole-chip ESD protection. ISCAS (1) 1999: 545-548 - 1998
- [c5]Ming-Dou Ker, Jeng-Jie Peng:
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology. CICC 1998: 537-540 - [c4]Ming-Dou Ker, Hun-Hsien Chang:
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection. CICC 1998: 541-544 - [c3]Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu:
CMOS on-chip ESD protection design with substrate-triggering technique. ICECS 1998: 273-276 - [c2]Ming-Dou Ker:
Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview. ICECS 1998: 325-328 - 1997
- [j3]Ming-Dou Ker, Hun-Hsien Chang, Chung-Yu Wu:
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs. IEEE J. Solid State Circuits 32(1): 38-51 (1997) - [j2]Ming-Dou Ker:
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current. IEEE J. Solid State Circuits 32(8): 1293-1296 (1997) - 1996
- [j1]Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang:
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. IEEE Trans. Very Large Scale Integr. Syst. 4(3): 307-321 (1996) - 1995
- [c1]Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu:
Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's. ISCAS 1995: 833-836
Coauthor Index
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