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ORCIDHubert Kaeslin
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- affiliation: ETH Zurich, Switzerland
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2010 – 2019
- 2018
[j16]Michael Schaffner
, Florian Scheidegger, Lukas Cavigelli, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Towards Edge-Aware Spatio-Temporal Filtering in Real-Time. IEEE Trans. Image Process. 27(1): 265-280 (2018)- 2016
- [j15]Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. IEEE Trans. Circuits Syst. Video Technol. 26(11): 2093-2108 (2016) - 2015
- [c35]Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Automatic multiview synthesis - Towards a mobile system on a chip. VCIP 2015: 1-4 - [c34]Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Automatic multiview synthesis - Prototype demo. VCIP 2015: 1 - [p1]Hubert Kaeslin:
Semiconductor Technology and the Energy Efficiency of ICT. ICT Innovations for Sustainability 2015: 105-111 - 2014
- [c33]Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim, Hubert Kaeslin:
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC. ASAP 2014: 25-29 - [c32]Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. DAC 2014: 132:1-132:6 - [c31]Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber:
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. ISCAS 2014: 2740-2743 - 2013
- [j14]Pierre Greisen, Marian Runo, Patrice Guillet, Simon Heinzle, Aljoscha Smolic, Hubert Kaeslin, Markus H. Gross:
Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications. IEEE Trans. Circuits Syst. Video Technol. 23(8): 1402-1407 (2013) - [c30]Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic:
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. ESSCIRC 2013: 61-64 - [c29]David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer:
Live demonstration: Real-time audio restoration using sparse signal recovery. ISCAS 2013: 659 - [c28]Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin:
A real-time 720p feature extraction core based on Semantic Kernels Binarized. VLSI-SoC 2013: 27-32 - [c27]Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. VLSI-SoC (Selected Papers) 2013: 144-167 - 2012
- [j13]Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk:
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 579-590 (2012) - [j12]Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross:
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications. IEEE Trans. Circuits Syst. Video Technol. 22(11): 1577-1589 (2012) - [c26]Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer:
Sparsity-based real-time audio restoration. DASIP 2012: 1-2 - [c25]Patrick Maechler, Norbert Felber, Hubert Kaeslin:
Compressive sensing for WiFi-based passive bistatic radar. EUSIPCO 2012: 1444-1448 - [c24]Lin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin:
High-speed compressed sensing reconstruction on FPGA using OMP and AMP. ICECS 2012: 53-56 - [c23]Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg:
Hardware-efficient random sampling of fourier-sparse signals. ISCAS 2012: 269-272
2000 – 2009
- 2008
- [j11]Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 830-836 (2008) - [c22]Peter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison. APCCAS 2008: 830-833 - 2007
- [j10]Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross:
A hardware architecture for surface splatting. ACM Trans. Graph. 26(3): 90 (2007) - [c21]Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. CICC 2007: 451-454 - 2006
- [c20]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
GALS at ETH Zurich: Success or Failure. ASYNC 2006: 150-159 - [c19]Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. DAC 2006: 558-561 - [c18]Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
Two-phase resonant clocking for ultra-low-power hearing aid applications. DATE 2006: 73-78 - [c17]Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
42% power savings through glitch-reducing clocking strategy in a hearing aid application. ISCAS 2006 - 2005
- [c16]Flavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A 0.67-mm2 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids. ECCTD 2005: 141-144 - [c15]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Improving DPA security by using globally-asynchronous locally-synchronous systems. ESSCIRC 2005: 407-410 - [c14]Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. PATMOS 2005: 446-455 - [c13]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. FMGALS@MEMOCODE 2005: 133-149 - 2004
- [c12]Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Towards an AES crypto-chip resistant to differential power analysis. ESSCIRC 2004: 307-310 - [c11]Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin:
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 - 2003
- [j9]Jürgen Wassner, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Waveform coding for low-power digital filtering of speech data. IEEE Trans. Signal Process. 51(6): 1656-1661 (2003) - [c10]Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner:
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2003: 141-150 - [c9]Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner:
Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) 2003: 113-116 - 2002
- [c8]Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2002: 181-189 - [c7]Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner:
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES 2002: 144-158 - 2001
- [j8]Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Design and Verification of a Stack Processor Virtual Component. IEEE Micro 21(2): 69-80 (2001) - 2000
- [c6]Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A new paradigm for very flexible SONET/SDH IP-modules. CICC 2000: 533-536
1990 – 1999
- 1999
- [c5]Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann:
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. ITC 1999: 414-420 - 1997
- [j7]Robert Rogenmoser, Hubert Kaeslin:
The impact of transistor sizing on power efficiency in submicron CMOS circuits. IEEE J. Solid State Circuits 32(7): 1142-1145 (1997) - 1996
- [c4]Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle:
Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. PPSN 1996: 849-858 - 1994
- [j6]Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. IEEE J. Solid State Circuits 29(3): 303-307 (1994) - 1993
- [c3]Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner:
VINCI: Secure Test of a VLSI High-Speed Encryption System. ITC 1993: 782-790 - 1991
- [c2]Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai:
VLSI Implementation of a New Block Cipher. ICCD 1991: 510-513
1980 – 1989
- 1989
- [j5]Marc Biver, Hubert Kaeslin, Carlo Tommasini:
Architectural design and realization of a single-chip Viterbi decoder. Integr. 8(1): 3-16 (1989) - [j4]Marc Biver, Hubert Kaeslin, Carlo Tommasini:
In-place updating of path metrics in Viterbi decoders. IEEE J. Solid State Circuits 24(4): 1158-1160 (1989) - 1988
- [j3]Hubert Kaeslin:
Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX. it Inf. Technol. 30(1): 11-16 (1988) - [c1]Hubert Kaeslin:
Application of Graph Theory to Topology Generation for Logic Gates. WG 1988: 304-316 - 1986
- [j2]Hubert Kaeslin:
A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space. Speech Commun. 5(1): 35-46 (1986) - [j1]Hubert Kaeslin:
A systematic approach to the extraction of diphone elements from natural speech. IEEE Trans. Acoust. Speech Signal Process. 34(2): 264-271 (1986)
Coauthor Index
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