"A 2 Gb/s balanced AES crypto-chip implementation."

Frank K. Gürkaynak et al. (2004)

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DOI: 10.1145/988952.988963

access: closed

type: Conference or Workshop Paper

metadata version: 2020-01-17

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Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin:
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44

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