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ORCIDKris Tiri
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2010 – 2019
- 2010
[p1]Kris Tiri:
Side-Channel Resistant Circuit Styles and Associated IC Design Flow. Secure Integrated Circuits and Systems 2010: 145-157
2000 – 2009
- 2007
- [c19]Patrick Schaumont, Kris Tiri:
Masking and Dual-Rail Logic Don't Add Up. CHES 2007: 95-106 - [c18]Kris Tiri:
Side-Channel Attack Pitfalls. DAC 2007: 15-20 - [c17]Kris Tiri, Onur Aciiçmez, Michael Neve, Flemming Andersen:
An Analytical Model for Time-Driven Cache Attacks. FSE 2007: 399-413 - [i6]Kris Tiri, Ingrid Verbauwhede:
Design Method for Constant Power Consumption of Differential Logic Circuits. CoRR abs/0710.4756 (2007) - [i5]Kris Tiri, Ingrid Verbauwhede:
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. CoRR abs/0710.4806 (2007) - [i4]Michael Neve, Kris Tiri:
On the complexity of side-channel attacks on AES-256 - methodology and quantitative results on cache attacks. IACR Cryptol. ePrint Arch. 2007: 318 (2007) - 2006
- [j5]David Hwang, Patrick Schaumont
, Kris Tiri, Ingrid Verbauwhede:
Securing Embedded Systems. IEEE Secur. Priv. 4(2): 40-49 (2006) - [j4]David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. IEEE J. Solid State Circuits 41(4): 781-792 (2006) - [j3]Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1146-1154 (2006) - [j2]Kris Tiri, Ingrid Verbauwhede:
A digital design flow for secure integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1197-1208 (2006) - [c16]Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede:
Side-Channel Leakage Tolerant Architectures. ITNG 2006: 204-209 - [c15]Kris Tiri, Patrick Schaumont:
Changing the Odds Against Masked Logic. Selected Areas in Cryptography 2006: 134-146 - 2005
- [c14]Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. CHES 2005: 354-365 - [c13]Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. DAC 2005: 222-227 - [c12]Kris Tiri, Ingrid Verbauwhede:
Simulation models for side-channel information leaks. DAC 2005: 228-233 - [c11]Kris Tiri, Ingrid Verbauwhede:
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. DATE 2005: 58-63 - [c10]Kris Tiri, Ingrid Verbauwhede:
Design Method for Constant Power Consumption of Differential Logic Circuits. DATE 2005: 628-633 - [c9]Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede:
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. ACM Great Lakes Symposium on VLSI 2005: 60-63 - 2004
- [j1]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39(7): 1119-1130 (2004) - [c8]Kris Tiri, Ingrid Verbauwhede:
Place and Route for Secure Standard Cell Design. CARDIS 2004: 143-158 - [c7]Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede:
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. CASES 2004: 303-311 - [c6]Kris Tiri, Ingrid Verbauwhede:
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. DATE 2004: 246-251 - [c5]Kris Tiri, Ingrid Verbauwhede:
Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]. ESSCIRC 2004: 179-182 - [c4]Kris Tiri, Ingrid Verbauwhede:
Secure Logic Synthesis. FPL 2004: 1052-1056 - [i3]Kris Tiri, Ingrid Verbauwhede:
A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC's. IACR Cryptol. ePrint Arch. 2004: 66 (2004) - [i2]Kris Tiri, Ingrid Verbauwhede:
Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC's against Differential Power Analysis. IACR Cryptol. ePrint Arch. 2004: 67 (2004) - [i1]Kris Tiri, Ingrid Verbauwhede:
Synthesis of Secure FPGA Implementations. IACR Cryptol. ePrint Arch. 2004: 68 (2004) - 2003
- [c3]Kris Tiri, Ingrid Verbauwhede:
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. CHES 2003: 125-136 - [c2]Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC 2003: 257-260 - 2002
- [c1]Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404
Coauthor Index
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