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2010 – 2019
- 2019
[j24]Guan-Yuan Wu, Masayuki Mizuno
:
The numerical analysis of mass evacuation in Taipei 101 with control volume model. Simul. Model. Pract. Theory 96 (2019)- [c20]Masayuki Mizuno, Eijiro Sumii:
Formal Verifications of Call-by-Need and Call-by-Name Evaluations with Mutual Recursion. APLAS 2019: 181-201 - 2018
- [c19]Masayuki Mizuno, Eijiro Sumii:
Formal Verification of the Correspondence Between Call-by-Need and Call-by-Name. FLOPS 2018: 1-16 - 2013
- [c18]Ken'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno:
A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. ISSCC 2013: 406-407 - 2012
- [j23]Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno:
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. IEEE J. Solid State Circuits 47(2): 435-443 (2012) - [j22]Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno:
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits 47(4): 832-840 (2012) - [c17]Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno:
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC 2012: 16-17 - 2011
- [j21]Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno:
A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Trans. Electron. 94-C(1): 102-109 (2011) - [j20]Koichi Yamaguchi, Masayuki Mizuno:
Dicode Partial Response Signaling over Inductively-Coupled Channel. IEICE Trans. Electron. 94-C(4): 613-618 (2011) - [j19]Koichi Yamaguchi, Masayuki Mizuno:
A Duobinary Signaling for Asymmetric Multi-Chip Communication. IEICE Trans. Electron. 94-C(4): 619-626 (2011) - 2010
- [j18]Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. IEEE J. Solid State Circuits 45(1): 15-22 (2010) - [j17]Haruya Ishizaki, Masayuki Mizuno:
A 0.2 mm 2 , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability. IEEE J. Solid State Circuits 45(4): 921-927 (2010) - [j16]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda:
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits 45(10): 2057-2065 (2010) - [c16]Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda:
A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC 2010: 1-4 - [c15]Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno:
A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. ISSCC 2010: 162-163 - [c14]Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno:
A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC 2010: 192-193 - [c13]Young Moon Kim, Tze Wee Chen, Yoshio Kameda, Masayuki Mizuno, Subhasish Mitra:
Gate-oxide early-life failure identification using delay shifts. VTS 2010: 69-74
2000 – 2009
- 2009
- [j15]Katsu Nakamura, Masayuki Mizuno:
Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 44(4): 1039-1040 (2009) - [j14]Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery. IEEE J. Solid State Circuits 44(12): 3560-3567 (2009) - [j13]Keishi Ohashi, Kenichi Nishi, Takanori Shimizu, Masafumi Nakada, Junichi Fujikata, Jun Ushida, Sunao Torii, Koichi Nose, Masayuki Mizuno, Hiroaki Yukawa, Masao Kinoshita, Nobuo Suzuki, Akiko Gomyo, Tsutomu Ishi, Daisuke Okamoto, Katsuya Furue, Toshihide Ueno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Jun Akedo:
On-Chip Optical Interconnect. Proc. IEEE 97(7): 1186-1198 (2009) - [c12]Masahiro Sekimoto, Sadao Kawamura, Tomoya Ishitsubo, Shinsuke Akizuki, Masayuki Mizuno:
Basis-motion torque composition approach: generation of feedforward inputs for control of multi-joint robots. IROS 2009: 3127-3132 - [c11]Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A chip-stacked memory for on-chip SRAM-rich SoCs and processors. ISSCC 2009: 60-61 - [c10]Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. ISSCC 2009: 192-193 - [c9]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno:
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC 2009: 470-471 - 2008
- [j12]Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi:
LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Trans. Electron. 91-C(2): 131-137 (2008) - [j11]Koichi Nose, Masayuki Mizuno:
A 0.016 mm2, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis. IEEE J. Solid State Circuits 43(4): 1038-1046 (2008) - 2007
- [j10]Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda:
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. 90-C(4): 829-835 (2007) - [c8]Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada:
LAGS System Using Data/Instruction Grain Power Control. ISSCC 2007: 66-587 - [c7]Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno:
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. ISSCC 2007: 174-594 - [c6]Toru Nakura, Koichi Nose, Masayuki Mizuno:
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC 2007: 402-611 - 2006
- [j9]Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kazuya Terabe, Tsuyoshi Hasegawa, Masakazu Aono:
Solid-Electrolyte Nanometer Switch. IEICE Trans. Electron. 89-C(11): 1492-1498 (2006) - [j8]Koichi Nose, Mikihiro Kajita, Masayuki Mizuno:
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. IEEE J. Solid State Circuits 41(12): 2911-2920 (2006) - [c5]Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba:
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC 2006: 1686-1695 - [c4]Koichi Nose, Mikihiro Kajita, Masayuki Mizuno:
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. ISSCC 2006: 2112-2121 - 2005
- [j7]Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono:
A nonvolatile programmable solid-electrolyte nanometer switch. IEEE J. Solid State Circuits 40(1): 168-176 (2005) - [j6]Makoto Takamiya, Masayuki Mizuno:
A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL. IEEE J. Solid State Circuits 40(3): 719-725 (2005) - 2004
- [c3]Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka:
Frequency-hopping vernier clock generators for multiple clock domain SoCs. CICC 2004: 91-94 - 2003
- [j5]Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno:
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. IEEE J. Solid State Circuits 38(5): 741-746 (2003) - 2001
- [c2]Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina:
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC 2001: 213-216
1990 – 1999
- 1999
- [j4]Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina:
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits 34(7): 1010-1021 (1999) - 1997
- [j3]Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina:
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. IEEE J. Solid State Circuits 32(11): 1807-1816 (1997) - [c1]Yasushi Ooi, Osamu Ohnishi, Yutaka Yokoyama, Yoichi Katayama, Masayuki Mizuno, Masakazu Yamashina, Hideo Takano, Naoya Hayashi, Ichiro Tamitani:
An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. ICASSP 1997: 599-602 - 1996
- [j2]Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina:
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. IEEE J. Solid State Circuits 31(4): 531-536 (1996) - [j1]Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada:
A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid State Circuits 31(6): 784-791 (1996)
Coauthor Index
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