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2020 – today
- 2023
[j38]Shinichi Nishizawa
, Toru Nakura:
Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 551-559 (2023)- [c53]Yuto Yakubo, Kazuma Furutani, Kouhei Toyotaka, Haruki Katagiri, Masashi Fujita, Munehiro Kozuma, Yoshinori Ando, Yoshiyuki Kurokawa, Toru Nakura, Shunpei Yamazaki:
Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating. ISSCC 2023: 212-213 - 2022
- [j37]Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada:
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. 105-C(10): 544-551 (2022) - [c52]Shinichi Nishizawa, Toru Nakura:
Density Aware Cell Library Design for Design-Technology Co-Optimization. ISQED 2022: 1
2010 – 2019
- 2019
- [j36]Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada:
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16(19): 20190390 (2019) - [j35]Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura:
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express 16(19): 20190546 (2019) - [j34]Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68(7): 2519-2530 (2019) - [j33]Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 11-19 (2019) - 2018
- [j32]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34(2): 147-161 (2018) - [j31]Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda:
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15(5) (2018) - [j30]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 410-424 (2018) - [j29]Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada:
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. 101-C(4): 218-223 (2018) - [j28]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. 101-C(4): 292-298 (2018) - [c51]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) 2018: 1-13 - [c50]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC 2018: 55-58 - 2017
- [j27]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 200-209 (2017) - [j26]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. 100-C(9): 736-745 (2017) - [j25]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2741-2749 (2017) - [c49]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC 2017: 23-24 - [c48]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
CMOS-on-quartz pulse generator for low power applications. ASP-DAC 2017: 29-30 - [c47]Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging 2017: 18-23 - [c46]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS 2017: 1-2 - [c45]Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS 2017: 1-4 - [c44]Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS 2017: 231-234 - [c43]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS 2017: 318-321 - [c42]Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada:
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS 2017: 1-3 - [c41]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS 2017: 257-260 - 2016
- [j24]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32(3): 257-271 (2016) - [j23]Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada:
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. 99-C(2): 275-284 (2016) - [j22]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. 99-C(10): 1219-1225 (2016) - [j21]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25(3): 1640017:1-1640017:16 (2016) - [c40]Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC 2016: 313-316 - [c39]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE 2016: 517-522 - [c38]Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada:
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC 2016: 301-304 - [c37]Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada:
One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME 2016: 1-3 - [c36]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Resonant power supply noise reduction using a triangular active charge injection. ICECS 2016: 113-116 - [c35]Masahiro Kano, Toru Nakura, Kunihiro Asada:
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED 2016: 386-391 - [c34]Toru Nakura, Kunihiro Asada:
Fully automated PLL compiler generating final GDS from specification. ISQED 2016: 437-442 - [c33]Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC 2016: 1-8 - 2015
- [j20]Toru Nakura, Hiroaki Matsui, Kunihiro Asada:
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express 12(3): 20141114 (2015) - [j19]Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada:
Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. 98-C(7): 734-740 (2015) - [c32]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC 2015: 1-4 - [c31]Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada:
A Technique for Analyzing On-Chip Power Supply Impedance. ATS 2015: 193-198 - [c30]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS 2015: 131-136 - [c29]Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS 2015: 1-4 - 2014
- [c28]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Burst-pulse Generator based on transmission line toward sub-MMW. DDECS 2014: 59-64 - [c27]Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada:
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS 2014: 282-285 - [c26]Toru Nakura, Kunihiro Asada:
Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME 2014: 133-136 - [c25]Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada:
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC 2014: 1-10 - 2013
- [j18]Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. 96-C(4): 560-567 (2013) - [c24]Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC 2013: 1-4 - [c23]Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Pulse Width controlled PLL and its automated design flow. ICECS 2013: 5-8 - [c22]Tomohiko Yano, Toru Nakura, Kunihiro Asada:
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS 2013: 625-628 - 2012
- [j17]Toru Nakura, Kunihiro Asada:
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. 95-C(2): 297-302 (2012) - [j16]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. 95-C(4): 643-650 (2012) - [j15]Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. 95-C(12): 1857-1863 (2012) - [c21]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium 2012: 252-257 - [c20]Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada:
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC 2012: 1-4 - [c19]Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC 2012: 1-10 - 2011
- [j14]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. 94-C(4): 487-494 (2011) - [j13]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. 94-C(4): 511-519 (2011) - [j12]Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. 94-C(4): 654-662 (2011) - [j11]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. 94-C(6): 1098-1104 (2011) - [c18]Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80 - [c17]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114 - [c16]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186 - [c15]Teruki Nakasato, Toru Nakura, Kunihiro Asada:
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC 2011: 150-153 - 2010
- [j10]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A 8bit two stage time-to-digital converter using time difference amplifier. IEICE Electron. Express 7(13): 943-948 (2010) - [j9]Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada:
Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Trans. Electron. 93-C(3): 303-308 (2010) - [j8]Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1319-1328 (2010) - [c14]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Cascaded time difference amplifier using differential logic delay cell. ASP-DAC 2010: 355-356 - [c13]Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172 - [c12]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC 2010: 182-185 - [c11]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC 2010: 266-269
2000 – 2009
- 2009
- [j7]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Trans. Electron. 92-C(6): 798-805 (2009) - [c10]Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda:
Measurement of power supply noise tolerance of self-timed processor. DDECS 2009: 128-131 - [c9]Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209 - [c8]Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada:
SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD 2009: 643-646 - [c7]Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC 2009: 156-159 - [c6]MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI 2009: 177-180 - 2007
- [c5]Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC 2007: 100-101 - [c4]Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada:
LAGS System Using Data/Instruction Grain Power Control. ISSCC 2007: 66-587 - [c3]Toru Nakura, Koichi Nose, Masayuki Mizuno:
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC 2007: 402-611 - 2006
- [j6]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. IEICE Trans. Electron. 89-C(3): 364-369 (2006) - [j5]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Autonomous di/dt Control of Power Supply for Margin Aware Operation. IEICE Trans. Electron. 89-C(11): 1689-1694 (2006) - 2005
- [j4]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Trans. Electron. 88-C(1): 125-132 (2005) - [j3]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
On-chip di/dt Detector Circuit. IEICE Trans. Electron. 88-C(5): 782-787 (2005) - [j2]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Trans. Electron. 88-C(8): 1734-1739 (2005) - [c2]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Autonomous di/dt noise control scheme for margin aware operation. ESSCIRC 2005: 467-470 - 2003
- [c1]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Theoretical study of stubs for power line noise reduction [LSI applications]. CICC 2003: 715-718 - 2000
- [j1]Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara:
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35(5): 751-756 (2000)
Coauthor Index
[j37] [j36] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [c51] [c50] [j27] [j26] [j25] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [j24] [j23] [j22] [j21] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [j20] [j19] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [j18] [c24] [c23] [c22] [j17] [j16] [j15] [c21] [c20] [c19] [j14] [j13] [j12] [j11] [c18] [c17] [c16] [c15] [j10] [j9] [j8] [c14] [c13] [c12] [c11] [j7] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [j6] [j5] [j4] [j3] [j2] [c2] [c1]
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