"IndiRA: Design and Implementation of a Pipelined RISC-V Processor."

Ankita Tiwari et al. (2023)

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DOI: 10.1109/RADIOELEKTRONIKA57919.2023.10109058

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-13

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Ankita Tiwari, Prithwijit Guha, Gaurav Trivedi, Nitesh Gupta, Navneeth Jayaraj, Jan Pidanic:
IndiRA: Design and Implementation of a Pipelined RISC-V Processor. RADIOELEKTRONIKA 2023: 1-6

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