default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID21. FPGA 2013: Monterey, CA, USA
- Brad L. Hutchings, Vaughn Betz:
The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013. ACM 2013, ISBN 978-1-4503-1887-7
Tutorials
- Stephen Neuendorffer, Fernando Martinez-Vallina:
Building zynq® accelerators with Vivado® high level synthesis. 1-2 - Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe:
Cross-platform FPGA accelerator development using CoRAM and CONNECT. 3-4 - Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling:
Harnessing the power of FPGAs using altera's OpenCL compiler. 5-6 - Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi:
High-level synthesis with LegUp: a crash course for users and researchers. 7-8
CAD for high-level synthesis and debug
- Wei Zuo, Yun Liang, Peng Li
, Kyle Rupnow, Deming Chen, Jason Cong:
Improving high level synthesis optimization opportunity through polyhedral transformations. 9-18 - Eddie Hung, Steven J. E. Wilton:
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. 19-28 - Louis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong:
Polyhedral-based data reuse optimization for configurable computing. 29-38 - Martin Langhammer, Bogdan Pasca:
Faithful single-precision floating-point tangent for FPGAs. 39-42
Applications I
- Nathaniel McVicar, Walter L. Ruzzo, Scott Hauck:
Accelerating ncRNA homology search with FPGAs. 43-52 - Zilong Wang, Sitao Huang, Lanjun Wang, Hao Li, Yu Wang, Huazhong Yang:
Accelerating subsequence similarity search based on dynamic time warping distance with FPGA. 53-62 - Jungwook Choi, Rob A. Rutenbar:
Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform. 63-72
FPGA circuitry and security
- Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi:
Fully-functional FPGA prototype with fine-grain programmable body biasing. 73-80 - Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. 81-90 - Amir Moradi, David F. Oswald, Christof Paar, Pawel Swierczynski:
Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering. 91-100 - Kenneth M. Zick, Meeta Srivastav, Wei Zhang, Matthew French:
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs. 101-104
Computer-aided design tools
- David Boland, George A. Constantinides:
Word-length optimization beyond straight line code. 105-114 - Michael J. Wirthlin, Joshua E. Jensen, Alex Wilson, William Howes, Shi-Jie Wen, Rick Wong:
Placement of repair circuits for in-field FPGA repair. 115-124 - Michel A. Kinsy, Michael Pellauer, Srinivas Devadas:
Heracles: a tool for fast RTL-based design space exploration of multicore processors. 125-134
Evening panel: are FPGAs suffering from the innovator's dilemna?
- Vaughn Betz, Jason Cong:
Are FPGAs suffering from the innovator's dilemna? 135-136
FPGA architecture
- André DeHon:
Location, location, location: the role of spatial locality in asymptotic energy minimization. 137-146 - David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu:
Architectural enhancements in Stratix V™. 147-156 - Peter Grossmann, Miriam Leeser, Marvin Onabajo:
Minimum energy operation for clustered island-style FPGAs. 157-166 - Seyyed Ahmad Razavi, Morteza Saheb Zamani:
Improving bitstream compression by modifying FPGA architecture. 167-170
Design studies and design methodologies
- Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu:
Elastic CGRAs. 171-180 - Bailey Miller, Frank Vahid, Tony Givargis:
Embedding-based placement of processing element networks on FPGAs for physical model simulation. 181-190 - Udit Dhawan, André DeHon:
Area-efficient near-associative memories on FPGAs. 191-200
High-level abstractions and tools
- Jeremy Fowers, Greg Stitt:
Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations. 201-210 - Ruediger Willenberg, Paul Chow:
A remote memory access infrastructure for global address space programming models in FPGAs. 211-220 - Gabriel Weisz, James C. Hoe:
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction. 221-230 - Jason Cong, Karthik Gururaj:
Architecture support for custom instructions with memory operations. 231-234
Applications II
- Hao Wang, Jyh-Charn Liu:
An FPGA based parallel architecture for music melody matching. 235-244 - Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala:
An FPGA memcached appliance. 245-254 - Da Tong, Lu Sun, Kiran Kumar Matam, Viktor K. Prasanna:
High throughput and programmable online trafficclassifier on FPGA. 255-264
Poster session I
- Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai:
FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). 265 - Meng Yang, Jiarong Tong, A. E. A. Almaini:
Indirect connection aware attraction for FPGA clustering (abstract only). 265 - Eric S. Chung, Michael Papamichael:
Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only). 265 - Trevor Bunker, Steven Swanson:
A latency-optimized hybrid network for clustering FPGAs (abstract only). 266 - Chao Wang, Xi Li, Xuehai Zhou, Jim Martin, Ray C. C. Cheung:
Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only). 266 - Soon Ee Ong, Siaw Chen Lee, Noohul Basheer Zain Ali:
Hardware implemented real-time operating system (abstract only). 266 - Anh-Tuan Hoang, Takeshi Fujino:
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). 266-267 - Christos Kyrkou, Christos-Savvas Bouganis, Theocharis Theocharides:
FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only). 267 - Jing Zhou, Lei Chen, Shuo Wang:
Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only). 267 - Chao Wang, Xi Li, Huizhen Zhang, Jinsong Ji, Xuehai Zhou:
Custom instruction generation and mapping for reconfigurable instruction set processors (abstract only). 268 - Pavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis:
High performance architecture for object detection in streamed video (abstract only). 268
Poster session II
- Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong:
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). 269 - Chun Zhu, Qiuli Li, Jian Wang, Jinmei Lai:
A novel multithread routing method for FPGAs (abstract only). 269 - Andrew Love, Peter Athanas:
FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only). 269 - Sezer Gören, Yusuf Turk, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag:
Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only). 270 - Hasan Baig, Jeong-A Lee:
A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only). 270 - Vivek Venugopal, Devu Manikantan Shila:
Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only). 270 - Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). 271 - Chia-Hsiang Chen, Shiming Song, Zhengya Zhang:
An FPGA-based transient error simulator for evaluating resilient system designs (abstract only). 271 - Peng Chen, Chao Wang, Xi Li, Xuehai Zhou:
Acceleration of the long read mapping on a PC-FPGA architecture (abstract only). 271
Poster session III
- Jingfei Jiang, Rongdong Hu, Mikel Luján:
Effect of fixed-point arithmetic on deep belief networks (abstract only). 273 - Wenjuan Deng, Yiqun Zhu:
A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only). 273 - Yu Bai, Abigail Fuentes-Rivera, Mingjie Lin, Mike Riera:
Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only). 273 - David Uliana, Krzysztof Kepa, Peter Athanas:
FPGA-based HPC application design for non-experts (abstract only). 274 - Swapnil Haria, Viktor K. Prasanna:
AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on FPGA (abstract only). 274 - Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire:
Performance and toolchain of a combined GPU/FPGA desktop (abstract only). 274 - Marc-André Daigneault, Jean-Pierre David:
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). 274-275 - Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu:
Automating resource optimisation in reconfigurable design (abstract only). 275
Poster session IV
- Sheng Wei, Jason Xin Zheng, Miodrag Potkonjak:
Low power FPGA design using post-silicon device aging (abstract only). 277 - Oluseyi A. Ayorinde, Benton H. Calhoun:
Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only). 277 - Jason Cong, Muhuan Huang, Peng Zhang:
Efficient system-level mapping from streaming applications to FPGAs (abstract only). 277 - Jason Cong, Bingjun Xiao:
Defect recovery in nanodevice-based programmable interconnects (abstract only). 277-278 - Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt:
A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only). 278 - Yun Qu, Viktor K. Prasanna:
Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only). 278 - Nick Ni, Yi Peng:
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only). 278 - Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). 279 - Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). 279
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-09 15:00 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
