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ORCIDPaolo Ienne
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- affiliation: Swiss Federal Institute of Technology in Lausanne, Switzerland
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2020 – today
- 2024
[j53]Stefan Nikolic
, Paolo Ienne:
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. ACM Trans. Reconfigurable Technol. Syst. 17(1): 14:1-14:39 (2024)- [c169]Mohamed Shahawy, Canberk Sönmez, Cemalettin Belentepe, Paolo Ienne:
HardCilk: Cilk-like Task Parallelism for FPGAs. FCCM 2024: 140-150 - [c168]Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne:
DynaRapid: From C to FPGA in a Few Seconds. FPGA 2024: 40 - [c167]Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA 2024: 44-54 - [c166]Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne:
DynaRapid: Fast-Tracking from C to Routed Circuits. FPL 2024: 24-32 - [c165]Canberk Sönmez, Mohamed Shahawy, Cemalettin Cem Belentepe, Paolo Ienne:
FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs. FPL 2024: 78-86 - [i4]Beatriz Borges, Negar Foroutan, Deniz Bayazit, Anna Sotnikova, Syrielle Montariol, Tanya Nazaretzky, Mohammadreza Banaei, Alireza Sakhaeirad, Philippe Servant, Seyed Parsa Neshaei, Jibril Frej, Angelika Romanou, Gail Weiss, Sepideh Mamooler, Zeming Chen, Simin Fan, Silin Gao, Mete Ismayilzada, Debjit Paul, Alexandre Schöpfer, Andrej Janchevski, Anja Tiede, Clarence Linden, Emanuele Troiani, Francesco Salvi, Freya Behrens, Giacomo Orsi, Giovanni Piccioli, Hadrien Sevel, Louis Coulon, Manuela Pineros-Rodriguez, Marin Bonnassies, Pierre Hellich, Puck van Gerwen, Sankalp Gambhir, Solal Pirelli, Thomas Blanchard, Timothée Callens, Toni Abi Aoun, Yannick Calvino Alonso, Yuri Cho, Alberto Silvio Chiappa, Antonio Sclocchi, Étienne Bruno, Florian Hofhammer, Gabriel Pescia, Geovani Rizk, Leello Dadi, Lucas Stoffl, Manoel Horta Ribeiro, Matthieu Bovel, Yueyang Pan, Aleksandra Radenovic, Alexandre Alahi, Alexander Mathis, Anne-Florence Bitbol, Boi Faltings, Cécile Hébert, Devis Tuia, François Maréchal, George Candea, Giuseppe Carleo, Jean-Cédric Chappelier, Nicolas Flammarion, Jean-Marie Fürbringer, Jean-Philippe Pellet, Karl Aberer, Lenka Zdeborová, Marcel Salathé, Martin Jaggi, Martin Rajman, Mathias Payer, Matthieu Wyart, Michael Gastpar, Michele Ceriotti, Ola Svensson, Olivier Lévêque, Paolo Ienne, Rachid Guerraoui, Robert West, Sanidhya Kashyap, Valerio Piazza, Viesturs Simanis, Viktor Kuncak, Volkan Cevher, Philippe Schwaller, Sacha Friedli, Patrick Jermann, Tanja Käser, Antoine Bosselut:
Could ChatGPT get an Engineering Degree? Evaluating Higher Education Vulnerability to AI Assistants. CoRR abs/2408.11841 (2024) - 2023
- [j52]Jovan Blanusa, Kubilay Atasu, Paolo Ienne:
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. 10(3): 15:1-15:35 (2023) - [j51]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 16(4): 54:1-54:27 (2023) - [j50]Paolo Ienne:
Introduction to the Special Section on FPGA 2022. ACM Trans. Reconfigurable Technol. Syst. 16(4): 56:1-56:2 (2023) - [c164]Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA 2023: 39-45 - [c163]Stefan Nikolic, Paolo Ienne:
Regularity Matters: Designing Practical FPGA Switch-Blocks. FPGA 2023: 99-109 - [e6]Paolo Ienne, Zhiru Zhang:
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023. ACM 2023, ISBN 978-1-4503-9417-8 [contents] - [i3]Jovan Blanusa, Kubilay Atasu, Paolo Ienne:
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR abs/2301.01068 (2023) - 2022
- [j49]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [j48]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2142-2155 (2022) - [j47]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 15(1): 4:1-4:32 (2022) - [j46]Mikhail Asiatici, Paolo Ienne:
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(2): 13:1-13:33 (2022) - [j45]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. 15(4): 37:1-37:33 (2022) - [c162]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. FCCM 2022: 1-9 - [c161]Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL 2022: 253-261 - [c160]Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic:
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL 2022: 375-383 - [c159]Jovan Blanusa, Paolo Ienne, Kubilay Atasu:
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA 2022: 247-258 - [e5]Michael Adler, Paolo Ienne:
FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022. ACM 2022, ISBN 978-1-4503-9149-8 [contents] - [i2]Jovan Blanusa, Paolo Ienne, Kubilay Atasu:
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR abs/2202.09685 (2022) - 2021
- [j44]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. J. Signal Process. Syst. 93(12): 1405-1417 (2021) - [c158]Stefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne:
Global Is the New Local: FPGA Architecture at 5nm and Beyond. FPGA 2021: 34-44 - [c157]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. FPGA 2021: 226 - [c156]Stefan Nikolic, Paolo Ienne:
Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. FPL 2021: 225-233 - [c155]Mikhail Asiatici, Paolo Ienne:
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. ISCA 2021: 609-622 - 2020
- [j43]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. 13(11): 2676-2690 (2020) - [c154]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP 2020: 133-140 - [c153]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA 2020: 1-10 - [c152]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA 2020: 150-160 - [c151]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA 2020: 186-196 - [c150]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298 - [c149]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL 2020: 153-161 - [c148]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops 2020: 211-214
2010 – 2019
- 2019
- [j42]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne:
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access 7: 103938-103947 (2019) - [c147]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Speculative Dataflow Circuits. FPGA 2019: 162-171 - [c146]Anastasiia Kucherenko, Stefan Nikolic, Paolo Ienne:
On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. FPGA 2019: 188 - [c145]Mikhail Asiatici, Paolo Ienne:
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA 2019: 310-319 - [c144]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL 2019: 31-37 - [c143]Mikhail Asiatici, Paolo Ienne:
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL 2019: 254-262 - [c142]Gabor Csordas, Mikhail Asiatici, Paolo Ienne:
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT 2019: 188-196 - [c141]Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne:
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT 2019: 197-205 - 2018
- [c140]Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. AHS 2018: 74-81 - [c139]Lana Josipovic, Radhika Ghosal, Paolo Ienne:
Dynamically Scheduled High-level Synthesis. FPGA 2018: 127-136 - [c138]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). FPGA 2018: 294 - [c137]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA 2018: 295 - [c136]João Vieira, Nuno Roma, Pedro Tomás, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Exploiting Compute Caches for Memory Bound Vector Operations. SBAC-PAD 2018: 197-200 - [p2]Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne:
Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. Advanced Logic Synthesis 2018: 169-188 - 2017
- [j41]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - [j40]João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva:
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5: 14600-14615 (2017) - [j39]Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, Olivier Temam:
An Accelerator for High Efficient Vision Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 227-240 (2017) - [j38]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 125:1-125:19 (2017) - [c135]Lana Josipovic, Philip Brisk, Paolo Ienne:
From C to elastic circuits. ACSSC 2017: 121-125 - [c134]Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne:
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC 2017: 5:1-5:6 - [c133]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134 - [c132]Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA 2017: 135-140 - [c131]Grace Zgheib, Paolo Ienne:
Evaluating FPGA clusters under wide ranges of design parameters. FPL 2017: 1-8 - [c130]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - 2016
- [j37]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems 46: 219-220 (2016) - [j36]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers 65(4): 1006-1009 (2016) - [j35]Paolo Ienne, Jean-Pierre Talpin:
Guest Editorial: Special Issue on Models and Methodologies for System Design. ACM Trans. Embed. Comput. Syst. 15(2): 29:1-29:2 (2016) - [j34]Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi:
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3489-3498 (2016) - [c129]Francesco Regazzoni, Paolo Ienne:
Instruction Set Extensions for secure applications. DATE 2016: 1529-1534 - [c128]Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne:
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA 2016: 80-89 - [c127]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - [c126]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [c125]Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko:
Fast hierarchical NPN classification. FPL 2016: 1-4 - [c124]Lana Josipovic, Nithin George, Paolo Ienne:
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT 2016: 177-180 - [c123]Grace Zgheib, Paolo Ienne:
Automatic wire modeling to explore novel FPGA architectures. FPT 2016: 181-184 - [c122]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c121]Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner:
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. ICCAD 2016: 95 - [c120]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [e4]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j33]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers 64(2): 329-341 (2015) - [j32]Xavier Jimenez, David Novo, Paolo Ienne:
Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash. ACM Trans. Embed. Comput. Syst. 14(2): 28:1-28:22 (2015) - [j31]Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14(2): 33:1-33:23 (2015) - [c119]Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu:
Retraining-based timing error mitigation for hardware neural networks. DATE 2015: 593-596 - [c118]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM 2015: 97 - [c117]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL 2015: 1-8 - [c116]Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne:
Automatic support for multi-module parallelism from computational patterns. FPL 2015: 1-8 - [c115]Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8 - [c114]Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne:
Improved carry chain mapping for the VTR flow. FPT 2015: 80-87 - [c113]Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne:
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference 2015: 259-275 - [c112]Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam:
ShiDianNao: shifting vision processing closer to the sensor. ISCA 2015: 92-104 - [c111]Panagiotis Skrimponis, Georgios Zindros, Ioannis Parnassos, Muhsen Owaida, Nikolaos Bellas, Paolo Ienne:
Exploring Automatically Generated Platforms in High Performance FPGAs. PARCO 2015: 563-570 - [e3]Yunji Chen, Paolo Ienne, Qing Ji:
Advanced Parallel Processing Technologies - 11th International Symposium, APPT 2015, Jinan, China, August 20-21, 2015, Proceedings. Lecture Notes in Computer Science 9231, Springer 2015, ISBN 978-3-319-23215-7 [contents] - 2014
- [j30]Walid A. Najjar, Paolo Ienne:
Reconfigurable Computing. IEEE Micro 34(1): 4-6 (2014) - [j29]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. 11(2): 15:1-15:26 (2014) - [j28]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 62-75 (2014) - [c110]Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu:
A low-cost memory interface for high-throughput accelerators. CASES 2014: 11:1-11:10 - [c109]Andrew Becker, David Novo, Paolo Ienne:
SKETCHILOG: Sketching combinational circuits. DATE 2014: 1-4 - [c108]David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor:
Energy efficient MIMO processing: A case study of opportunistic run-time approximations. DATE 2014: 1-6 - [c107]Xavier Jimenez, David Novo, Paolo Ienne:
Wear unleveling: improving NAND flash lifetime by balancing page endurance. FAST 2014: 47-59 - [c106]Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. FPGA 2014: 45-54 - [c105]Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne:
Hardware system synthesis from Domain-Specific Languages. FPL 2014: 1-8 - [c104]Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne:
Constrained interpolation for guided logic synthesis. ICCAD 2014: 462-469 - 2013
- [j27]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - [c103]Andrew Becker, David Novo, Paolo Ienne:
Automated circuit elaboration from incomplete architectural descriptions. ACSSC 2013: 391-395 - [c102]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Paolo Ienne:
Sleuth: Automated Verification of Software Power Analysis Countermeasures. CHES 2013: 293-310 - [c101]David Novo, Sara El Alaoui, Paolo Ienne:
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. DATE 2013: 15-20 - [c100]Xavier Jimenez, David Novo, Paolo Ienne:
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. DATE 2013: 226-229 - [c99]Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. DATE 2013: 410-415 - [c98]Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508 - [c97]Madhura Purnaprajna, Paolo Ienne:
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM 2013: 53-56 - [c96]Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu:
Elastic CGRAs. FPGA 2013: 171-180 - [c95]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 - [c94]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. FPL 2013: 1-4 - [c93]Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne:
Making domain-specific hardware synthesis tools cost-efficient. FPT 2013: 120-127 - [c92]Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo Ienne:
Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement. NAS 2013: 31-40 - [c91]David Novo, I. Tzimi, Ubaid Ahmad, Paolo Ienne, Francky Catthoor:
Cracking the complexity of fixed-point refinement in complex wireless systems. SiPS 2013: 18-23 - 2012
- [j26]Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne P. Burleson:
An architecture-independent instruction shuffler to protect against side-channel attacks. ACM Trans. Archit. Code Optim. 8(4): 20:1-20:19 (2012) - [j25]Madhura Purnaprajna, Paolo Ienne:
Making wide-issue VLIW processors viable on FPGAs. ACM Trans. Archit. Code Optim. 8(4): 33:1-33:16 (2012) - [j24]Elisardo Antelo, David Hough, Paolo Ienne:
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 61(8): 1057-1058 (2012) - [c90]Xavier Jimenez, David Novo, Paolo Ienne:
Software controlled cell bit-density to improve NAND flash lifetime. DAC 2012: 229-234 - [c89]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548 - [c88]Shuai Jiao, Paolo Ienne, Xiaochun Ye, Da Wang, Dongrui Fan, Ninghui Sun:
CRAW/P: A Workload Partition Method for the Efficient Parallel Simulation of Manycores. Euro-Par 2012: 102-114 - [c87]Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM 2012: 224-231 - [c86]Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne:
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA 2012: 119-128 - [c85]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 - [c84]Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Counting stream registers: An efficient and effective snoop filter architecture. ICSAMOS 2012: 120-127 - [p1]Francesco Regazzoni, Luca Breveglieri, Paolo Ienne, Israel Koren:
Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks. Fault Analysis in Cryptography 2012: 257-272 - 2011
- [j23]Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne:
Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(4): 39:1-39:19 (2011) - [c83]Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
A first step towards automatic application of power analysis countermeasures. DAC 2011: 230-235 - [c82]Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici:
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC 2011: 1014-1019 - [c81]Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne:
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246 - [c80]Hadi Parandeh-Afshar, Paolo Ienne:
Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL 2011: 225-231 - [e2]Elisardo Antelo, David Hough, Paolo Ienne:
20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011. IEEE Computer Society 2011, ISBN 978-0-7695-4318-5 [contents] - [e1]Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca:
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1291-3 [contents] - 2010
- [j22]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 341-354 (2010) - [j21]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1096-1109 (2010) - [j20]Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 578-590 (2010) - [c79]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c78]Hadi Parandeh-Afshar, Paolo Ienne:
Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM 2010: 229-236 - [c77]Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24 - [c76]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC 2010: 126-140 - [c75]Xiaochun Ye, Dongrui Fan, Wei Lin, Nan Yuan, Paolo Ienne:
High performance comparison-based sorting algorithm on many-core GPUs. IPDPS 2010: 1-10
2000 – 2009
- 2009
- [j19]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. 13(1-2): 115-137 (2009) - [j18]Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. 4: 230-243 (2009) - [j17]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [j16]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. 2(3): 19:1-19:42 (2009) - [c74]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218 - [c73]Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209 - [c72]Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 - [c71]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36 - [c70]Claudio Favi, René Beuchat, Xavier Jimenez, Paolo Ienne:
From gates to multi-processors learning systems hands-on with FPGA4U in a computer science programme. WESE@ESWEEK 2009: 56-63 - [c69]Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270 - [c68]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - [c67]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249 - [c66]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 - [c65]Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 - [c64]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197 - [c63]Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696 - [c62]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD 2009: 797-804 - [c61]Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne:
Arithmetic optimization for custom instruction set synthesis. SASP 2009: 54-57 - [c60]Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne:
Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP 2009: 114-121 - [c59]Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120 - 2008
- [j15]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1761-1774 (2008) - [j14]Paolo Ienne, Peter Petrov:
Guest Editorial Special Section on Application Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1257-1258 (2008) - [c58]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143 - [c57]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339 - [c56]Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c55]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248 - [c54]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255 - [c53]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261 - [c52]Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren:
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. DFT 2008: 202-210 - [c51]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180 - [c50]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - [c49]Maurizio Skerlj, Paolo Ienne:
Error Protected Data Bus Inversion Using Standard DRAM Components. ISQED 2008: 35-42 - 2007
- [j13]Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 435-446 (2007) - [c48]Ajay Kumar Verma, Paolo Ienne:
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ASP-DAC 2007: 601-608 - [c47]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134 - [c46]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217 - [c45]Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 - [c44]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409 - [c43]Ajay Kumar Verma, Paolo Ienne:
Automatic synthesis of compressor trees: reevaluating large counters. DATE 2007: 443-448 - [c42]Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar:
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. DFT 2007: 508-516 - [c41]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179 - [c40]Frederic Worm, Patrick Thiran, Paolo Ienne:
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. ISQED 2007: 861-866 - [c39]Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214 - [i1]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. CoRR abs/0710.4820 (2007) - 2006
- [j12]Laura Pozzi, Kubilay Atasu, Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1209-1229 (2006) - [j11]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 754-762 (2006) - [j10]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 910-915 (2006) - [c38]Ajay Kumar Verma, Paolo Ienne:
Towards the automatic exploration of arithmetic-circuit architectures. DAC 2006: 445-450 - [c37]Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
Automatic identification of application-specific functional units with architecturally visible storage. DATE 2006: 212-217 - [c36]Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma:
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE 2006: 218-223 - [c35]Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele:
Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. FPT 2006: 197-204 - [c34]Frederic Worm, Patrick Thiran, Paolo Ienne:
Designing Robust Checkers in the Presence of Massive Timing Errors. IOLTS 2006: 281-286 - [c33]Mehmet Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici:
A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC 2006: 152-157 - [c32]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656 - 2005
- [j9]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Des. Test Comput. 22(2): 102-113 (2005) - [j8]Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli:
A robust self-calibrating transmission scheme for on-chip networks. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 126-139 (2005) - [c31]Frederic Worm, Patrick Thiran, Paolo Ienne:
A Unified Coding Framework for Delay-Insensitivity. ASYNC 2005: 201-211 - [c30]Laura Pozzi, Paolo Ienne:
Exploiting pipelining to relax register-file port constraints of instruction-set extensions. CASES 2005: 2-10 - [c29]Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne:
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. CODES+ISSS 2005: 243-248 - [c28]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251 - [c27]Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici:
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTIMedia 2005: 135-140 - [c26]Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne:
Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) 2005: 1782-1785 - [c25]Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli:
Self-calibrating networks-on-chip. ISCAS (3) 2005: 2361-2364 - 2004
- [j7]Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli:
On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. IEEE Des. Test Comput. 21(6): 524-535 (2004) - [c24]Marc Epalza, Paolo Ienne, Daniel Mlynek:
Adding Limited Reconfigurability to Superscalar Processors. IEEE PACT 2004: 53-62 - [c23]Marc Epalza, Paolo Ienne, Daniel Mlynek:
Dynamic Reallocation of Functional Units in Superscalar Processors. Asia-Pacific Computer Systems Architecture Conference 2004: 185-198 - [c22]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. ASAP 2004: 339-351 - [c21]Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt:
Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734 - [c20]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors. DAC 2004: 948-953 - [c19]Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne:
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. DATE 2004: 748 - [c18]Paolo Ienne, Ajay Kumar Verma:
Arithmetic Transformations to Maximise the Use of Compressor Trees. DELTA 2004: 219-224 - [c17]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. FCCM 2004: 24-33 - [c16]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. FPL 2004: 596-605 - [c15]Frederic Worm, Paolo Ienne, Patrick Thiran:
Soft self-synchronising codes for self-calibrating communication. ICCAD 2004: 440-447 - [c14]Ajay Kumar Verma, Paolo Ienne:
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ICCAD 2004: 791-798 - [c13]Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne:
Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. SoC 2004: 37-40 - [c12]Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne:
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES 2004: 17-32 - 2003
- [j6]Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. 31(6): 411-428 (2003) - [c11]Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli:
Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP 2003: 108- - [c10]Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC 2003: 256-261 - 2002
- [c9]Laura Pozzi, Miljan Vuletic, Paolo Ienne:
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. DATE 2002: 1138 - [c8]M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7 - [c7]Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm:
An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ISSS 2002: 92-100
1990 – 1999
- 1998
- [c6]Paolo Ienne, Alexander Grießing:
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? DAC 1998: 396-401 - 1997
- [j5]Paolo Ienne, Patrick Thiran, Nikolaos Vassilas:
Modified self-organizing feature map algorithms for efficient digital hardware implementation. IEEE Trans. Neural Networks 8(2): 315-330 (1997) - [c5]Paolo Ienne:
Digital Connectionist Hardware: Current Problems and Future Challenges. IWANN 1997: 688-713 - 1996
- [j4]Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, Marc A. Viredaz:
Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator. Sci. Program. 5(1): 47-61 (1996) - [j3]Paolo Ienne, Thierry Cornu, Gary Kuhn:
Special-purpose digital hardware for neural networks: An architectural survey. J. VLSI Signal Process. 13(1): 5-25 (1996) - [c4]Nikolaos Vassilas, Patrick Thiran, Paolo Ienne:
On modifications of Kohonen's feature map algorithm for an efficient parallel implementation. ICNN 1996: 932-937 - 1995
- [j2]Paolo Ienne, Marc A. Viredaz:
GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. J. VLSI Signal Process. 9(3): 257-273 (1995) - [c3]Paolo Ienne:
Horizontal Microcode Compaction for Programmable Systolic Accelerators. ASAP 1995: 85- - 1994
- [j1]Paolo Ienne, Marc A. Viredaz:
Bit-Serial Multipliers and Squarers. IEEE Trans. Computers 43(12): 1445-1450 (1994) - 1993
- [c2]Paolo Ienne, Marc A. Viredaz:
GENES IV: A bit-serial processing element for a built-model neural-network accelerator. ASAP 1993: 345-356 - [c1]Francesco Mondada, Edoardo Franzi, Paolo Ienne:
Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms. ISER 1993: 501-513
Coauthor Index
[j38] [c135] [c134] [c133] [c126] [e4] [j33] [j29] [j28] [j27] [c99] [c89] [c85] [c84] [j23] [c83] [c81] [j22] [j21] [j20] [c79] [c77] [c76] [j19] [j17] [j16] [c74] [c73] [c72] [c71] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [j15] [c58] [c57] [c56] [c55] [c54] [c53] [c51] [c50] [c47] [c46] [c45] [c44] [c41]
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