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ORCIDAndré DeHon
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- affiliation: University of Pennsylvania, Philadelphia, USA
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2020 – today
- 2024
[j35]Yuanlong Xiao
, Dongjoon Park, Zeyu Jason Niu, Aditya Hota, André DeHon:
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. ACM Trans. Reconfigurable Technol. Syst. 17(2): 21:1-21:28 (2024)- [c95]Dongjoon Park, André DeHon:
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. FPGA 2024: 108-118 - 2023
- [c94]Dongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon:
Asymmetry in Butterfly Fat Tree FPGA NoC. ICFPT 2023: 227-231 - 2022
- [j34]Nick Roessler, André DeHon:
SCALPEL: Exploring the Limits of Tag-enforced Compartmentalization. ACM J. Emerg. Technol. Comput. Syst. 18(1): 2:1-2:28 (2022) - [c93]Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon:
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. ASPLOS 2022: 933-945 - [c92]Yuanlong Xiao, André DeHon:
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. FPGA 2022: 155 - [c91]Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon:
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. FPL 2022: 70-78 - [c90]Dongjoon Park, Yuanlong Xiao, André DeHon:
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. FPT 2022: 1-10 - 2021
- [j33]João M. P. Cardoso, André DeHon, Laura Pozzi:
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems. IEEE Trans. Computers 70(12): 2013-2014 (2021) - [c89]Nikos Vasilakis, Cristian-Alexandru Staicu, Grigoris Ntousakis, Konstantinos Kallas, Ben Karel, André DeHon, Michael Pradel:
Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction. CCS 2021: 1821-1838 - [c88]Matthew Hofmann, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson, André DeHon:
XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion. FCCM 2021: 1-9 - [c87]Eric Micallef, Yuanlong Xiao, André DeHon:
HLS-Compatible, Embedded-Processor Stream Links. FCCM 2021: 214-218 - [c86]Nik Sultana, John Sonchack, Hans Giesen, Isaac Pedisich, Zhaoyang Han, Nishanth Shyamkumar, Shivani Burad, André DeHon, Boon Thau Loo:
Flightplan: Dataplane Disaggregation and Placement for P4 Programs. NSDI 2021: 571-592 - [c85]Nick Roessler, Lucas Atayde, Imani Palmer, Derrick Paul McKee, Jai Pandey, Vasileios P. Kemerlis, Mathias Payer, Adam Bates, Jonathan M. Smith, André DeHon, Nathan Dautenhahn:
μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts. RAID 2021: 296-311 - [i5]André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao:
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation. CoRR abs/2104.01929 (2021) - 2020
- [j32]André DeHon:
Introduction to Special Section on FCCM 2019. ACM Trans. Reconfigurable Technol. Syst. 13(4): 17:1-17:2 (2020) - [c84]Joel Hypolite, John Sonchack, Shlomo Hershkop, Nathan Dautenhahn, André DeHon, Jonathan M. Smith:
DeepMatch: practical deep packet inspection in the data plane using network processors. CoNEXT 2020: 336-350 - [c83]Yuanlong Xiao, Syed Tousif Ahmed, André DeHon:
Fast Linking of Separately-Compiled FPGA Blocks without a NoC. FPT 2020: 196-205 - [i4]Nikos Vasilakis, Cristian-Alexandru Staicu, Greg Ntousakis, Konstantinos Kallas, Ben Karel, André DeHon, Michael Pradel:
Mir: Automated Quantifiable Privilege Reduction Against Dynamic Library Compromise in JavaScript. CoRR abs/2011.00253 (2020)
2010 – 2019
- 2019
- [c82]Vipula Sateesh, Connor Mckeon, Jared Winograd, André DeHon:
Pipelined Parallel Finite Automata Evaluation. FPT 2019: 108-116 - [c81]Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon:
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. FPT 2019: 153-161 - [c80]Nikos Vasilakis, Ben Karel, Yash Palkhiwala, John Sonchack, André DeHon, Jonathan M. Smith:
Ignis: scaling distribution-oblivious systems with light-touch distribution. PLDI 2019: 1010-1026 - 2018
- [j31]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). ACM Trans. Reconfigurable Technol. Syst. 11(1): 3:1-3:23 (2018) - [c79]Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon:
Case for Fast FPGA Compilation Using Partial Reconfiguration. FPL 2018: 235-238 - [c78]Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, André DeHon, Jonathan M. Smith:
BreakApp: Automated, Flexible Application Compartmentalization. NDSS 2018 - [c77]Hans Giesen, Lei Shi, John Sonchack, Anirudh Chelluri, Nishanth Prabhu, Nik Sultana, Latha A. Kant, Anthony J. McAuley, Alexander Poylisher, André DeHon, Boon Thau Loo:
In-network computing to the rescue of faulty links. NetCompute@SIGCOMM 2018: 1-6 - [c76]Nick Roessler, André DeHon:
Protecting the Stack with Metadata Policies and Tagged Hardware. IEEE Symposium on Security and Privacy 2018: 478-495 - 2017
- [j30]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Self-Adaptive Timing Repair. IEEE Des. Test 34(6): 54-62 (2017) - [c75]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. FPGA 2017: 85-94 - [c74]Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, André DeHon, Jonathan M. Smith:
Towards Fine-grained, Automated Application Compartmentalization. PLOS@SOSP 2017: 43-50 - 2016
- [j29]Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach:
A verified information-flow architecture. J. Comput. Secur. 24(6): 689-734 (2016) - [j28]Edin Kadric, Paul Gurniak, André DeHon:
Accurate Parallel Floating-Point Accumulation. IEEE Trans. Computers 65(11): 3224-3238 (2016) - [j27]André DeHon, Derek Chiou:
Introduction to Special Issue on Reconfigurable Components with Source Code. ACM Trans. Reconfigurable Technol. Syst. 9(3): 19:1-19:2 (2016) - [j26]Edin Kadric, David Lakata, André DeHon:
Impact of Parallelism and Memory Architecture on FPGA Communication Energy. ACM Trans. Reconfigurable Technol. Syst. 9(4): 30:1-30:23 (2016) - [c73]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). FCCM 2016: 111-118 - [c72]Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, André DeHon:
Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. FCCM 2016: 172-175 - [c71]Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon:
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. FPGA 2016: 100-104 - [c70]David K. Wittenberg, Edin Kadric, André DeHon, Jonathan Edwards, Jeffrey Smith, Silviu Chiricescu:
PERFECT case studies demonstrating order of magnitude reduction in power consumption. HPEC 2016: 1-7 - 2015
- [j25]Russell Tessier, Kenneth L. Pocek, André DeHon:
Reconfigurable Computing Architectures. Proc. IEEE 103(3): 332-354 (2015) - [j24]André DeHon:
Fundamental Underpinnings of Reconfigurable Computing Architectures. Proc. IEEE 103(3): 355-378 (2015) - [j23]Udit Dhawan, André DeHon:
Area-Efficient Near-Associative Memories on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(4): 30:1-30:22 (2015) - [j22]Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction. ACM Trans. Reconfigurable Technol. Syst. 7(4): 32:1-32:23 (2015) - [c69]Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon:
Architectural Support for Software-Defined Metadata Processing. ASPLOS 2015: 487-502 - [c68]Edin Kadric, David Lakata, André DeHon:
Impact of Memory Architecture on FPGA Energy Consumption. FPGA 2015: 146-155 - [c67]Hyunseok Park, Shreel Vijayvargiya, André DeHon:
Energy minimization in the time-space continuum. FPT 2015: 64-71 - [i3]Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach:
A Verified Information-Flow Architecture. CoRR abs/1509.06503 (2015) - 2014
- [c66]Benjamin Gojman, André DeHon:
GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction. FCCM 2014: 88-95 - [c65]Edin Kadric, Kunal Mahajan, André DeHon:
Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations. FCCM 2014: 214-221 - [c64]Edin Kadric, Kunal Mahajan, André DeHon:
Energy Reduction through Differential Reliability and Lightweight Checking. FCCM 2014: 243-250 - [c63]André DeHon:
Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization. FPGA 2014: 189-198 - [c62]Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith, André DeHon:
RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks. FPT 2014: 183-190 - [c61]Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon:
PUMP: a programmable unit for metadata processing. HASP@ISCA 2014: 8:1-8:8 - [c60]Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach:
A verified information-flow architecture. POPL 2014: 165-178 - 2013
- [c59]Edin Kadric, Paul Gurniak, André DeHon:
Accurate Parallel Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic 2013: 153-162 - [c58]Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., André DeHon:
Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security. CCS 2013: 721-732 - [c57]Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. FPGA 2013: 81-90 - [c56]André DeHon:
Location, location, location: the role of spatial locality in asymptotic energy minimization. FPGA 2013: 137-146 - [c55]Udit Dhawan, André DeHon:
Area-efficient near-associative memories on FPGAs. FPGA 2013: 191-200 - [c54]André DeHon, Nikil Mehta:
Exploiting partially defective LUTs: Why you don't need perfect fabrication. FPT 2013: 12-19 - 2012
- [j21]Nachiket Kapre, André DeHon:
${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 9-22 (2012) - [c53]Nikil Mehta, Raphael Rubin, André DeHon:
Limit study of energy & delay benefits of component-specific routing. FPGA 2012: 97-106 - [c52]Yutian Huan, André DeHon:
FPGA optimized packet-switched NoC using split and merge primitives. FPT 2012: 47-52 - [c51]Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, André DeHon, Gregory Malecha, Greg Morrisett, Thomas F. Knight Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David K. Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan:
Hardware Support for Safety Interlocks and Introspection. SASO Workshops 2012: 1-8 - 2011
- [j20]André DeHon, Benjamin Gojman:
Crystals and Snowflakes: Building Computation from Nanowire Crossbars. Computer 44(2): 37-45 (2011) - [j19]Nachiket Kapre, André DeHon:
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. Int. J. Reconfigurable Comput. 2011: 745147:1-745147:14 (2011) - [j18]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, André DeHon:
Spatial hardware implementation for sparse graph algorithms in GraphStep. ACM Trans. Auton. Adapt. Syst. 6(3): 17:1-17:20 (2011) - [j17]Raphael Rubin, André DeHon:
Choose-your-own-adventure routing: Lightweight load-time defect avoidance. ACM Trans. Reconfigurable Technol. Syst. 4(4): 33:1-33:24 (2011) - [c50]Raphael Rubin, André DeHon:
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. FPGA 2011: 173-176 - [c49]Nachiket Kapre, André DeHon:
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. FPT 2011: 1-9 - [c48]André DeHon, Ben Karel, Thomas F. Knight Jr., Gregory Malecha, Benoît Montagu, Robin Morisset, Greg Morrisett, Benjamin C. Pierce, Randy Pollack, Sumit Ray, Olin Shivers, Jonathan M. Smith, Gregory Sullivan:
Preliminary design of the SAFE platform. PLOS@SOSP 2011: 4:1-4:5 - [p3]Nikil Mehta, André DeHon:
Low-Power Techniques for FPGAs. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 337-363 - [p2]Nikil Mehta, André DeHon:
Variation and Aging Tolerance in FPGAs. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 365-380 - [p1]Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon:
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 381-432 - 2010
- [c47]André DeHon, Heather M. Quinn, Nicholas P. Carter:
Vision for cross-layer optimization to address the dual challenges of energy and reliability. DATE 2010: 1017-1022 - [c46]Nachiket Kapre, André DeHon:
An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications. ReCoSoC 2010: 87-94
2000 – 2009
- 2009
- [j16]Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon:
Inversion schemes for sublithographic programmable logic arrays. IET Comput. Digit. Tech. 3(6): 625-642 (2009) - [j15]Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon:
Pipelining Saturated Accumulation. IEEE Trans. Computers 58(2): 208-219 (2009) - [j14]Helia Naeimi, André DeHon:
Fault Secure Encoder and Decoder for NanoMemory Applications. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 473-486 (2009) - [c45]Nachiket Kapre, André DeHon:
Accelerating SPICE Model-Evaluation using FPGAs. FCCM 2009: 37-44 - [c44]Raphael Rubin, André DeHon:
Choose-your-own-adventure routing: lightweight load-time defect avoidance. FPGA 2009: 23-32 - [c43]Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger:
CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 - [c42]Nachiket Kapre, André DeHon:
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. FPL 2009: 65-72 - [c41]Benjamin Gojman, André DeHon:
VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems. FPT 2009: 78-87 - 2008
- [j13]André DeHon, Mike Hutton:
Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1(1): 2:1-2:3 (2008) - 2007
- [j12]André DeHon, Craig S. Lent, Fabrizio Lombardi:
Introduction to the Special Section on Nano Systems and Computing. IEEE Trans. Computers 56(2): 145-146 (2007) - [j11]Kia Bazargan, André DeHon:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 201-202 (2007) - [c40]Nachiket Kapre, André DeHon:
Optimistic Parallelization of Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic 2007: 205-216 - [c39]Helia Naeimi, André DeHon:
Fault Secure Encoder and Decoder for Memory Applications. DFT 2007: 409-417 - [c38]André DeHon:
Architecture approaching the atomic scale. ESSCIRC 2007: 11-20 - [c37]Helia Naeimi, André DeHon:
Fault tolerant nano-memory with fault secure encoder and decoder. Nano-Net 2007: 2 - [e3]André DeHon, Jean-Louis Giavitto, Frédéric Gruau:
Computing Media and Languages for Space-Oriented Computation, 03.09. - 08.09.2006. Dagstuhl Seminar Proceedings 06361, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2007 [contents] - [e2]André DeHon, Mike Hutton:
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007. ACM 2007, ISBN 978-1-59593-600-4 [contents] - [i2]André DeHon, Jean-Louis Giavitto, Frédéric Gruau:
06361 Executive Report -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation 2007 - [i1]André DeHon, Jean-Louis Giavitto, Frédéric Gruau:
06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation 2007 - 2006
- [j10]John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, Yue Wu:
Radial addressing of nanowires. ACM J. Emerg. Technol. Comput. Syst. 2(2): 129-154 (2006) - [j9]André DeHon, Randy Huang, John Wawrzynek:
Stochastic spatial routing for reconfigurable networks. Microprocess. Microsystems 30(6): 301-318 (2006) - [j8]André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek:
Stream computations organized for reconfigurable execution. Microprocess. Microsystems 30(6): 334-354 (2006) - [c36]Michael G. Wrighton, André DeHon:
SAT-based optimal hypergraph partitioning with replication. ASP-DAC 2006: 789-795 - [c35]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon:
GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM 2006: 143-151 - [c34]Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon:
Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM 2006: 205-216 - [c33]Rajiv V. Joshi, Kaustav Banerjee, André DeHon:
Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4 - [c32]Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto:
3D Nanowire-Based Programmable Logic. Nano-Net 2006: 1-5 - [c31]Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon:
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net 2006: 1-5 - [e1]Steven J. E. Wilton, André DeHon:
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006. ACM 2006, ISBN 1-59593-292-5 [contents] - 2005
- [j7]André DeHon, Helia Naeimi:
Seven Strategies for Tolerating Highly Defective Fabrication. IEEE Des. Test Comput. 22(4): 306-315 (2005) - [j6]André DeHon:
Nanowire-based programmable architectures. ACM J. Emerg. Technol. Comput. Syst. 1(2): 109-162 (2005) - [c30]Michael DeLorimier, André DeHon:
Floating-point sparse matrix-vector multiply for FPGAs. FPGA 2005: 75-85 - [c29]André DeHon:
Design of programmable interconnect for sublithographic programmable logic arrays. FPGA 2005: 127-137 - [c28]Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon:
Pipelining Saturated Accumulation. FPT 2005: 19-26 - [c27]André DeHon, Konstantin Likharev:
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. ICCAD 2005: 375-382 - 2004
- [j5]André DeHon, Raphael Rubin:
Design of FPGA interconnect for multilevel metallization. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1038-1050 (2004) - [j4]André DeHon:
Unifying mesh- and tree-based programmable interconnect. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1051-1065 (2004) - [c26]André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton:
Design Patterns for Reconfigurable Computing. FCCM 2004: 13-23 - [c25]André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica:
What is the right model for programming and using modern FPGAs? FPGA 2004: 119 - [c24]André DeHon, Michael J. Wilson:
Nanowire-based sublithographic programmable logic arrays. FPGA 2004: 123-132 - [c23]Helia Naeimi, André DeHon:
A greedy algorithm for tolerating defective crosspoints in nanoPLA design. FPT 2004: 49-56 - 2003
- [c22]Michael G. Wrighton, André DeHon:
Hardware-assisted simulated annealing with application for fast FPGA placement. FPGA 2003: 33-42 - [c21]Randy Huang, John Wawrzynek, André DeHon:
Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA 2003: 78-87 - [c20]Raphael Rubin, André DeHon:
Design of FPGA interconnect for multilevel metalization. FPGA 2003: 154-163 - 2002
- [c19]André DeHon, Randy Huang, John Wawrzynek:
Hardware-Assisted Fast Routing. FCCM 2002: 205- - [c18]Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon:
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA 2002: 196-205 - [c17]Michael Butts, André DeHon, Seth Copen Goldstein:
Molecular electronics: devices, systems and tools for gigagate, gigabit chips. ICCAD 2002: 433-440 - [c16]André DeHon:
Very Large Scale Spatial Computing. UMC 2002: 27-36 - 2001
- [c15]André DeHon:
Rent's rule based switching requirements. SLIP 2001: 197-204 - 2000
- [j3]André DeHon:
The Density Advantage of Configurable Computing. Computer 33(4): 41-49 (2000) - [c14]Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon:
Stream Computations Organized for Reconfigurable Execution (SCORE). FPL 2000: 605-614 - [c13]André DeHon:
Compact, multilayer layout for butterfly fat-tree. SPAA 2000: 206-215
1990 – 1999
- 1999
- [c12]André DeHon, John Wawrzynek:
Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC 1999: 610-615 - [c11]André DeHon:
Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). FPGA 1999: 69-78 - [c10]William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon:
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA 1999: 125-134 - 1998
- [j2]André DeHon, Thomas F. Knight Jr.:
High Performance, Point-to-Point, Transmission Line Signaling. VLSI Design 7(1): 111-129 (1998) - [c9]Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek:
Object Oriented Circuit-Generators in Java. FCCM 1998: 158-166 - [c8]Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek:
Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA 1998: 123-132 - 1997
- [j1]William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg:
Seeking Solutions in Configurable Computing. Computer 30(12): 38-43 (1997) - [c7]André DeHon:
Directions in General-Purpose Computing Architectures. HICSS (1) 1997: 717-718 - 1996
- [b1]André DeHon:
Reconfigurable architectures for general-purpose computing. Massachusetts Institute of Technology, Cambridge, MA, USA, 1996 - [c6]Ethan Mirsky, André DeHon:
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. FCCM 1996: 157-166 - [c5]André DeHon:
Entropy, Counting, and Programmable Interconnect. FPGA 1996: 73-79 - [c4]André DeHon:
DPGA Utilization and Application. FPGA 1996: 115-121 - 1994
- [c3]Frederic T. Chong, Henry Minsky, André DeHon, Matthew E. Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.:
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. ISCA 1994: 266-277 - [c2]André DeHon:
In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. ITC 1994: 350-359 - [c1]Ian Eslick, André DeHon, Thomas F. Knight Jr.:
Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks. PCRCW 1994: 215-225
Coauthor Index
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For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-05 21:16 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
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