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ORCIDISLPED 2012: Redondo Beach, CA, USA
- Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera:
International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. ACM 2012, ISBN 978-1-4503-1249-3
Keynote address
- Pradip Bose:
Energy-secure computing. 1-2
Circuits in emerging techniques
- Yusung Kim
, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy:
Write-optimized reliable design of STT MRAM. 3-8 - Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy:
High-performance low-energy STT MRAM based on balanced write scheme. 9-14 - Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao:
Design benchmarking to 7nm with FinFET predictive technology models. 15-20
Tools for physical design and architecture simulation
- Xin Zhao, Sung Kyu Lim:
TSV array utilization in low-power 3D clock network design. 21-26 - Song Chen, Xiaolin Zhang, Takeshi Yoshimura:
Practically scalable floorplanning with voltage island generation. 27-32 - Ehsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau:
Thermal-aware sampling in architectural simulation. 33-38
Caches, memories, and interconnect
- Lei Jiang, Youtao Zhang, Jun Yang:
ER: elastic RESET for low power and long endurance MLC based phase change memory. 39-44 - Zhenyu Sun, Hai Li, Wenqing Wu:
A dual-mode architecture for fast-switching STT-RAM. 45-50 - Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
ASCIB: adaptive selection of cache indexing bits for removing conflict misses. 51-56 - Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai:
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. 57-62
Industry focus session on low power design
- Clive Bittlestone, Jim Kardach, Renu Mehra, David Flynn, Barry M. Pangrle:
Industry focus session on low-power design. 63-64 - Jim Kardach:
Advances in ultrabook™ platform power management. 65-66 - Renu Mehra:
Commercial low-power EDA tools: a review. 67-72 - David Flynn:
An ARM perspective on addressing low-power energy-efficient SoC designs. 73-78
Low power SRAM
- Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang:
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. 79-84 - Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. 85-90 - Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David T. Blaauw, Dennis Sylvester:
An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs. 91-96
System level power optimization
- Da-Cheng Juan, Diana Marculescu:
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors. 97-102 - Woojoo Lee, Yanzhi Wang, Donghwa Shin, Naehyuck Chang, Massoud Pedram:
Power conversion efficiency characterization and optimization for smartphones. 103-108 - Yanzhi Wang, Xue Lin, Naehyuck Chang, Massoud Pedram:
Dynamic reconfiguration of photovoltaic energy harvesting system in hybrid electric vehicles. 109-114 - Sangyoung Park, Yanzhi Wang, Younghyun Kim, Naehyuck Chang, Massoud Pedram:
Battery management for grid-connected PV systems with a battery. 115-120
Panel
- Kenneth Wagner, Martin St. Laurent, Robert C. Aitken, Hugh Barrass, Randall Robinson:
Panel: going green across communications and storage systems: control of power in non-mobile devices. 121-122
Low power design and validation methodologies
- Elif S. Mungan, Chao Lu, Vijay Raghunathan, Kaushik Roy:
Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. 123-128 - Jérôme Lescot, Vincent Bligny, Dina Medhat, Didier Chollat-Namy, Ziyang Lu, Sophie Billy, Mark Hofmann:
Static low power verification at transistor level for SoC design. 129-134 - Lu Wan, Deming Chen:
CCP: common case promotion for improved timing error resilience with energy efficiency. 135-140 - Mirko Loghi, Haroon Mahmood, Andrea Calimera, Massimo Poncino, Enrico Macii:
Energy-optimal caches with guaranteed lifetime. 141-146
Keynote address 2
- Kaushik Roy:
Spin as state variable for computation: prospects and perspectives. 147-148
Digital techniques
- Eric Donkoh, Teck Siong Ong, Yan Nee Too, Patrick Chiang:
Register file write data gating techniques and break-even analysis model. 149-154 - Eric Donkoh, Patrick Chiang:
A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability. 155-160 - Mingoo Seok:
A fine-grained many VT design methodology for ultra low voltage operations. 161-166 - Kyle Craig, Yousef Shakhsheer, Sudhanshu Khanna, Saad Arrabi, John C. Lach, Benton H. Calhoun, Stephen Kosonocky:
A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs. 167-172
Energy efficiency and non-volatile memories
- Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen:
Improving energy efficiency of write-asymmetric memories by log style write. 173-178 - Zhenyu Sun, Xiuyuan Bi, Hai Li:
Process variation aware data management for STT-RAM cache design. 179-184 - Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
TapeCache: a high density, energy efficient cache based on domain wall memory. 185-190 - Yong Li, Yiran Chen, Alex K. Jones:
A software approach for combating asymmetries of non-volatile memories. 191-196 - Yuhao Wang, Chun Zhang, Hao Yu, Wei Zhang:
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention. 197-202
Poster Session
- Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong:
TAP: token-based adaptive power gating. 203-208 - Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design trade-offs for high density cross-point resistive memory. 209-214 - Mingoo Seok:
Performance and energy-efficiency improvement through modified CPL in organic transistor integrated circuits. 215-220 - Kyle Craig, Yousef Shakhsheer, Benton H. Calhoun:
Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation. 221-224 - Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman:
BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs. 225-230 - Jongmin Lee, Soontae Kim:
Adopting TLB index-based tagging to data caches for tag energy reduction. 231-236 - Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar, Glenn Reinman:
Static and dynamic co-optimizations for blocks mapping in hybrid caches. 237-242 - Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir:
Design space exploration of workload-specific last-level caches. 243-248 - Debashis Banerjee, Shreyas Sen, Aritra Banerjee, Abhijit Chatterjee:
Low-power adaptive RF system design using real-time fuzzy noise-distortion control. 249-254 - Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty:
Designing for dark silicon: a methodological perspective on energy efficient systems. 255-260 - Davide Zoni, Simone Corbetta, William Fornaciari:
HANDS: heterogeneous architectures and networks-on-chip design and simulation. 261-266 - Svilen Kanev, Gu-Yeon Wei, David M. Brooks:
XIOSim: power-performance modeling of mobile x86 cores. 267-272 - Wei Zheng, Ana Paula Centeno, Frederic T. Chong, Ricardo Bianchini:
LogStore: toward energy-proportional storage servers. 273-278 - Yang Ge, Yukan Zhang, Qinru Qiu, Yung-Hsiang Lu:
A game theoretic resource allocation for overall energy minimization in mobile cloud computing system. 279-284 - Himanshu Markandeya, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy:
A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability. 285-290 - Matthew Schuchhardt, Benjamin Scholbrock, Utku Pamuksuz, Gokhan Memik, Peter A. Dinda, Robert P. Dick:
Understanding the impact of laptop power saving options on user satisfaction using physiological sensors. 291-296 - Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini:
MultiScale: memory system DVFS with multiple memory controllers. 297-302 - James B. Wendt, Saro Meguerdichian, Hyduke Noshadi, Miodrag Potkonjak:
Semantics-driven sensor configuration for energy reduction in medical sensor networks. 303-308
Innovations in low power analog
- Tetsutaro Hashimoto, Satoshi Tanabe, Kouichi Nakayama, Hisanori Fujisawa:
Voltage droop reduction for multiple-power domain SoCs with on-die LDO using output voltage boost and adaptive response scaling. 309-314 - Nicola Cottini, Massimo Gottardi, Nicola Massari, Roberto Passerone, Zeev Smilansky:
A 33μW 42 GOPS/W 64x64 pixel vision sensor with dynamic background subtraction for scene interpretation. 315-320 - Anvesha Amaravati, Maryam Shojaei Baghini:
Process and temperature invariant bandwidth and gain, low-area, low-power and high swing Gm-C filter for multichannel neuro-potential signal conditioning. 321-326 - Aatmesh Shrivastava, John C. Lach, Benton H. Calhoun:
A charge pump based receiver circuit for voltage scaled interconnect. 327-332 - Akira Saito, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS. 333-338
Software-driven techniques for energy efficiency in embedded and multi-core systems
- Inkwon Hwang, Timothy Kam, Massoud Pedram:
A study of the effectiveness of CPU consolidation in a virtualized multi-core server system. 339-344 - Jason Cong, Bo Yuan:
Energy-efficient scheduling on heterogeneous multi-core architectures. 345-350 - Qing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yanxiang He:
MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems. 351-356 - Hassan Ghasemzadeh, Navid Amini, Majid Sarrafzadeh:
Energy-efficient signal processing in wearable embedded systems: an optimal feature selection approach. 357-362
Embedded tutorial
- Hwisung Jung:
Advanced power and thermal management for low-power, high-performance smartphones. 363-364
Keynote address 3
- Uming Ko:
Ultra-low power challenges for the next generation ASIC. 365-366
Processor design and implementation
- Aaron Rogers, David Kaplan, Eric Quinnell, Bill Kwan:
The core-C6 (CC6) sleep state of the AMD bobcat x86 microprocessor. 367-372 - Sae Kyu Lee, David M. Brooks, Gu-Yeon Wei:
Evaluation of voltage stacking for near-threshold multicore computing. 373-378 - Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman:
CHARM: a composable heterogeneous accelerator-rich microprocessor. 379-384 - Yasuko Eckert, Srilatha Manne, Michael J. Schulte, David A. Wood:
Something old and something new: P-states can borrow microarchitecture techniques too. 385-390
Memory management and scheduling
- Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee:
Reducing L1 caches power by exploiting software semantics. 391-396 - Sukki Kim, Soontae Kim, Yebin Lee:
DRAM power-aware rank scheduling. 397-402 - Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie:
Energy-efficient GPU design with reconfigurable in-package graphics memory. 403-408 - Christine S. Chan, Yanqin Jin, Yen-Kuan Wu, Kenny C. Gross, Kalyan Vaidyanathan, Tajana Simunic Rosing:
Fan-speed-aware scheduling of data intensive jobs. 409-414 - Abbas Rahimi, Luca Benini, Rajesh Gupta:
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters. 415-420
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