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2020 – today
- 2022
[c84]Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. ISOCC 2022: 169-170- 2021
- [j30]Wei Lu
, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 776-788 (2021) - [j29]Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang:
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. IEEE Open J. Circuits Syst. 2: 131-143 (2021) - [c83]Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang:
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. ISOCC 2021: 260-261 - 2020
- [c82]Chin-Yang Lo, Po-Tsang Huang, Wei Hwang:
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. AICAS 2020: 320-323 - [c81]Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen:
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. SoCC 2020: 242-247
2010 – 2019
- 2019
- [c80]I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang:
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. AICAS 2019: 42-45 - [c79]Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC 2019: 248-253 - 2018
- [c78]Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC 2018: 272-277 - [c77]Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT 2018: 1-4 - 2017
- [j28]Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. 11(5): 1013-1025 (2017) - [j27]Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang:
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1791-1802 (2017) - [j26]Chung-Shiang Wu, Hui-Hsuan Lee, Po-Hung Chen, Wei Hwang:
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 783-787 (2017) - [c76]Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS 2017: 1-4 - [c75]Yu-Hsuan Lin, Shih-Fan Peng, Wei Hwang:
Wide-I/O 3D-staked DRAM controller for near-data processing system. VLSI-DAT 2017: 1-4 - 2016
- [c74]Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS 2016: 1302-1305 - [c73]Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang:
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC 2016: 18-23 - 2015
- [c72]Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang:
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC 2015: 1-3 - [c71]Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang:
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. ISCAS 2015: 1370-1373 - [c70]Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang:
Energy-efficient gas recognition system with event-driven power control. SoCC 2015: 245-250 - [c69]Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT 2015: 1-4 - [c68]Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang:
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT 2015: 1-4 - 2014
- [j25]Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong:
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. 8(6): 810-823 (2014) - [j24]Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang:
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 188-192 (2014) - [j23]Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang:
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3416-3425 (2014) - [c67]Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang:
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC 2014: 129-132 - [c66]Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC 2014: 1-4 - [c65]Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC 2014: 1-4 - [c64]Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS 2014: 1841-1844 - [c63]Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong:
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC 2014: 320-321 - [c62]Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang:
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC 2014: 76-81 - [c61]Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC 2014: 136-139 - [c60]Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT 2014: 1-4 - 2013
- [j22]Dao-Ping Wang, Hon-Jarn Lin, Wei Hwang:
A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation. J. Low Power Electron. 9(1): 9-22 (2013) - [c59]Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen:
Low temperature (<180 °C) bonding for 3D integration. 3DIC 2013: 1-5 - [c58]Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS 2013: 238-241 - [c57]Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang:
Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. ISCAS 2013: 133-136 - [c56]Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih:
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS 2013: 1468-1471 - [c55]Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong:
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC 2013: 102-103 - [c54]Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang:
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. SoCC 2013: 92-97 - [c53]Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu:
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC 2013: 110-115 - 2012
- [j21]Po-Tsang Huang, Wei Hwang:
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electr. Comput. Eng. 2012: 697039:1-697039:19 (2012) - [j20]Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang:
A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. J. Low Power Electron. 8(1): 63-72 (2012) - [j19]Dao-Ping Wang, Wei Hwang:
A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. J. Low Power Electron. 8(4): 472-484 (2012) - [j18]Ming-Hung Chang, Yi-Te Chiu, Wei Hwang:
Design and Iso-Area Vmin Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 59-II(7): 429-433 (2012) - [j17]Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang:
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 863-867 (2012) - [j16]Wei-Chih Hsieh, Wei Hwang:
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 989-1001 (2012) - [c52]Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS 2012: 1831-1834 - [c51]Po-Jen Yang, Po-Tsang Huang, Wei Hwang:
Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS 2012: 3274-3277 - [c50]Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang:
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED 2012: 79-84 - [c49]Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang:
An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. SoCC 2012: 5-10 - [c48]Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC 2012: 218-223 - [c47]Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang:
On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC 2012: 370-375 - [c46]Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang:
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. VLSI-DAT 2012: 1-4 - [c45]Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih:
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT 2012: 1-4 - [c44]Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang:
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT 2012: 1-4 - 2011
- [j15]Po-Tsang Huang, Wei Hwang:
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(11): 2412-2424 (2011) - [j14]Po-Tsang Huang, Wei Hwang:
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. IEEE J. Solid State Circuits 46(2): 507-519 (2011) - [j13]Hao-I Yang, Wei Hwang, Ching-Te Chuang:
Impacts of gate-oxide breakdown on power-gated SRAM. Microelectron. J. 42(1): 101-112 (2011) - [j12]Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang:
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1239-1251 (2011) - [j11]Wei-Chih Hsieh, Wei Hwang:
Adaptive Power Control Technique on Power-Gated Circuitries. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1167-1180 (2011) - [j10]Hao-I Yang, Wei Hwang, Ching-Te Chuang:
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1192-1204 (2011) - [c43]Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang:
Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. ISLPED 2011: 15-20 - [c42]Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang:
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. ISLPED 2011: 291-296 - [c41]Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang:
An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. SoCC 2011: 19-23 - [c40]Po-Tsang Huang, Yung Chang, Wei Hwang:
On-demand memory sub-system for multi-core SoCs. SoCC 2011: 122-127 - [c39]Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC 2011: 197-200 - 2010
- [j9]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6(4): 551-562 (2010) - [c38]Ming-Hung Chang, Jung-Yi Wu, Wei-Chih Hsieh, Shang-Yuan Lin, You-Wei Liang, Wei Hwang:
High efficiency power management system for solar energy harvesting applications. APCCAS 2010: 879-882 - [c37]Wei-Chih Hsieh, Wei Hwang:
Low quiescent current variable output digital controlled voltage regulator. ISCAS 2010: 609-612 - [c36]Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, Wei Hwang:
Fully on-chip temperature, process, and voltage sensors. ISCAS 2010: 897-900 - [c35]Tien-Hung Lin, Po-Tsang Huang, Wei Hwang:
Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC 2010: 209-212
2000 – 2009
- 2009
- [c34]Hao-I Yang, Ching-Te Chuang, Wei Hwang:
Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS 2009: 377-380 - [c33]Yi-Ming Chang, Ming-Hung Chang, Wei Hwang:
A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. SoCC 2009: 115-118 - [c32]Po-Tsang Huang, Wei Hwang:
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC 2009: 375-378 - 2008
- [c31]Mu-Tien Chang, Wei Hwang:
A fully-differential subthreshold SRAM cell with auto-compensation. APCCAS 2008: 1771-1774 - [c30]Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang:
"Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325 - [c29]Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang:
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345 - [c28]Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang:
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83 - [c27]Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang:
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC 2008: 97-100 - [c26]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178 - [c25]Wei-Chih Hsieh, Wei Hwang:
In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC 2008: 215-218 - [c24]Hao-I Yang, Ssu-Yun Lai, Wei Hwang:
Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC 2008: 239-242 - 2007
- [c23]Ming-Hung Chang, Zong-Xi Yang, Wei Hwang:
A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS 2007: 1137-1140 - [c22]Wei-Chih Hsieh, Wei Hwang:
Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS 2007: 1637-1640 - [c21]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210 - [c20]Chang-Hsuan Chang, Ming-Hung Chang, Wei Hwang:
A flexible two-layer external memory management for H.264/AVC decoder. SoCC 2007: 219-222 - 2006
- [c19]Jen-Wei Yang, Po-Tsang Huang, Wei Hwang:
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669 - [c18]Po-Tsang Huang, Wei-Keng Chang, Wei Hwang:
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304 - [c17]Chi-Chen Lai, Wei Hwang:
A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS 2006: 1931-1934 - [c16]Tzu-Chiang Chao, Wei Hwang:
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS 2006 - [c15]Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang:
A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS 2006 - [c14]Po-Tsang Huang, Wei Hwang:
2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006 - 2005
- [c13]Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen:
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) 2005: 444-447 - [c12]Chung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang:
Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM. MTDT 2005: 129-134 - 2004
- [j8]Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang:
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. J. VLSI Signal Process. 38(2): 101-113 (2004) - 2003
- [j7]Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban:
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47(2-3): 283-298 (2003) - 2002
- [c11]Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang:
Multiplier architecture power consumption characterization for low-power DSP applications. ICECS 2002: 741-744 - 2001
- [c10]Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang:
SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42 - [c9]W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi:
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266 - [c8]Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann:
Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196- - 2000
- [j6]Wei Hwang, Rajiv V. Joshi, George Gristede:
A scannable pulse-to-static conversion register array for self-timed circuits. IEEE J. Solid State Circuits 35(1): 125-128 (2000) - [c7]George Gristede, Wei Hwang:
A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI 2000: 101-106 - [c6]Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang:
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206 - [c5]Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang:
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
1990 – 1999
- 1999
- [j5]Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. IEEE J. Solid State Circuits 34(1): 56-67 (1999) - [j4]Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel:
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. IEEE J. Solid State Circuits 34(8): 1108-1117 (1999) - [c4]Rajiv V. Joshi, Wei Hwang:
Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531 - 1998
- [c3]Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel:
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability. CICC 1998: 519-522 - 1997
- [j3]Fang-Shi Lai, Wei Hwang:
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems. IEEE J. Solid State Circuits 32(4): 563-573 (1997) - [c2]W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285 - [c1]Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717 - 1994
- [j2]Walter H. Henkels, Wei Hwang:
Large-signal 2T, 1C DRAM cell: signal and layout analysis. IEEE J. Solid State Circuits 29(7): 829-832 (1994)
1980 – 1989
- 1988
- [j1]Sang H. Dhong, Nicky Chau-Chun Lu, Wei Hwang, Stephen A. Parke:
High-speed sensing scheme for CMOS DRAMs. IEEE J. Solid State Circuits 23(1): 34-40 (1988)
Coauthor Index
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