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ORCIDValerio Tenace
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2020 – today
- 2024
[i2]Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace:
AIvril: AI-Driven RTL Generation With Verification In-The-Loop. CoRR abs/2409.11411 (2024)- 2021
- [c16]Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon:
NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. ASAP 2021: 57-60 - [c15]Shubham Rai
, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - 2020
- [j6]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 397-410 (2020) - [i1]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [j5]Matteo Grimaldi, Valerio Tenace, Andrea Calimera:
Layer-Wise Compressive Training for Convolutional Neural Networks. Future Internet 11(1): 7 (2019) - [c14]Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera:
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. DATE 2019: 372-377 - [c13]Luca Mocerino, Valerio Tenace, Andrea Calimera:
Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. DATE 2019: 848-853 - 2018
- [j4]Valerio Tenace, Andrea Calimera:
Quasi-exact logic functions through classification trees. Integr. 63: 248-255 (2018) - [c12]Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera:
A compression-driven training framework for embedded deep neural networks. INTESA@ESWEEK 2018: 45-50 - [c11]Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera:
Multiplication by Inference using Classification Trees: A Case-Study Analysis. ISCAS 2018: 1-5 - [c10]Valerio Tenace, Andrea Calimera:
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. VLSI-SoC 2018: 149-154 - 2017
- [c9]Valerio Tenace, Andrea Calimera:
Activation-Kernel Extraction through Machine Learning. NGCAS 2017: 5-8 - 2016
- [b1]Valerio Tenace:
CAD Tools for Graphene-Based Electronic Circuits. Polytechnic University of Turin, Italy, 2016 - [j3]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1111-1115 (2016) - [c8]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI 2016: 145-150 - [c7]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS 2016: 2897 - [c6]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC 2016: 1-6 - [c5]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) 2016: 60-82 - 2015
- [j2]Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems 39(8): 962-972 (2015) - [c4]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC 2015: 128:1-128:6 - [c3]Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI 2015: 39-44 - 2014
- [j1]Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45(5): 530-538 (2014) - [c2]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE 2014: 1-4 - 2012
- [c1]Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI 2012: 279-282
Coauthor Index
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