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ORCIDWalter Lau Neto
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2020 – today
- 2024
[c12]Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù:
Scalable Sequential Optimization Under Observability Don't Cares. DATE 2024: 1-6- 2023
- [j3]Walter Lau Neto
, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu:
FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1912-1925 (2023) - [i4]Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù:
Scalable Sequential Optimization Under Observability Don't Cares. CoRR abs/2311.09967 (2023) - 2022
- [j2]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5126-5130 (2022) - [c11]Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon:
Improving LUT-based optimization for ASICs. DAC 2022: 421-426 - [i3]Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu:
End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit. CoRR abs/2202.07721 (2022) - 2021
- [c10]Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC 2021: 530-535 - [c9]Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC 2021: 859-864 - [c8]Scott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon:
Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. DAC 2021: 1331-1334 - [c7]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [i2]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR abs/2112.00621 (2021) - 2020
- [j1]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020) - [c6]Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable Mixed Synthesis Framework for Heterogeneous Networks. DATE 2020: 670-673 - [i1]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [c5]Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon:
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. ICCAD 2019: 1-6 - [c4]Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon:
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI 2019: 224-229 - 2018
- [c3]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI 2018: 1-6 - 2017
- [c2]Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
Sleep convention logic isochronic fork: an analysis. SBCCI 2017: 103-109 - 2016
- [c1]Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
A standard cell characterization flow for non-standard voltage supplies. SBCCI 2016: 1-6
Coauthor Index
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