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ORCIDMitsumasa Koyanagi
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2020 – today
- 2023
[c61]Mariappan Murugesan, M. Sawa, E. Sone, Makoto Motoyoshi, Mitsumasa Koyanagi, Takafumi Fukushima
:
Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding. 3DIC 2023: 1-4- [c60]Jiayi Shen, Chang Liu, Tadaaki Hoshi, Atsushi Sinoda, Hisashi Kino, Tetsu Tanaka, Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima:
Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last. 3DIC 2023: 1-4 - 2021
- [c59]Takafumi Fukushima, Shinichi Sakuyama, Masatomo Takahashi, Hiroyuki Hashimoto, Jichoel Bea, Theodorus Marcello, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi, Mariappan Murugesan:
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. 3DIC 2021: 1-4 - [c58]Yoshihiko Horio, Takemori Orima, Koji Kiyoyama, Mitsumasa Koyanagi:
Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. 3DIC 2021: 1-4 - [c57]Koji Kiyoyama, Yoshihiko Horio, Takafumi Fukushima, Hiroyuki Hashimoto, Takemori Orima, Mitsumasa Koyanagi:
Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. 3DIC 2021: 1-4 - [c56]Mariappan Murugesan, E. Sone, A. Simomura, Makoto Motoyoshi, M. Sawa, K. Fukuda, Mitsumasa Koyanagi, Takafumi Fukushima:
Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications. 3DIC 2021: 1-4 - 2020
- [c55]Mitsumasa Koyanagi:
3D Heterogeneous Integration Technology for AI System. VLSI-DAT 2020: 1
2010 – 2019
- 2019
- [c54]Shunji Kurooka, Yoshinori Hotta, Ai Nakamura, Mitsumasa Koyanagi, Takafumi Fukushima:
Cu-Cu Bonding Challenges with 'i-ACF' for Advanced 3D Integration. 3DIC 2019: 1-4 - [c53]Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima:
Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI. 3DIC 2019: 1-5 - [c52]Mariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima:
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. 3DIC 2019: 1-4 - 2016
- [j5]Takafumi Fukushima, Hideto Hashiguchi, Hiroshi Yonekura, Hisashi Kino, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. Micromachines 7(10): 184 (2016) - [c51]Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
New concept of TSV formation methodology using Directed Self-Assembly (DSA). 3DIC 2016: 1-4 - [c50]Kang Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi:
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. 3DIC 2016: 1-5 - [c49]Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi:
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. 3DIC 2016: 1-4 - [c48]Mariappan Murugesan, Jichel Bea, Takafumi Fukushima, Makoto Motoyoshi, Tetsu Tanaka, Mitsumasa Koyanagi:
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. 3DIC 2016: 1-4 - 2015
- [j4]Mitsumasa Koyanagi:
Recent progress in 3D integration technology. IEICE Electron. Express 12(7): 20152001 (2015) - [c47]K. W. Lee, Chisato Nagai, Ai Nakamura, Hiroki Aizawa, Ji Chel Bea, Mitsumasa Koyanagi, Hideto Hashiguchi, Takafumi Fukushima, Tanaka Tanaka:
Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers. 3DIC 2015: TS1.2.1-TS1.2.4 - [c46]Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka:
Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors. 3DIC 2015: TS3.1.1-TS3.1.4 - [c45]Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi:
Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. 3DIC 2015: TS5.2.1-TS5.2.5 - [c44]Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi:
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. 3DIC 2015: TS7.4.1-TS7.4.4 - [c43]Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka:
Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC. 3DIC 2015: TS8.26.1-TS8.26.4 - [c42]Kang Wook Lee, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. IRPS 2015: 4 - 2014
- [c41]Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi:
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. 3DIC 2014: 1-4 - [c40]K. W. Lee, Chisato Nagai, Ai Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tanaka Tanaka, Mitsumasa Koyanagi:
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. 3DIC 2014: 1-4 - 2013
- [c39]Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Mitsumasa Koyanagi:
Development of via-last 3D integration technologies using a new temporary adhesive system. 3DIC 2013: 1-4 - [c38]Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Ho-Young Son, M.-S. Suh, K.-Y. Byun, N.-S. Kim, Kang Wook Lee, Mitsumasa Koyanagi:
3D memory chip stacking by multi-layer self-assembly technology. 3DIC 2013: 1-4 - [c37]Hiroyuki Hashimoto, Takafumi Fukushima, Kang Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka:
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. 3DIC 2013: 1-5 - [c36]Kouji Kiyoyama, Y. Sato, Hiroyuki Hashimoto, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. 3DIC 2013: 1-4 - [c35]Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 3DIC 2013: 1-4 - [c34]Mariappan Murugesan, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi, Yuji Sutou, H. Wang, J. Koike:
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. 3DIC 2013: 1-4 - 2012
- [c33]Noboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Kazuko Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Makoto Miakashi, Naoki Kobayashi, M. Inagaki, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, Masaki Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, Masahiro Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, Shingo Zaitsu, Hiroaki Nasu, Takuya Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, Kousuke Kanazawa:
A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. ISSCC 2012: 422-424 - [e1]Mitsumasa Koyanagi, Morihiro Kada:
2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012. IEEE 2012, ISBN 978-1-4673-2189-1 [contents] - 2011
- [j3]Takafumi Fukushima, Takayuki Konno, Eiji Iwata, Risato Kobayashi, Toshiya Kojima, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. Micromachines 2(1): 49-68 (2011) - [c32]Takafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Temporary bonding strength control for self-assembly-based 3D integration. 3DIC 2011: 1-4 - [c31]Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi:
Chip-level TSV integration for rapid prototyping of 3D system LSIs. 3DIC 2011: 1-4 - [c30]Yuka Ito, Shinsuke Terada, Shinya Arai, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi:
High-bandwidth data transmission of new transceiver module through optical interconnection. 3DIC 2011: 1-4 - [c29]Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, H. Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi:
A very low area ADC for 3-D stacked CMOS image processing system. 3DIC 2011: 1-4 - [c28]Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Yuki Ohara, Tetsu Tanaka, Mitsumasa Koyanagi:
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. 3DIC 2011: 1-4 - [c27]Makoto Motoyoshi, Junichi Takanohashi, Takafumi Fukushima, Yasuo Arai, Mitsumasa Koyanagi:
Stacked SOI pixel detector using versatile fine pitch μ-bump technology. 3DIC 2011: 1-4 - [c26]Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress. 3DIC 2011: 1-4 - [c25]Mariappan Murugesan, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
High density Cu-TSVs and reliability issues. 3DIC 2011: 1-4 - [c24]Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. 3DIC 2011: 1-4 - [c23]Yuki Ohara, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. 3DIC 2011: 1-4 - [c22]Mitsumasa Koyanagi:
3D super chip technology to achieve low-power and high-performance system-on-a chip. ISLPED 2011: 61-62 - 2010
- [c21]Takafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC 2010: 1-5 - [c20]Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, Hiroaki Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi:
A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. 3DIC 2010: 1-4 - [c19]Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 3DIC 2010: 1-5 - [c18]Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. 3DIC 2010: 1-4 - [c17]Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. CICC 2010: 1-4
2000 – 2009
- 2009
- [j2]Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
High-Density Through Silicon Vias for 3-D LSIs. Proc. IEEE 97(1): 49-59 (2009) - [c16]Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisashi Kino, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 3DIC 2009: 1-5 - [c15]Takafumi Fukushima, Eiji Iwata, Tetsu Tanaka, Mitsumasa Koyanagi:
Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. 3DIC 2009: 1-4 - [c14]Yoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
3D integration technology for 3D stacked retinal chip. 3DIC 2009: 1-4 - [c13]Kouji Kiyoyama, Yuki Ohara, Kang Wook Lee, Y. Yang, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
A parallel ADC for high-speed CMOS image processing system with 3D structure. 3DIC 2009: 1-4 - [c12]Kang Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Heterogeneous integration technology for MEMS-LSI multi-chip module. 3DIC 2009: 1-6 - [c11]Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC 2009: 1-6 - [c10]Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
Three-dimensional integration technology and integrated systems. ASP-DAC 2009: 409-415 - 2006
- [c9]Atsushi Konno, Ryo Uchikura, Toshiyuki Ishihara, Teppei Tsujita, Takeaki Sugimura, Jun Deguchi, Mitsumasa Koyanagi, Masaru Uchiyama:
Development of a High Speed Vision System for Mobile Robots. IROS 2006: 1372-1377 - 2005
- [c8]Takeaki Sugimura, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Hiroyuki Kurino, Mitsumasa Koyanagi:
Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. ARCS Workshops 2005: 27-32 - 2004
- [c7]Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi:
Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. AINA (2) 2004: 241-244 - [c6]Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi:
Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. PDCAT 2004: 564-569 - 2003
- [c5]Takeaki Sugimura, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi:
Parallel image processing field programmable gate array for real time image processing system. FPT 2003: 372-374 - 2002
- [c4]Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi:
Nanometer design: what hurts next...? DAC 2002: 242 - 2000
- [c3]Hiroyuki Kurino, Masaki Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi:
Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. NIPS 2000: 720-726
1990 – 1999
- 1998
- [j1]Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani:
Future system-on-silicon LSI chips. IEEE Micro 18(4): 17-22 (1998) - [c2]Keiichi Hirano, Taizou Ono, Hiroyuki Kurino, Mitsumasa Koyanagi:
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. ASP-DAC 1998: 333-334 - 1991
- [c1]Mitsumasa Koyanagi:
A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. VLSI 1991: 377-386
Coauthor Index
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