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2020 – today
- 2024
[c11]Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra:
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. ETS 2024: 1-10- [c10]Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli
, Erik Jan Marinissen:
Test and Repair Improvements for UCIe. ETS 2024: 1-6 - [c9]Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim:
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. VTS 2024: 1-11 - 2023
- [c8]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6 - [c7]Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen:
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. ITC-Asia 2023: 1-6 - [c6]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - 2022
- [c5]Hong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu:
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime. VLSI-DAT 2022: 1-4 - 2020
- [c4]Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. DAC 2020: 1-6 - [i1]Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu:
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. CoRR abs/2003.06310 (2020)
2010 – 2019
- 2018
- [c3]Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen:
Covering hard-to-detect defects by thermal quorum sensing. ETS 2018: 1-2 - 2017
- [c2]Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen:
Cell-aware test generation time reduction by using switch-level ATPG. ITC-Asia 2017: 27-32 - 2016
- [c1]Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu:
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. ATS 2016: 197-202
Coauthor Index
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