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ORCIDXavier Vera
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2020 – today
- 2020
[c39]Xavier Vera:
Inside Tiger Lake: Intel's Next Generation Mobile Client CPU. Hot Chips Symposium 2020: 1-26
2010 – 2019
- 2016
- [j15]Gaurang Upasani, Xavier Vera, Antonio González
:
A Case for Acoustic Wave Detectors for Soft-Errors. IEEE Trans. Computers 65(1): 5-18 (2016) - 2014
- [c38]Gaurang Upasani, Xavier Vera, Antonio González:
Framework for economical error recovery in embedded cores. IOLTS 2014: 146-153 - [c37]Gaurang Upasani, Xavier Vera, Antonio González:
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. ISCA 2014: 37-48 - 2013
- [c36]Javier Carretero, Enric Herrero, Matteo Monchiero, Tanausú Ramírez, Xavier Vera:
Capturing vulnerability variations for register files. DATE 2013: 1468-1473 - [c35]Gaurang Upasani, Xavier Vera, Antonio González:
Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. IOLTS 2013: 85-91 - [c34]Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González:
Deconfigurable microprocessor architectures for silicon debug acceleration. ISCA 2013: 631-642 - 2012
- [c33]Gaurang Upasani, Xavier Vera, Antonio González:
Setting an error detection infrastructure with low cost acoustic wave detectors. ISCA 2012: 333-343 - 2011
- [j14]Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González:
Implementing End-to-End Register Data-Flow Continuous Self-Test. IEEE Trans. Computers 60(8): 1194-1206 (2011) - [c32]Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera:
Architectures for online error detection and recovery in multicore processors. DATE 2011: 533-538 - [c31]Javier Carretero, Jaume Abella, Xavier Vera, Pedro Chaparro:
Control-Flow Recovery Validation Using Microarchitectural Invariants. DFT 2011: 209-216 - [c30]Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González:
Hardware/software-based diagnosis of load-store queues using expandable activity logs. HPCA 2011: 321-331 - [c29]Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber:
New reliability mechanisms in memory design for sub-22nm technologies. IOLTS 2011: 111-114 - [c28]Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González:
Accelerating microprocessor silicon validation by exposing ISA diversity. MICRO 2011: 386-397 - [c27]Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
Design of complex circuits using the Via-Configurable transistor array regular layout fabric. SoCC 2011: 166-169 - [c26]Ramon Canal, Antonio Rubio, A. Asenov, A. Brown, Miguel Miranda, Paul Zuber, Antonio González, Xavier Vera:
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. FET 2011: 148-149 - 2010
- [j13]Jaume Abella, Xavier Vera:
Electromigration for microarchitects. ACM Comput. Surv. 42(2): 9:1-9:18 (2010) - [j12]Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella:
Microarchitectural Online Testing for Failure Detection in Memory Order Buffers. IEEE Trans. Computers 59(5): 623-637 (2010) - [c25]Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera:
The split register file. DATE 2010: 945-948 - [c24]Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González:
High-Performance low-vcc in-order core. HPCA 2010: 1-11 - [c23]Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González:
MT-SBST: Self-test optimization in multithreaded multicore architectures. ITC 2010: 734-743 - [c22]Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
VCTA: A Via-Configurable Transistor Array regular fabric. VLSI-SoC 2010: 335-340
2000 – 2009
- 2009
- [j11]Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González:
Reducing Soft Errors through Operand Width Aware Policies. IEEE Trans. Dependable Secur. Comput. 6(3): 217-230 (2009) - [j10]Xavier Vera, Jaume Abella, Javier Carretero, Antonio González:
Selective replication: A lightweight technique for soft errors. ACM Trans. Comput. Syst. 27(4): 8:1-8:30 (2009) - [c21]Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González:
Online error detection and correction of erratic bits in register files. IOLTS 2009: 81-86 - [c20]Xavier Vera:
DFx for massively multiprocessors. IOLTS 2009: 153 - [c19]Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González:
End-to-end register data-flow continuous self-test. ISCA 2009: 105-115 - [c18]Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González:
Low Vccmin fault-tolerant cache with highly predictable performance. MICRO 2009: 111-121 - 2008
- [j9]Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz:
Refueling: Preventing Wire Degradation due to Electromigration. IEEE Micro 28(6): 37-46 (2008) - [c17]Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera:
Issue system protection mechanisms. ICCD 2008: 599-604 - [c16]Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González:
On-Line Failure Detection and Confinement in Caches. IOLTS 2008: 3-9 - [c15]Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella:
On-line Failure Detection in Memory Order Buffers. ITC 2008: 1-10 - 2007
- [j8]Xavier Vera, Björn Lisper, Jingling Xue:
Data cache locking for tight timing calculations. ACM Trans. Embed. Comput. Syst. 7(1): 4:1-4:38 (2007) - [c14]Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González:
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. IOLTS 2007: 15-22 - [c13]Xavier Vera, Jaume Abella:
Surviving to Errors in Multi-Core Environments. IOLTS 2007: 260 - [c12]Jaume Abella, Xavier Vera, Antonio González:
Penelope: The NBTI-Aware Processor. MICRO 2007: 85-96 - 2006
- [j7]Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González:
Exploiting Narrow Values for Soft Error Tolerance. IEEE Comput. Archit. Lett. 5(2) (2006) - [j6]Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin:
Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26(6): 30-39 (2006) - [c11]Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González:
Empowering a helper cluster through data-width aware instruction selection policies. IPDPS 2006 - 2005
- [j5]Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle:
IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans. Archit. Code Optim. 2(1): 55-77 (2005) - [j4]Xavier Vera, Jaume Abella, Josep Llosa, Antonio González:
An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. 27(5): 946-987 (2005) - [c10]Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González:
Variable-Based Multi-module Data Caches for Clustered VLIW Processors. IEEE PACT 2005: 207-217 - 2004
- [j3]Jingling Xue, Xavier Vera:
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. IEEE Trans. Computers 53(5): 547-566 (2004) - [j2]Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González:
A fast and accurate framework to analyze and optimize cache memory behavior. ACM Trans. Program. Lang. Syst. 26(2): 263-300 (2004) - 2003
- [c9]Xavier Vera, Jaume Abella, Antonio González, Josep Llosa:
Optimizing Program Locality Through CMEs and GAs. IEEE PACT 2003: 68-78 - [c8]Qingguang Huang, Jingling Xue, Xavier Vera:
Code Tiling for Improving the Cache Performance of PDE Solvers. ICPP 2003: 615- - [c7]Xavier Vera, Björn Lisper, Jingling Xue:
Data Caches in Multitasking Hard Real-Time Systems. RTSS 2003: 154-165 - [c6]Xavier Vera, Björn Lisper, Jingling Xue:
Data cache locking for higher program predictability. SIGMETRICS 2003: 272-282 - 2002
- [c5]Xavier Vera, Jingling Xue:
Let's Study Whole-Program Cache Behaviour Analytically. HPCA 2002: 175-186 - [c4]Jaume Abella, Antonio González, Josep Llosa, Xavier Vera:
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops 2002: 568-580 - [c3]Xavier Vera, Josep Llosa, Antonio González:
Near-Optimal Padding for Removing Conflict Misses. LCPC 2002: 329-343 - 2000
- [j1]Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa:
Optimizing cache miss equations polyhedra. SIGARCH Comput. Archit. News 28(1): 43-52 (2000) - [c2]Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo:
A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). Euro-Par 2000: 194-198 - [c1]Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa:
An efficient solver for Cache Miss Equations. ISPASS 2000: 139-145
Coauthor Index
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