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ORCIDCarl Pixley
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2000 – 2009
- 2009
[c35]Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley:
Solver technology for system-level to RTL equivalence checking. DATE 2009: 196-201- 2008
- [c34]Carl Pixley:
Practical Considerations Concerning HL-to -RT Equivalence Checking. Haifa Verification Conference 2008: 6 - 2007
- [c33]Alfred Kölbl, Jerry R. Burch, Carl Pixley:
Memory Modeling in ESL-RTL Equivalence Checking. DAC 2007: 205-209 - [c32]In-Ho Moon, Per Bjesse, Carl Pixley:
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. DATE 2007: 1170-1175 - 2006
- [b1]Jun Yuan, Carl Pixley, Adnan Aziz:
Constraint-based verification. Springer 2006, ISBN 978-0-387-25947-5, pp. I-XII, 1-253 - [j15]Sandeep K. Shukla, Carl Pixley, Gary Smith:
Guest Editors' Introduction: The True State of the Art of ESL Design. IEEE Des. Test Comput. 23(5): 335-337 (2006) - [c31]In-Ho Moon, Per Bjesse, Carl Pixley:
Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. HLDVT 2006: 170-175 - [c30]Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley:
Panel: Assertion-Based Verification -What's the Big Deal? HLDVT 2006: 183 - 2005
- [j14]Alfred Kölbl, Carl Pixley:
Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation. Int. J. Parallel Program. 33(6): 645-666 (2005) - 2004
- [j13]Carl Pixley, Sharad Malik
:
Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Des. Test Comput. 21(6): 461-463 (2004) - [j12]Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin:
Simplifying Boolean constraint solving for random simulation-vector generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 412-420 (2004) - [c29]In-Ho Moon, Carl Pixley:
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. FMCAD 2004: 144-158 - [c28]Carl Pixley, D. Meyers, S. McMaster, A. Chittor:
Designers want proofs - but show me the money. MEMOCODE 2004: 153-154 - 2003
- [j11]Carl Pixley, Juan Antonio Carballo:
Panel Summaries. IEEE Des. Test Comput. 20(4): 86-88 (2003) - [j10]Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton:
Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) - [c27]Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Constraint synthesis for environment modeling in functional verification. DAC 2003: 296-299 - [c26]Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi:
Formal verification - prove it or pitch it. DAC 2003: 710-711 - [c25]Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin:
A Framework for Constrained Functional Verification. ICCAD 2003: 142-145 - 2002
- [c24]In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley:
Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD 2002: 52-69 - [c23]Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Boolean constraint solving for random simulation-vector generation. ICCAD 2002: 123-127 - [c22]Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Constraint Solving in Random Simulation Generation. IWLS 2002: 185-190 - 2001
- [j9]Carl Pixley:
Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. IEEE Des. Test Comput. 18(4): 4-5 (2001) - [j8]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 249-265 (2001) - [c21]Shuvendu K. Lahiri, Carl Pixley, Ken Albin:
Experience with term level modeling and verification of the M*CORE TM microprocessor core. HLDVT 2001: 109-114 - [c20]Noel R. Strader, Gérard Memmi, Carl Pixley:
Application of Formal Verification to Design Creation and Implementation. ISQED 2001: 11 - 2000
- [j7]Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho:
An Efficient Logic Equivalence Checker for Industrial Circuits. J. Electron. Test. 16(1-2): 91-106 (2000) - [j6]Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Automatic Vector Generation Using Constraints and Biasing. J. Electron. Test. 16(1-2): 107-120 (2000)
1990 – 1999
- 1999
- [j5]Carl Pixley, Vigyan Singhal:
Model Checking: A Hardware Design Perspective. Int. J. Softw. Tools Technol. Transf. 2(3): 288-306 (1999) - [c19]Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Modeling design constraints and biasing in simulation using BDDs. ICCAD 1999: 584-590 - [c18]Carl Pixley, Kurt Shultz, Jun Yuan:
Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. PDPTA 1999: 1061-1068 - 1998
- [c17]Jainendra Kumar, Carl Pixley:
Logic and Functional Verification in a Commercial Semiconductor Environment. ACSD 1998: 8-15 - [c16]Matt Kaufmann, Andrew Martin, Carl Pixley:
Design Constraints in Symbolic Model Checking. CAV 1998: 477-487 - [c15]In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley:
Approximate reachability don't cares for CTL model checking. ICCAD 1998: 351-358 - 1997
- [c14]Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley:
Formal Verification of FIRE: A Case Study. DAC 1997: 173-177 - [c13]Matt Kaufmann, Carl Pixley:
Intertwined Development and Formal Verification of a 60x Bus Model. ICCD 1997: 25-30 - 1996
- [c12]Carl Pixley, Noel R. Strader, William C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen:
Commercial Design Verification: Methodology and Tools. ITC 1996: 839-848 - 1995
- [c11]Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton:
The Validity of Retiming Sequential Circuits. DAC 1995: 316-321 - [c10]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Exploiting power-up delay for sequential optimization. EURO-DAC 1995: 54-59 - [c9]Vigyan Singhal, Robert K. Brayton, Carl Pixley:
Power-Up Delay for Retiming Digital Circuits. ISCAS 1995: 566-569 - 1994
- [j4]Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 1024-1034 (1994) - [c8]Vigyan Singhal, Carl Pixley:
The Verifiacation Problem for Safe Replaceability. CAV 1994: 311-323 - [c7]Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton:
Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449 - 1993
- [j3]Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley:
Synchronizing sequences and symbolic traversal techniques in test generation. J. Electron. Test. 4(1): 19-31 (1993) - [c6]June-Kyung Rho, Fabio Somenzi, Carl Pixley:
Minimum Length Synchronizing Sequences of Finite State Machine. DAC 1993: 463-468 - 1992
- [j2]Carl Pixley:
A theory and implementation of sequential hardware equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(12): 1469-1478 (1992) - [c5]Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC 1992: 620-623 - 1991
- [c4]Carl Pixley, Gary Beihl:
Calculating Resetability and Reset Sequences. ICCAD 1991: 376-379 - [c3]Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes:
Automatic Derivation of FSM Specification to Implementation Encoding. ICCD 1991: 245-249 - 1990
- [c2]Carl Pixley:
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. CAV 1990: 54-64 - [c1]Carl Pixley:
A Computation Theory and Implementation of Sequential Hardware Equivalence. CAV (DIMACS/AMS volume) 1990: 293-320
1980 – 1989
- 1988
- [j1]Carl Pixley:
An Incremental Garbage Collection Algorithm for Multi-Mutator Systems. Distributed Comput. 3(1): 41-50 (1988)
Coauthor Index
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