default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDYoun-Long Lin
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[c62]Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao:
NeighborTrack: Single Object Tracking by Bipartite Matching with Neighbor Tracklets and Its Applications to Sports. CVPR Workshops 2023: 5139-5148- 2022
- [c61]Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang:
SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. BMVC 2022: 55 - [c60]Ting-Yu Liao
, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin:
HarDNet-DFUS: Enhancing Backbone and Decoder of HarDNet-MSEG for Diabetic Foot Ulcer Image Segmentation. DFUC@MICCAI 2022: 21-30 - [i7]Ting-Yu Liao, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin:
HarDNet-DFUS: An Enhanced Harmonically-Connected Network for Diabetic Foot Ulcer Image Segmentation and Colonoscopy Polyp Segmentation. CoRR abs/2209.07313 (2022) - [i6]Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang:
SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. CoRR abs/2210.16572 (2022) - [i5]Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao:
NeighborTrack: Improving Single Object Tracking by Bipartite Matching with Neighbor Tracklets. CoRR abs/2211.06663 (2022) - 2021
- [c59]Hung-Yu Wu, Youn-Long Lin:
HarDNet-BTS: A Harmonic Shortcut Network for Brain Tumor Segmentation. BrainLes@MICCAI (1) 2021: 261-271 - [c58]Chien-Yao Wang, Hong-Yuan Mark Liao, I-Hau Yeh, Yung-Yu Chuang, Youn-Long Lin:
Exploring the power of lightweight YOLOv4. ICCVW 2021: 779-788 - [i4]Chien-Hsiang Huang, Hung-Yu Wu, Youn-Long Lin:
HarDNet-MSEG: A Simple Encoder-Decoder Polyp Segmentation Neural Network that Achieves over 0.9 Mean Dice and 86 FPS. CoRR abs/2101.07172 (2021) - 2020
- [i3]Chao-Yang Kao, Huang-Chih Kuo, Jian-Wen Chen, Chiung-Liang Lin, Pin-Han Chen, Youn-Long Lin:
RNNAccel: A Fusion Recurrent Neural Network Accelerator for Edge Intelligence. CoRR abs/2010.13311 (2020)
2010 – 2019
- 2019
- [c57]Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin:
HarDNet: A Low Memory Traffic Network. ICCV 2019: 3551-3560 - [i2]Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin:
HarDNet: A Low Memory Traffic Network. CoRR abs/1909.00948 (2019) - 2013
- [j37]Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang:
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access 1: 123-130 (2013) - [j36]Huang-Chih Kuo, Youn-Long Lin:
VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding. IPSJ Trans. Syst. LSI Des. Methodol. 6: 76-93 (2013) - [j35]Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao:
Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 413-423 (2013) - 2012
- [j34]Huang-Chih Kuo, Youn-Long Lin:
A Hybrid Algorithm for Effective Lossless Compression of Video Display Frames. IEEE Trans. Multim. 14(3-1): 500-509 (2012) - 2011
- [j33]Chia-Ming Hung, Youn-Long Lin:
Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse. IET Comput. Digit. Tech. 5(3): 179-185 (2011) - [j32]Huang-Chih Kuo, Li-Cian Wu, Hao-Ting Huang, Sheng-Tsung Hsu, Youn-Long Lin:
A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 925-938 (2011) - [c56]Huang-Chih Kuo, Youn-Long Lin:
A simple and effective lossless compression algorithm for video display frames. ICME 2011: 1-6 - 2010
- [j31]Jian-Wen Chen, Li-Cian Wu, Po-Sheng Liu, Youn-Long Lin:
A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video. IEEE Trans. Consumer Electron. 56(4): 2529-2536 (2010) - [j30]Huan-Kai Peng, Youn-Long Lin:
An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration. ACM Trans. Embed. Comput. Syst. 9(4): 35:1-35:39 (2010) - [j29]Chao-Yang Kao, Cheng-Long Wu, Youn-Long Lin:
A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 662-666 (2010) - [j28]Chao-Yang Kao, Youn-Long Lin:
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 866-874 (2010) - [c55]Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC 2010: 1-6 - [c54]Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC 2010: 1-4 - [c53]Ping Chao, Youn-Long Lin:
An elastic software cache with fast prefetching for motion compensation in video decoding. CODES+ISSS 2010: 23-32
2000 – 2009
- 2009
- [j27]Jian-Wen Chen, Youn-Long Lin:
A high-performance hardwired CABAC decoder for ultra-high resolution video. IEEE Trans. Consumer Electron. 55(3): 1614-1622 (2009) - [j26]Yuan-Chun Lin, Youn-Long Lin:
A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 838-843 (2009) - [c52]Huang-Chih Kuo, Jian-Wen Chen, Youn-Long Lin:
A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. ESTIMedia 2009: 1-8 - [c51]Hui-Ting Yang, Jian-Wen Chen, Huang-Chih Kuo, Youn-Long Lin:
An effective dictionary-based display frame compressor. ESTIMedia 2009: 28-34 - [c50]Li-Cian Wu, Youn-Long Lin:
A High throughput CABAC Encoder for Ultra High Resolution Video. ISCAS 2009: 1048-1051 - 2008
- [c49]Cheng-Long Wu, Chao-Yang Kao, Youn-Long Lin:
A high performance three-engine architecture for H.264/AVC fractional motion estimation. ICME 2008: 133-136 - [c48]Chao-Yang Kao, Youn-Long Lin:
A high-performance and memory-efficient architecture for H.264/AVC motion estimation. ICME 2008: 141-144 - [c47]Huang-Chih Kuo, Youn-Long Lin:
An H.264/AVC full-mode intra-frame encoder for 1080HD video. ICME 2008: 1037-1040 - [c46]Ping Chao, Youn-Long Lin:
Reference frame access optimization for ultra high resolution H.264/AVC decoding. ICME 2008: 1441-1444 - [c45]Ping Chao, Youn-Long Lin:
A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. ISCAS 2008: 256-259 - 2007
- [c44]Jian-Wen Chen, Youn-Long Lin:
A High-Performance Hardwired CABAC Decoder. ICASSP (2) 2007: 37-40 - [i1]Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC. CoRR abs/0710.4667 (2007) - 2006
- [c43]Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin:
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. APCCAS 2006: 562-565 - [c42]Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin:
A near optimal deblocking filter for H.264 advanced video coding. ASP-DAC 2006: 170-175 - [c41]Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin:
Introduction to H.264 advanced video coding. ASP-DAC 2006: 736-741 - [c40]Chao-Yang Kao, Huang-Chih Kuo, Youn-Long Lin:
High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. ICME 2006: 1241-1244 - 2005
- [j25]Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin:
A platform based SOC design methodology and its application in image compression. Int. J. Embed. Syst. 1(1/2): 23-32 (2005) - [c39]Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC. DATE 2005: 1116-1117 - [c38]Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin:
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. ISCAS (5) 2005: 4525-4528 - [c37]Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin:
An AMBA-compliant deblocking filter IP for H.264/AVC. ISCAS (5) 2005: 4529-4532 - 2004
- [c36]Tien-Wei Hsieh, Youn-Long Lin:
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. ESTIMedia 2004: 87-90 - 2002
- [j24]Yih-Chih Chou, Youn-Long Lin:
Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 15-22 (2002) - [c35]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356- - [c34]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411- - 2001
- [c33]Yih-Chih Chou, Youn-Long Lin:
A 3-step approach for performance-driven whole-chip routing. ASP-DAC 2001: 187-191 - [c32]Yih-Chih Chou, Youn-Long Lin:
A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD 2001: 24-29 - [c31]Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin:
Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. ISSS 2001: 233-238 - 2000
- [c30]Michael C.-J. Lin, Youn-Long Lin:
A VLSI implementation of the blowfish encryption/decryption algorithm. ASP-DAC 2000: 1-2 - [c29]Tzu-Chieh Tien, Youn-Long Lin:
Performance-optimal clustering with retiming for sequential circuits. ASP-DAC 2000: 409-414 - [c28]Hong-Kai Chang, Youn-Long Lin:
Array allocation taking into account SDRAM characteristics. ASP-DAC 2000: 497-502
1990 – 1999
- 1999
- [j23]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 475-483 (1999) - [j22]Wei-Kai Cheng, Youn-Long Lin:
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. 4(3): 231-256 (1999) - [c27]Yun-Yin Lian, Youn-Long Lin:
Layout-based Logic Decomposition for Timing Optimization. ASP-DAC 1999: 229-232 - [c26]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC 1999: 262-267 - 1998
- [c25]Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin:
Integrating logic retiming and register placement. ICCAD 1998: 136-139 - [c24]Yih-Chih Chou, Youn-Long Lin:
A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD 1998: 426-429 - [c23]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD 1998: 12-17 - [c22]Wei-Kai Cheng, Youn-Long Lin:
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS 1998: 15-22 - 1997
- [j21]Hsiao-Pin Su, Youn-Long Lin:
A phase assignment method for virtual-wire-based hardware emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 776-783 (1997) - [j20]Youn-Long Lin:
Recent developments in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 2(1): 2-21 (1997) - [c21]Youn-Long Lin:
Computing brokerage and its application in VLSI design. ASP-DAC 1997: 65-69 - [c20]Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin:
Preserving HDL synthesis hierarchy for cell placement. ISPD 1997: 169-174 - 1996
- [j19]Tsung-Yi Wu, Youn-Long Lin:
Register minimization beyond sharing among variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1583-1587 (1996) - [c19]Youn-Long Lin, Tsung-Yi Wu:
Storage optimization by replacing some flip-flops with latches. EURO-DAC 1996: 296-301 - 1995
- [j18]Allen C.-H. Wu, Youn-Long Lin:
High-Level Synthesis -A Tutorial. IEICE Trans. Inf. Syst. 78-D(3): 209-218 (1995) - [j17]Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin:
TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 371-374 (1995) - [j16]Yu-Wen Tsay, Youn-Long Lin:
A row-based cell placement method that utilizes circuit structural properties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 393-397 (1995) - [j15]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995) - [c18]Wei-Kai Cheng, Youn-Long Lin:
A Transformation-Based Approach for Storage Optimization. DAC 1995: 158-163 - [c17]Tsung-Yi Wu, Youn-Long Lin:
Register Minimization beyond Sharing among Variables. DAC 1995: 164-169 - 1994
- [j14]Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 137-149 (1994) - [j13]Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski:
A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 439-450 (1994) - [c16]Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin:
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281 - [c15]Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
State Assignment for Power and Area Minimization. ICCD 1994: 250-254 - [c14]Wei-Kai Cheng, Youn-Long Lin:
Code generation for a DSP processor. HLSS 1994: 82-87 - 1993
- [j12]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 410-424 (1993) - [j11]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
PLS: a scheduler for pipeline synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1279-1286 (1993) - [c13]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127 - 1992
- [j10]Yirng-An Chen, Youn-Long Lin, Long-Wen Chang:
A Systolic Algorithm for the k-Nearest Neighbors Problem. IEEE Trans. Computers 41(1): 103-108 (1992) - [c12]Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin:
An effective methodology for functional pipelining. ICCAD 1992: 230-233 - 1991
- [j9]Ta-Yung Liu, Youn-Long Lin:
FLORA: A data path allocator based on branch-and-bound search. Integr. 11(1): 43-66 (1991) - [j8]Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao:
Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991) - [j7]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 994-1005 (1991) - [j6]Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin:
Channel density reduction by routing over the cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1067-1071 (1991) - [c11]Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin:
Channel Density Reduction by Routing Over The Cells. DAC 1991: 120-125 - [c10]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486 - [c9]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769 - 1990
- [j5]Youn-Long Lin, Yu-Chin Hsu:
A new algorithm for tile generation. Integr. 9(3): 259-269 (1990) - [j4]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 151-157 (1990) - [j3]Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 781-786 (1990) - [c8]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70 - [c7]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: A Cell Layout Generator. DAC 1990: 474-479 - [c6]Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu:
Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504
1980 – 1989
- 1989
- [j2]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
SILK: a simulated evolution router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1108-1114 (1989) - [c5]Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin:
A new integer linear programming formulation for the scheduling problem in data path synthesis. ICCAD 1989: 20-23 - [c4]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD 1989: 344-347 - [c3]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Routing using a pyramid data structure. ICCAD 1989: 436-439 - 1988
- [j1]Youn-Long Lin, Daniel D. Gajski:
LES: a layout expert system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 868-876 (1988) - [c2]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
A detailed router based on simulated evolution. ICCAD 1988: 38-41 - 1987
- [c1]Youn-Long Lin, Daniel Gajski:
LES: A Layout Expert System. DAC 1987: 672-678
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-16 00:42 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
