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DSD Importanat Question Unit Wise Unit 1

The document contains important questions for different units of a DSD course. Unit 1 questions focus on entity declaration, VHDL capabilities, operators, delays, and data types. Unit 2 covers differences between dataflow and behavioral modeling, structural layout, technology libraries, generics, and control structures. Unit 6 asks for short notes on types of programmable logic devices. Units 3-5 require writing VHDL code for various digital circuits and systems like adders, decoders, counters, and a 1-bit microcomputer. The questions assess a range of VHDL concepts and skills.

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205 views2 pages

DSD Importanat Question Unit Wise Unit 1

The document contains important questions for different units of a DSD course. Unit 1 questions focus on entity declaration, VHDL capabilities, operators, delays, and data types. Unit 2 covers differences between dataflow and behavioral modeling, structural layout, technology libraries, generics, and control structures. Unit 6 asks for short notes on types of programmable logic devices. Units 3-5 require writing VHDL code for various digital circuits and systems like adders, decoders, counters, and a 1-bit microcomputer. The questions assess a range of VHDL concepts and skills.

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siddharthgrg
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DSD IMPORTANAT QUESTION UNIT WISE

Unit 1
1. Explain entity in detail (e.g entity declaration, architure,
configuration & package).
2. What are the capabilities of VHDL.(J. Bhaskar)
3. Explain different types of operator are used in VHDL.
4. Explain different types of delays.
5. Explain data types used in VHDL.
6. Explain types of data objects used in VHDL.
7. Explain signal drivers and effects of delay on signal drivers.
8. Explain different types of overloading.
Unit 2
1.
2.
3.
4.
5.

Difference between dataflow and behavior model with example.


What do you understand by structural layout?
What do you understand by Technology Library?
Explain Generics with example.
Explain the following:
If statement
Wait statement
Block statement
Process statement. Etc.
Unit 6
1.Write

short note on:


FPGA
CPLD
PLA
PAL
Peel
GAL

Unit 3
1.Write VHDL code for full adder in any of the modeling. (i.e
dataflow, behavior, structure)
2.Write VHDL code for full subtractor in any of the modeling.

3.Write VHDL code for Decoder/Encoder in any of the modeling.


4.Write VHDL code for mux.(4:1,8:1,16:1)/Demux.in any of the
modeling.
5.Write VHDL code for Priority Encoder in any of the modeling.
6.Write VHDL code for comparator (1 bit & 4 bit) in any of the
modeling.
7.Write VHDL code for Parity checker in any of the modeling.
8.Write VHDL code for Code convertor (binary to gray & gray to
binary) in any of the modeling.
9.Write VHDL code for BCD to 7 Seg. decoder in any of the
modeling.
10.
Write VHDL code for Boolean equations in any of the
modeling.
Unit 4
1. Write VHDL code for Shift Registers ( PISO, PIPO, SISO, SIPO)
in any of the modeling.
2. Write VHDL code for COUNTERS (UP, DOWN, UP-DOWN) in any
of the modeling.
3. Write VHDL code for Johnson/Ring Counter in any of the
modeling.
Unit 5
1. Write VHDL code for implementation of 1 bit microcomputer
system in any of the modeling.

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