8085 Microprocessor Ramesh S. Gaonkar
8085 Microprocessor Ramesh S. Gaonkar
8085 Microprocessor Ramesh S. Gaonkar
• Reference Book:
– Ramesh S. Goankar, “Microprocessor Architecture,
Programming and Applications with 8085”, 5th Edition,
Prentice Hall
• Week 1 – Basic Concept and Ideas about Microprocessor.
• Week 2 - Architecture of 8085
• Week 3 - Addressing Modes and Instruction set of 8085
• Week 4 – Interrupts of 8085
• Week 5 onwards – Peripherals.
Basic Concepts of Microprocessors
• Differences between:
– Microcomputer – a computer with a
microprocessor as its CPU. Includes memory, I/O
etc.
– Microprocessor – silicon chip which includes
ALU, register circuits & control circuits
– Microcontroller – silicon chip which includes
microprocessor, memory & I/O in a single
package.
What is a Microprocessor?
• The word comes from the combination micro and
processor.
– Processor means a device that processes whatever. In
this context processor means a device that processes
numbers, specifically binary numbers, 0’s and 1’s.
• To process means to manipulate. It is a general term that
describes all manipulation. Again in this content, it means to
perform certain operations on the numbers that depend on the
microprocessor’s design.
What about micro?
• Micro is a new addition.
– In the late 1960’s, processors were built using discrete
elements.
• These devices performed the required operation, but were too
large and too slow.
Input Output
Memory
Inside The Microprocessor
• Internally, the microprocessor is made up of
3 main units.
– The Arithmetic/Logic Unit (ALU)
– The Control Unit.
– An array of registers for holding data while it is
being manipulated.
Organization of a microprocessor-
based system
• Let’s expand the picture a bit.
I/O
Input / Output
ALU Register
Array
System Bus
Control Memory
ROM RAM
Memory
• Memory stores information such as instructions
and data in binary format (0 and 1). It provides
this information to the microprocessor whenever
it is needed.
5FFF
6000
RAM 2 Address Range of 2nd RAM Chip
8FFF
9000
RAM 3 Address Range of 3rd RAM Chip
A3FF
A400
F7FF
FFFF
Memory
• To execute a program:
– the user enters its instructions in binary format into the
memory.
– The microprocessor then reads these instructions and
whatever data is needed from memory, executes the
instructions and places the results either in memory or
produces it on an output device.
The three cycle instruction
execution model
• To execute a program, the microprocessor “reads”
each instruction from memory, “interprets” it, then
“executes” it.
Input/Output/
Memory
Read
Write
Address latch
Multiplexed
Enable
Address Data
Bus
Address
Bus
• System Bus – wires connecting memory & I/O to
microprocessor
– Address Bus
• Unidirectional
• Identifying peripheral or memory location
– Data Bus
• Bidirectional
• Transferring data
– Control Bus
• Synchronization signals
• Timing signals
• Control signal
Architecture of Intel 8085 Microprocessor
Intel 8085 Microprocessor
• Microprocessor consists of:
– Control unit: control microprocessor operations.
– ALU: performs data processing function.
– Registers: provide storage internal to CPU.
– Interrupts
– Internal data bus
The ALU
• In addition to the arithmetic & logic circuits, the
ALU includes the accumulator, which is part of
every arithmetic & logic operation.
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
– Sign Flag
• Used for indicating the sign of the data in the accumulator
• The sign flag is set if negative (1 – negative)
• The sign flag is reset if positive (0 –positive)
• Zero Flag
– Is set if result obtained after an operation is 0
– Is set following an increment or decrement operation of that register
10110011
+ 01001101
---------------
1 00000000
• Carry Flag
– Is set if there is a carry or borrow from arithmetic operation
ALE
AD7-AD0 Latch
A7- A0
D7- D0
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR
Introduction to 8085 Instructions
The 8085 Instructions
– Since the 8085 is an 8-bit device it can have up to 28
(256) instructions.
• However, the 8085 only uses 246 combinations that represent a
total of 74 instructions.
– Most of the instructions have more than one format.
– They transfer:
• Data between registers.
• Data Byte to a register or memory location.
• Data between a memory location and a register.
• Data between an I\O Device and the accumulator.
LXI B 40 00H B 40 00 C
The Memory “Register”
• Most of the instructions of the 8085 can use a
memory location in place of a register.
– The memory location will become the “memory” register M.
• MOV M B
– copy the data from register B into a memory location.
– Which memory location?
• RLC
7 6 5 4 3 2 1 0
Accumulator
Carry Flag
• RAL 7 6 5 4 3 2 1 0
Accumulator
Logical Operations
• Compare
• Compare the contents of a register or memory location with the
contents of the accumulator.
– CMP R/M Compare the contents of the register
or memory location to the contents of
the accumulator.
– CPI # Compare the 8-bit number to the
contents of the accumulator.
• The compare instruction sets the flags (Z, Cy, and S).
– CALL Address
• Jump to the address specified but treat it as a subroutine.
– RET
• Return from a subroutine.
– MVI A, 32
• Operation: MVI A
• Operand: The number 32
• Binary Code:
0011 1110 3E 1st byte.
0011 0010 32 2nd byte.
Instruction with a Memory
Address
• Operation: go to address 2085.
Initialize
Body of loop
No Is this
Final
Count?
Yes
Sample ALP for implementing a loop
Using DCR instruction
MVI C, 15H
LOOP DCR C
JNZ LOOP
Using a Register Pair as a Loop
Counter
• Using a single register, one can repeat a loop for a
maximum count of 255 times.
LXI B, 1000H
LOOP DCX B
MOV A, C
ORA B
JNZ LOOP
Delays
• It was shown in Chapter 2 that each instruction
passes through different combinations of Fetch,
Memory Read, and Memory Write cycles.
• Knowing the combinations of cycles, one can
calculate how long such an instruction would
require to complete.
• The table in Appendix F of the book contains a
column with the title B/M/T.
– B for Number of Bytes
– M for Number of Machine Cycles
– T for Number of T-State.
Delays
• Knowing how many T-States an instruction
requires, and keeping in mind that a T-State is one
clock cycle long, we can calculate the time using
the following formula:
• TO = 7 T-States
– Delay of the MVI instruction
• TO = 10 T-States
– The delay for the LXI instruction
Body of loop 2
loop. Is this
No
– In the figure, the body of Final
Count?
loop2 can be before or
Yes
after loop1.
Nested Loops for Delay
• Instead (or in conjunction with) Register Pairs, a
nested loop structure can be used to increase the
total delay produced.
• Total Delay
– TDelay = 57412 X 0.5 µSec = 28.706 mSec
Increasing the delay
• The delay can be further increased by using
register pairs for each of the loop counters
in the nested loops setup.
• It can also be increased by adding dummy
instructions (like NOP) in the body of the
loop.
Timing Diagram
Representation of Various Control signals generated during
Execution of an Instruction.
Following Buses and Control Signals must be shown in a
Timing Diagram:
•Higher Order Address Bus.
•Lower Address/Data bus
•ALE
•RD
•WR
•IO/M
Timing Diagram
Instruction:
A000h MOV A,B
Corresponding Coding:
A000h 78
Timing Diagram
Instruction:
A000h MOV A,B
Corresponding Coding:
A000h 78
OFC
8085 Memory
Timing Diagram
Instruction: T1 T2 T3 T4
A000h 78
ALE
RD
OFC WR
IO/M
8085 Memory
Op-code fetch Cycle
Timing Diagram
Instruction:
A000h MVI A,45h
Corresponding Coding:
A000h 3E
A001h 45
Timing Diagram
Instruction:
A000h MVI A,45h
Corresponding Coding:
OFC
A000h 3E
MEMR
A001h 45
8085 Memory
Timing Diagram
T1 T2 T3 T4 T5 T6 T7
A0h A0h
A15- A8 (Higher Order Address bus)
00h 3Eh 01h 45h
DA7-DA0 (Lower order address/data Bus)
Instruction:
A000h MVI A,45h
ALE
Corresponding Coding:
RD
A000h 3E
A001h 45
WR
IO/M
Instruction:
A000h LXI A,FO45h
Corresponding Coding: OFC
A000h 21 MEMR
MEMR
A001h 45
A002h F0 8085 Memory
Timing Diagram
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
ALE
RD
WR
IO/M
Timing Diagram
Instruction:
A000h MOV A,M
Corresponding Coding:
A000h 7E
Timing Diagram
Instruction:
A000h MOV A,M
OFC
Corresponding Coding: MEMR
A000h 7E
8085 Memory
Timing Diagram
T1 T2 T3 T4 T5 T6 T7
A0h Content Of Reg H
A15- A8 (Higher Order Address bus)
00h 7Eh L Reg Content Of M
Instruction: DA7-DA0 (Lower order address/data Bus)
WR
IO/M
Instruction:
A000h MOV M,A
Corresponding Coding:
A000h 77
Timing Diagram
Instruction:
A000h MOV M,A
OFC
Corresponding Coding: MEMW
A000h 77
8085 Memory
Timing Diagram
T1 T2 T3 T4 T5 T6 T7
A0h Content Of Reg H
A15- A8 (Higher Order Address bus)
00h 7Eh L Reg Content of Reg A
Instruction: DA7-DA0 (Lower order address/data Bus)
WR
IO/M
location pointed to by SP F3
FFFC
FFFD
FFFE 12
FFFF SP
The POP Instruction
• POP D
– Copy the contents of the memory location
pointed to by the SP to register E
– Increment SP
– Copy the contents
D E
of the memory location
pointed to by
12 the
F3 SP to register D
FFFB
– Increment SP FFFC
FFFD F3 SP
FFFE 12
FFFF
Operation of the Stack
• During pushing, the stack operates in a
“decrement then store” style.
– The stack pointer is decremented first, then the
information is placed on the stack.
PUSH B
PUSH D
...
POP D
POP B
The PSW Register Pair
• The 8085 recognizes one additional register pair
called the PSW (Program Status Word).
– This register pair is made up of the Accumulator and
the Flags registers.
2
Tri-State Buffers
An important circuit element that is used
extensively in memory.
This buffer is a logic circuit that has three states:
Logic 0, logic1, and high impedance.
When this circuit is in high impedance mode it looks
as if it is disconnected from the output completely.
3
The Tri-State Buffer
This circuit has two inputs and one output.
The first input behaves like the normal input for the
circuit.
The second input is an “enable”.
If it is set high, the output follows the proper circuit
behavior.
If it is set low, the output looks like a wire connected to
nothing.
Input Output OR Input Output
Enable Enable
4
The Basic Memory Element
The basic memory element is similar to a D
latch.
This latch has an input where the data comes in.
It has an enable input and an output on which
data comes out.
Data Input Data Output
D Q
Enable
EN
5
The Basic Memory Element
However, this is not safe.
Data is always present on the input and the output is
always set to the contents of the latch.
To avoid this, tri-state buffers are added at the input
and output of the latch.
Data Input Data Output
D Q
WR RD
Enable
EN
6
The Basic Memory Element
The WR signal controls the input buffer.
The bar over WR means that this is an active low
signal.
So, if WR is 0 the input data reaches the latch input.
If WR is 1 the input of the latch looks like a wire
connected to nothing.
The RD signal controls the output in a similar
manner.
7
A Memory “Register”
If we take four of these latches and connect
them together, we would have a 4-bit memory
register
I0 I1 I2 I3
WR
D D D D
Q Q Q Q
EN EN EN EN
EN
RD O0 O1 O2 O3
8
A group of memory registers
D0 D1 D2 D3
o o o o
WR
D Q D Q D Q D Q
EN EN EN EN
D Q D Q D Q D Q
EN EN
Expanding on this
EN EN
EN EN EN EN
o o o o
RD
D0 D1 D2
9 D3
Externally Initiated Operations
External devices can initiate (start) one of the 4
following operations:
Reset
All operations are stopped and the program counter is reset to 0000.
Interrupt
The microprocessor’s operations are interrupted and the
microprocessor executes what is called a “service routine”.
This routine “handles” the interrupt, (perform the necessary
operations). Then the microprocessor returns to its previous
operations and continues.
10
A group of Memory Registers
If we represent each memory location (Register) as
a block we get the following
I0 I1 I2 I3
WR Input Buffers
RD Output Buffers
O0 O1 O2 O3
11
The Design of a Memory Chip
Using the RD and WR controls we can determine the
direction of flow either into or out of memory. Then
using the appropriate Enable input we enable an
individual memory register.
12
The Enable Inputs
How do we produce these enable line?
Since we can never have more than one of these
enables active at the same time, we can have them
encoded to reduce the number of lines coming into
the chip.
These encoded lines are the address lines for
memory.
13
The Design of a Memory Chip
So, the previous diagram would now look like the
following: I 0 I I I1 2 3
WR Input Buffers
A D Memory Reg. 0
d e
A1 d c Memory Reg. 1
r o
e Memory Reg. 2
A0 d
s e Memory Reg. 3
s r
RD Output Buffers
O0 O1 O2 O3
14
The Design of a Memory Chip
Since we have tri-state buffers on both the inputs
and outputs of the flip flops, we can actually use
WR one set of pins only.
Input Buffers
The
A D chip Memory
d e
would Reg.now
0 look likeDthis:
0 D0
A1 d c Memory Reg. 1 D1 A1 D1
r o
e Memory Reg. 2 D2 D2
A0 d A0
s e Memory Reg. 3
s r D3 D3
RD Output Buffers
RD WR
15
The steps of writing into Memory
What happens when the programmer issues the
STA instruction?
The microprocessor would turn on the WR control
(WR = 0) and turn off the RD control (RD = 1).
The address is applied to the address decoder which
generates a single Enable signal to turn on only
one of the memory registers.
The data is then applied on the data lines and it is
stored into the enabled register.
16
Dimensions of Memory
Memory is usually measured by two numbers: its length
and its width (Length X Width).
The length is the total number of locations.
The width is the number of bits in each location.
18
Chip Select
Usually, each memory chip has a CS (Chip Select)
input. The chip will only work if an active signal is
applied on that input.
19
Chip Selection Example
Assume that we need to build a memory system
made up of 4 of the 4 X 4 memory chips we
designed earlier.
20
Chip Selection Example
RD
WR
D0
D1
RD WR RD WR RD WR RD WR
A0 A0 A0 A0
A1 A1 A1 A1
CS CS CS CS
A0
A1
A2 2 X4
A3 Decoder
21
Memory Map and Addresses
The memory map is a picture representation of
the address range and shows where the different
memory chips are located within the address
range.
0000 0000
EPROM Address Range of EPROM Chip
3FFF
4400
RAM 1 Address Range of 1st RAM Chip
Address Range
5FFF
6000
RAM 2 Address Range of 2nd RAM Chip
8FFF
9000
RAM 3 Address Range of 3rd RAM Chip
A3FF
A400
F7FF
FFFF
22
Address Range of a Memory Chip
The address range of a particular chip is the list of all
addresses that are mapped to the chip.
23
Address Range of a Memory Chip
The above example can be modified slightly to make it closer
to our discussion on memory.
• Let’s say that this post office has only 1000 boxes.
• Let’s also say that these are grouped into 10 groups of 100 boxes each.
Boxes 0000 to 0099 are in group 0, boxes 0100 to 0199 are in group 1
and so on.
The upper digit of the box number identifies the group and the lower two
digits identify the box within the group.
24
The 8085 and Address Ranges
The 8085 has 16 address lines. So, it can
address a total of 64K memory locations.
If we use memory chips with 1K locations each, then
we will need 64 such chips.
The 1K memory chip needs 10 address lines to
uniquely identify the 1K locations. (log21024 = 10)
That leaves 6 address lines which is the exact
number needed for selecting between the 64
different chips (log264 = 6).
25
The 8085 and Address Ranges
Now, we can break up the 16-bit address of the 8085
into two pieces:
Chip Selection Location Selection within the Chip
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
26
Chip Select Example
A chip that uses the combination A15 - A10 =
001000 would have addresses that range from
2000H to 23FFH.
Keep in mind that the 10 address lines on the chip gives a range of
00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips.
The memory chip in this example would require the following circuit on its
chip select input:
A 10
A 11
A 12 CS
A 13
A 14
A 15
27
Chip Select Example
If we change the above combination to the following:
A 10
A 11
A 12 CS
A 13
A 14
A 15
28
Chip Select Example
To illustrate this with a picture:
in the first case, the memory chip occupies the piece of
the memory map identified as before.
In the second case, it occupies the piece identified as
after. Before After
0000 0000
2000
23FF 2400
27FF
FFFF FFFF
29
High-Order vs. Low-Order Address Lines
The address lines from a microprocessor can be
classified into two types:
High-Order
Used for memory chip selection
Low-Order
Used for location selection within a memory chip.
30
Data Lines
All of the above discussion has been regarding memory
length. Lets look at memory width.
We said that the width is the number of bits in each
memory word.
We have been assuming so far that our memory chips have
the right width.
What if they don’t?
It is very common to find memory chips that have only 4 bits per
location. How would you design a byte wide memory system using
these chips?
We use two chips for the same address range. One chip will supply 4
of the data bits per address and the other chip supply the other 4 data
bits for the same address.
31
Data Lines
CS
A0
…
A9
CS CS
D0
…
D3
D4
…
D7
32
Interrupts
Interrupts
• Interrupt is a process where an external device can
get the attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.
RST0 CALL
0000H
D D
76543210
11101111
Hardware Generation of RST
Opcode
• During the interrupt acknowledge machine cycle,
(the 1st machine cycle of the RST operation):
– The Microprocessor activates the INTA signal.
– This signal will enable the Tri-state buffers, which will
place the value EFH on the data bus.
– Therefore, sending the Microprocessor the RST 5
instruction.
– The vectors for these interrupt fall in between the vectors for the
RST instructions. That’s why they have names like RST 5.5
(RST 5 and a half).
Masking RST 5.5, RST 6.5 and
RST 7.5
• These three interrupts are masked at two
levels:
– Through the Interrupt Enable flip flop and the
EI/DI instructions.
• The Interrupt Enable flip flop controls the whole
maskable interrupt process.
– Through individual mask flip flops that control
the availability of the individual interrupts.
• These flip flops control the interrupts individually.
Maskable Interrupts
RST7.5 Memory
RST 7.5
M 7.5
RST 6.5
M 6.5
RST 5.5
M 5.5
INTR
Interrupt
Enable
Flip Flop
The 8085 Maskable/Vectored
Interrupt Process
1. The interrupt process should be enabled using the
EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If there is an interrupt, and if the interrupt is
enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call instruction
that sends the execution to the appropriate location
in the interrupt vector table.
The 8085 Maskable/Vectored
Interrupt Process
5. When the microprocessor executes the call
instruction, it saves the address of the next
instruction on the stack.
6. The microprocessor jumps to the specific service
routine.
7. The service routine must include the instruction EI
to re-enable the interrupt process.
8. At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted.
Manipulating the Masks
• The Interrupt Enable flip flop is manipulated using
the EI/DI instructions.
M5.5
M7.5
M6.5
MSE
SDO
R7.5
SDE
XXX
RST5.5 Mask
Serial Data Out RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked
M7.5
M6.5
M5.5
MSE
SDO
R7.5
SDE
XXX
- Enable 5.5 bit 0 = 0
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
0 0 0 0 1 0 1 0
- Allow setting the masks bit 3 = 1
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0 Contents of accumulator are: 0AH
- Don’t use serial data bit 6 = 0
- Serial data is ignored bit 7 = 0
IE
RST 6.5
M 6.5
RST 5.5
M 5.5
Interrupt Enable
Flip Flop
How RIM sets the Accumulator’s
different bits
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
P6.5
P7.5
P5.5
SDI
IE
RST5.5 Mask
Serial Data In RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked
M7.5
M6.5
M5.5
P6.5
P7.5
P5.5
SDI
IE
RIM ; Read the current settings.
0 0 0 0 0 0 1 0
MSE
M7.5
M6.5
M5.5
R7.5
SDO
SDE
XXX
TRAP
• TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot be
disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again until
it goes low, then high again.
Dev. 6
I7 INTA
Dev. 5
I6 INTR
8 8
I5 AD7
Dev. 4
2
I4 AD6 0
I3 5 AD5
Dev. 3
I2 9 AD4 8
AD3
I1 A AD2 5
Dev. 2 AD1
I0
AD0
Dev. 1
Dev. 0
Operating of the 8259A
• The 8259A requires the microprocessor to
provide 2 control words to set up its operation.
After that, the following sequence occurs:
1. One or more interrupts come in.
2. The 8259A resolves the interrupt priorities based on
its internal settings
3. The 8259A sends an INTR signal to the
microprocessor.
4. The microprocessor responds with an INTA signal
and turns off the interrupt enable flip flop.
5. The 8259A responds by placing the op-code for the
CALL instruction (CDH) on the data bus.
Operating of the 8259A
6. When the microprocessor receives the op-code for
CALL instead of RST, it recognizes that the device
will be sending 16 more bits for the address.
7. The microprocessor sends a second INTA signal.
8. The 8259A sends the high order byte of the ISR’s
address.
9. The microprocessor sends a third INTA signal.
10. The 8259A sends the low order byte of the ISR’s
address.
11. The microprocessor executes the CALL instruction
and jumps to the ISR.
Direct Memory Access
• This is a process where data is transferred between
two peripherals directly without the involvement
of the microprocessor.
– This process employs the HOLD pin on the
microprocessor
• The external DMA controller sends a signal on the HOLD pin
to the microprocessor.
• The microprocessor completes the current operation and sends
a signal on HLDA and stops using the buses.
• Once the DMA controller is done, it turns off the HOLD signal
and the microprocessor takes back control of the buses.
Serial I/O and Data
Communication
Basic Concepts in Serial I/O
• Interfacing requirements:
– Identify the device through a port number.
• Memory-mapped.
• Peripheral-mapped.
– Enable the device using the Read and Write control
signals.
• Read for an input device.
• Write for an output device.
– Only one data line is used to transfer the information
instead of the entire data bus.
Basic Concepts in Serial I/O
• Controlling the transfer of data:
– Microprocessor control.
• Unconditional, polling, status check, etc.
– Device control.
• Interrupt.
Synchronous Data Transmission
• The transmitter and receiver are synchronized.
– A sequence of synchronization signals is sent before the
communication begins.
• Message based.
– Synchronization occurs at the beginning of a long
message.
Asynchronous Data Transmission
• Transmission occurs at any time.
• Character based.
– Each character is sent separately.
D0 D1 D2 D3 D4 D5 D6 D7 Stop
One Character
Time
Simplex and Duplex
Transmission
• Simplex.
– One-way transmission.
– Only one wire is needed to connect the two devices
– Like communication from computer to a printer.
• Half-Duplex.
– Two-way transmission but one way at a time.
– One wire is sufficient.
• Full-Duplex.
– Data flows both ways at the same time.
– Two wires are needed.
– Like transmission between two computers.
Rate of Transmission
• For parallel transmission, all of the bits are sent at
once.
• For serial transmission, the bits are sent one at a
time.
– Therefore, there needs to be agreement on how “long”
each bit stays on the line.
– Even Parity
• The transmitter counts the number of ones in the data. If there
is an odd number of 1’s, bit D7 is set to 1 to make the total
number of 1’s even.
• The receiver calculates the parity of the received message, it
should match bit D7.
– If it doesn’t match, there was an error in the transmission.
Checksum
• Used when larger blocks of data are being
transmitted.
Output Port
Accumulator
D5 0
D4 0
D3 0
D2 0
D1 0 D0
D0 1
Start
Stop 0 1 0 0 0 0 0 1
Time
Flowchart of Serial Transmission
Set up Bit Counter
Set bit D0 of A to 0 (Start Bit)
Rotate A Left
Decrement Bit Counter
No
Last Bit?
Yes
Add Parity
Send Stop Bit(s)
Software-Controlled Serial
Reception
• The main steps involved in serial reception are:
– Wait for a low to appear on the transmission line.
• Start bit
– Read the value of the line over the next 8 bit lengths.
• The 8 bits of the character.
– Calculate parity and compare it to bit 8 of the character.
• Only if parity checking is being used.
– Verify the reception of the appropriate number of stop
bits.
Serial Reception
D7
0 D7
1 D6
Accumulator
0 D5
Input Port
0 D4
0 D3
0 D2
0 D1
1 D0
Shift
Start
Stop 0 1 0 0 0 0 0 1
Time
Flowchart of Serial Reception
Read Input Port
Wait Bit Time
Read Input Port
No
Start Bit?
No Bit Still No
Last Bit?
Low?
Yes Yes
Check Parity
Start Bit Counter Wait for Stop Bits
The 8085 Serial I/O Lines
• The 8085 Microprocessor has two serial I/O
pins:
– SOD – Serial Output Data
– SID – Serial Input Data
M5.5
M7.5
M6.5
MSE
SDO
R7.5
SDE
XXX
M5.5
M7.5
M6.5
P6.5
P7.5
P5.5
SDI
IE
– Serial Data Input
Serial Input Data
11 RD
INTE
10 C WR
A1 RNAL
DEC 01 B
A0 ODIN
G PORT
00 A B
1 01
EN
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
0/1
1
8255A
+5V GROUP
POWER I/O
SUPPLIES GND GROUP A PA7-PA0
A PORT
CON- A
TROL (8)
GROUPA I/O
PORT C PC7-PC4
UPPER
BIDIRECTION
AL DATA BUS DATA (4)
BUS
D1,D0
BUFFER GROUPB I/O
8-BIT
INTERNAL
PORT C PC3-
DATA BUS LOWER PC0
(4)
RD READ/
WR GROUP GROUP
WRITE
A1
B B I/O
CONTROL
A0 CON- PORT PB7-
LOGIC
RESET
TROL B PB0
(8)
1
CS
Control Word Format for
I/O Mode
D7 D6 D5 D4 D3 D2 D1 D0
Group B
PORT CL (PC3-PC0)
1= INPUT;0= OUTPUT
PORT B
1= INPUT;0= OUTPUT
MODE SELECTION
0=MODE0; 1=MODE 1
PORT A
1= INPUT; 0=OUTPUT
MODE SELECTION
1
00= MODE 0;01= MODE 1;1X= MODE 2
PA7
PA0
PC7
PC4
8255A
PC3
CS
A1
PC0
A0
PB7
RD
WR
PB0
RESET
1
Mode 0 ( Simple Input or
Output )
PROBLEM 1)
Interface 8255a to a 8085 microprocessor using I/O-mapped -
I/O technique so that Port a have address 80H in the system.
Determine addresses of Ports B,C and control register.
Write an ALP to configure port A and port CL as output ports
and port B and port CU as input ports in mode 0.
Connect DIP switches connected to the to input ports and
LEDs to the output ports .
Read switch positions connected to port A and turn on the
respective LEDs of port b. Read switch positions of port CL and
display the reading at port CU
1
BSR (Bit Set/Reset ) Mode
BSR control word
D7 D6 D5 D4 D3 D2 D1 D0
000 = Bit 0
1
Mode 1: Input or Output with
Handshake
INTEA Port A Input PA7-PA0 Port A with
STBA Handshake
PC4
Signal
PC5 IBFA
PC3
INTRA
INTEB
PC2 STBB
Port b with
PC1 IBFB
Handshake
INTRB Signal
PC0
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0 1 1 x
Port B
I/O
Mode Input
Port A Port B
Mode 1 Mode 1
Port A PC6,7
Input 1 1=Input;
0=Output
Status Word – Mode 1 input
D7 D6 D5 D4 D3 D2 D1 D0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
1
STB
IBF
INTR
RD
Input from
peripheral 1
INTEA PA7-PA0
Port A Output Port A with
OBFA Handshake
PC7
Signal
PC6 ACKA
PC3
INTRA
INTEB
PC2 OBFB
Port b with
PC1 ACKB
Handshake
INTRB Signal
PC0
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1/0 1 0 x
Port B
I/O
Mode Output
Port A Port B
Mode 1 Mode 1
Port A PC4,5
Output 1 1=Input;
0=Output
Status Word – Mode 1 Output
D7 D6 D5 D4 D3 D2 D1 D0
OBFA INTEa I/O I/O INTRA INTEB OBFB INTRB
1
WR
OBF
INTR
ACK
output 1
Status
Interrupt
Initialize Ports
Initialize Ports
Read port
C for status Enable INTE
No
Yes
No
Is
Peripheral Continue
Ready?
yes
1
Continue
Problem 3)
1
8086 MICROPROCESSOR
Pinouts
I-46
8086 Pins
The 8086 comes in a 40 pin package which means that some pins have
more than one use or are multiplexed. The packaging technology of time
limited the number of pin that could be used.
In particular, the address lines 0 - 15 are multiplexed with data lines 0-15,
address lines 16-19 are multiplexed with status lines. These pins are
The 8086 has one other pin that is multiplexed and this is BHE’/S7.
BHE stands for Byte High Enable. This is an active low signal that is
asserted when there is data on the upper half of the data bus.
The 8086 has two modes of operation that changes the function of some pins.
The SDK-86 uses the 8086 in the minimum mode with the MN/MX’ pin tied to
5 volts. This is a simple single processor mode. The IBM PC uses an 8088
in the maximum mode with the MN/MX” pin tied to ground. This is the mode
required for a coprocessor like the 8087.
I-47
8086 Pins
In the minimum mode the following pins are available.
HOLD When this pin is high, another master is requesting control of the
local bus, e.g., a DMA controller.
I-48
8086 Pins
The following are pins are available in both minimum and maximum modes.
GND Ground
READY Acknowledgement from wait-state logic that the data transfer will
be completed.
RESET Stops processor and restarts execution from FFFF:0. Must be high
for 4 clocks. CS = 0FFFFH, IP = DS = SS = ES = Flags = 0000H, no
other registers are affected.
TEST’ The WAIT instruction waits for this pin to go low. Used with 8087.
CLK Clock: 33% duty cycle, i.e., high 1/3 the time.
I-49
8086 Features
• 16-bit Arithmetic Logic Unit
The address refers to a byte in memory. In the 8088, these bytes come in on
the 8-bit data bus. In the 8086, bytes at even addresses come in on the low
half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper
half of the data bus (bits 8-15).
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations. The 8088 needs two operations in either case.
I-8
8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).
• The BIU fetches instructions, reads and writes data, and computes the
20-bit address.
• The EU decodes and executes the instructions using the 16-bit ALU.
The BIU fetches instructions using the CS and IP, written CS:IP, to contruct
the 20-bit address. Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode.
I-9
8086 Block Diagram
I-10
8086 Architecture
The EU contains the following 16-bit registers:
AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Register
The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers are:
AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL
I-11
Flag Register
Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
NT IOPL OF DF IF TF SF ZF AF PF CF
Sign Flag (Bit 7), SF: 0 for positive number and 1 for negative number
Zero Flag (Bit 6), ZF: If the ALU output is 0, this bit is set (1); otherwise,
it is 0
Carry Flag (Bit 0), CF: It contains the carry generated during the execution
Auxiliary Carry, AF: Depending on the width of ALU inputs, this flag
(Bit 4) bit contains the carry generated at bit 3 (or, 7, 15)
of the 8088 ALU
Parity Flag (bit2), PF: It is set (1) if the output of the ALU has even number
of ones; otherwise it is zero
Direction Flag
Direction Flag (DF) is used to control the way SI and DI are adjusted during the
execution of a string instruction
— DF=0, SI and DI will auto-increment during the execution; otherwise, SI and DI
auto-decrement
— Instruction to set DF: STD; Instruction to clear DF: CLD
— Example:
CLD DS : SI
MOV CX, 5 0510:0000 53 S SI CX=5
REP MOVSB 0510:0001 48 H SI CX=4
0510:0002 4F O SI CX=3
0510:0003 50 P SI CX=2
At the beginning of execution, 50 P SI CX=1
0510:0004
DS=0510H and SI=0000H
0510:0005 45 E SI CX=0
0510:0006 52 R
Source String
8086 Programmer’s Model
ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer
AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
EU registers SI Source Index Register
16 bit arithmetic DI Destination Index Register
FLAGS
I-13
Memory Address Calculation
Examples
CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0
DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
EEE/CSE 226
Segments
Address
Segment Starting address is segment 0H
register value shifted 4 places to the left.
CODE
64K Data
STACK Segment
DATA
EXTRA ← CS:0
64K Code
Segment
Segment
Registers
0B2000H
SS: 0B200H STACK
0C1FFFH
CS: 0FF00H
0FF000H
CODE
0FFFFFH
4000H
CS: 0400H
IP 0056H 4056H
CS:IP = 400:56
Logical Address
Memory
0400 0
Segment Register
Offset + 0056
Physical or 04056H
0FFFFFH
Absolute Address
The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.
I-16
The Stack Segment 0H
0A000H
SS: 0A00
0A100H
SP 0100 SS:SP
Memory
0A00 0
Segment Register
Offset + 0100
0FFFFFH
Physical Address 0A100H
I-17
The Data Segment 0H
05C00H
DS: 05C0
05C50H
EA 0050 DS:EA
Memory
05C0 0
Segment Register
Offset + 0050
I-18
8086 memory Organization
Even addresses are on the low half
of the data bus (D0-D7).
Exceptions
String addressing
Port addressing (e.g. IN AL, 79H)
Data Transfer Instructions
MOV Destination, Source
— Move data from source to destination; e.g. MOV [DI+100H], AH
— It does not modify flags
For 80x86 family, directly moving data from one memory location to
another memory location is not allowed
When the size of data is not clear, assembler directives are used
MOV [SI], 0
BYTE PTR MOV BYTE PTR [SI], 12H
WORD PTR MOV WORD PTR [SI], 12H
DWORD PTR MOV DWORD PTR [SI], 12H
PUSH Source
— Push data (word) onto stack
— It does not modify flags
— For Example: PUSH AX (assume ax=1234H, SS=1000H, SP=2000H
before PUSH AX)
1000:1FFD ?? 1000:1FFD ??
1000:1FFE ?? SS:SP 1000:1FFE 34
1000:1FFF ?? 1000:1FFF 12
SS:SP 1000:2000 ?? 1000:2000 ?? 12 34
Decrementing the stack pointer during a push is a standard way of implementing stacks in hardware
Instructions for Stack Operations
PUSHF
— Push the values of the flag register onto stack
— It does not modify flags
POP Destination
— Pop word off stack
— It does not modify flags
— For example: POP AX
1000:1FFD ?? 1000:1FFD ??
SP 1000:1FFE 34 1000:1FFE 34
1000:1FFF 12 1000:1FFF 12
1000:2000 EC SP 1000:2000 EC 12 34
POPF
— Pop word from the stack to the flag register
— It modifies all flags
Data Transfer Instructions
SAHF
— Store data in AH to the low 8 bits of the flag register
— It modifies flags: AF, CF, PF, SF, ZF
LAHF
— Copies bits 0-7 of the flags register into AH
— It does not modify flags
XLAT
— Replace the data in AL with a data in a user defined look-up table
— BX stores the beginning address of the table
— At the beginning of the execution, the number in AL is used as the
index of the look-up table
— It does not modify flags
String Instructions
String is a collection of bytes, words, or long-words that can be up to 64KB
in length
String instructions can have at most two operands. One is referred to as source
string and the other one is called destination string
— Source string must locate in Data Segment and SI register points to the current
element of the source string
— Destination string must locate in Extra Segment and DI register points to the current
element of the destination string
DS : SI ES : DI
0510:0000 53 S 02A8:2000 53 S
0510:0001 48 H 02A8:2001 48 H
0510:0002 4F O 02A8:2002 4F O
0510:0003 50 P 02A8:2003 50 P
0510:0004 50 P 02A8:2004 50 P
0510:0005 45 E 02A8:2005 49 I
0510:0006 52 R 02A8:2006 4E N
Source String Destination String
Repeat Prefix Instructions
REP String Instruction
— The prefix instruction makes the microprocessor repeatedly execute the string instruction
until CX decrements to 0 (During the execution, CX is decreased by one when the string
instruction is executed one time).
— For Example:
MOV CX, 5
REP MOVSB
By the above two instructions, the microprocessor will execute MOVSB 5 times.
DS : SI ES : DI
MOV AX, 0510H 0510:0000 53 S 0300:0100
MOV DS, AX 0510:0001 48 H
MOV SI, 0
0510:0002 4F O
MOV AX, 0300H
MOV ES, AX 0510:0003 50 P
MOV DI, 100H 0510:0004 50 P
CLD 0510:0005 45 E
MOV CX, 5
0510:0006 52 R
REP MOVSB
Source String Destination String
String Instructions
CMPSB (CMPSW)
— Compare bytes (words) at memory locations DS:SI and ES:DI;
update SI and DI according to DF and the width of the data being compared
— It modifies flags
—Example:
Assume: ES = 02A8H DS : SI
DI = 2000H ES : DI
0510:0000 53 S 02A8:2000 53 S
DS = 0510H
SI = 0000H 0510:0001 48 H 02A8:2001 48 H
0510:0002 4F O 02A8:2002 4F O
CLD 0510:0003 50 P 50
02A8:2003 P
MOV CX, 9 50 P 50 P
0510:0004 02A8:2004
REPZ CMPSB 0510:0005 45 E I
49
02A8:2005
0510:0006 52 R 02A8:2006 4E N
What’s the values of CX after
Source String Destination String
The execution?
String Instructions
SCASB (SCASW)
— Move byte (word) in AL (AX) and at memory location ES:DI;
update DI according to DF and the width of the data being compared
— It modifies flags
LODSB (LODSW)
— Load byte (word) at memory location DS:SI to AL (AX);
update SI according to DF and the width of the data being transferred
— It does not modify flags
STOSB (STOSW)
— Store byte (word) at in AL (AX) to memory location ES:DI;
update DI according to DF and the width of the data being transferred
— It does not modify flags
Repeat Prefix Instructions
REPZ String Instruction
— Repeat the execution of the string instruction until CX=0 or zero flag is clear
The displacement is the number that, when added to the IP, changes the
IP to point at the jump target. Remember the IP is pointing at the next
instruction when this occurs.
The loop instructions perform several operations at one time but do not
change any flags.
I-40
8254 Internal Architecture
Data CLK 0
Counter GATE 0
D7-D0 8 Bus
=0
Buffer OUT 0
RD Read/ CLK 1
WR Counter
Write GATE 1
=1
A0 Logic OUT 1
A1
CS
Control CLK 2
Counter
Word GATE 2
=2
Register OUT 2
THE CONTROL WORD REGISTER AND COUNTERS
ARE SELECTED
ACCORDING TO THE SIGNALS ON LINE
A0 and A1 AS SHOWN BELOW
A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Register
8254 Control Word Format
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
RW1 RW0
SC1 SC0
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
MODE 0 : Interrupt on terminal count
Clk
WR 3 2 1 0
Output
Interrupt
MODE 1 : HARDWARE-RETRIGGERABLE
ONE-SHOT
Clk
WR 3 2 1 0
Output
MODE 2 : RATE GENERATOR CLOCK
Clk
WR
3 2 1 0 3
OUTPUT
MODE 3 : Square Wave Generator
Clk
OUTPUT(n=4) 4 2 4 2 4 2 4 2
OUTPUT(n=5) 5 4 2 5 2 5 4 2
MODE 4 : SOFTWARE TRIGGERED STROBE
• TRAP
• RST 7.5
• RST6.5
• RST5.5
• INTR