Microprocessor Systems: Asst - Prof.Dr. Haldun Sarnel
Microprocessor Systems: Asst - Prof.Dr. Haldun Sarnel
Microprocessor Systems: Asst - Prof.Dr. Haldun Sarnel
Class Materials
Text
book
Notes
Several related .pdf files
Advances in Semiconductor
Technology
Moores Law
1965 prediction by Intel cofounder
Gordon Moore:
The number of transistors that can be
built on the same size piece of silicon
will double every 18 months
A typical Programmable
Machine/System
Microprocessor
Microprocessor
I/O
Physical Devices
Program a group of instructions
preformed by the microprocessor
Software a group of programs
Memory
Microprocessor
I/O
Microprocessor vs.
Microcontroller
Microprocessor
single-chip only contains a CPU (Central Processing Unit) like the kind used in a PC
bus is available on the chip pins
ROM and RAM capacity, number of ports are selectable during system design
RAM is usually larger than ROM
includes some of the components on a chip and other components are used as
peripherals.
suitable to processing information in computer systems.
Microcontroller
A Microprocessor as a
Programmable Device
The
piano is a programmable
machine
Microprocessor has
different instructions :
The Memory
Word Addressing
l log 2 M
Example: to address 64 MB
(1 million words is 1024 x 1024),
we need :
Memory Organization
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
...
Types of Memory
Cache Memory
Stores programs and data that the computer needs when executing a
program
Dynamic RAM (DRAM)
ROM
Memory Hierarchy
The idea
Input / Output
Input
Devices
Switches , Keyboard, .
Output
Devices:
The
Microprocessor as CPU
1.
2.
3.
4.
Instruction Process
Von Neumann execution cycle
Fetch instruction from memory
Decode instruction
Evaluate address
Fetch operands from memory
Execute operation
Store result
Microprocessor Programming
Assembly language
for (i=0;i<8;i++)
Source Code
Compiler /
Interpreter
Object Code
(machine code)
Assembly Code
Assembler
Object Code
(machine code)
Reading Assignment
Please
Microprocessor-Based System
Microprocessor-Based System
Memory
Microprocessor
I/O
of instructions
What it does:
instruction
Writes the data to the output devices
Microprocessor Unit
Can it be interrupted ?
Program initiated operation interrupt done by a
program.
Peripheral initiated operation interrupt done by external
devices
Set
of logic circuits
Control
Clock
circuits
Program-initiated operations
and Buses
Microprocessor
Memory Read
Memory Write
I/O Read
I/O Write
Program-initiated operations
and Buses
Buses
Address Bus
Identify the memory
locations
Data Bus
Holds the data during
transfer operation
Control Lines
For timing signal
Buses
Address
can be accessed
Z80 has 16 address lines to address 216 locations
Data
Interruptions categories :
Wait: the memory can not handle the MPU request , wait signal must be
generated.
Bus Request: sometimes the processor is too slow to hand a request that can
be handled faster by another device.
E.g transfer large amount of data through the DMA could be faster than
using the MPU
Memory
Memory
Cell
Q(t+1)
Reset
Set
Memory (Continue)
4-bit
Register
4 X 8 bit register
Input
Input Buffer
WR
A1
A0
2-to-4 Decoder
Register 3
Register 2
Memory Unit
Register 2
Register 0
Output Buffer
RD
Output
The memory puts the data on the data bus and the
processor will read it
Reading Assignments
Review
What
Memory Read
Memory Write
I/O Read
I/O Write
Question
What
13
How
21 lines
Question
Specify
256*4
No
Question
If
Question
16 bit BUS
1024 X 16
Question
State
The memory puts the data on the data bus and the
processor will read it
8-bit Microprocessor
16- bit address lines
+5 V Power Supply
Housed in 40 pin dual in Line
(DIP) 2 sides
different versions of Z80
microprocessors such as Z80,
Z80A, Z80B and Z80H
rated to operate at various
frequencies ranging from 2.5MHz
to 8MHz.
53
54
Signal Classification
All
address bus
data bus
control signals
external requests
request acknowledge and special signals
power and frequency signals
Address Bus
Data Bus
Control and
Status Signals
Five
individual output
lines:
Control and
Status Signals
M1
Control and
Status Signals
MREQ
Memory Request:
Control and
Status Signals
IORQ
I/O Request:
Control and
Status Signals
RD - Read:
Control and
Status Signals
WR
Write:
Indicates that the microprocessor
has already placed a data byte on
the data bus and is ready to write
into memory or an I/O device
Should be used in conjunction
with
for the Memory
Write (MREQ
) operation
should MEMWR
be used in conjunction
with
for the I/O Write (
IOWR
IORQ
) operation.
External Requests
Used to interrupt an
ongoing process and to
request the microprocessor
to do something else.
External Requests
RESET Reset:
External Requests
External Requests
NMI
Nonmaskable Interrupt
It cannot be disabled. It is
activated by a negative edgetriggered signal from an external
source.
Used primarily for implementing
emergency procedures.
No Ack signal is generated
External Requests
BUSRQ Bus Request:
Initiated by external I/O devices such as
the DMA (Direct Memory Access)
controller
External Requests
WAIT
This
Wait:
BUSAK
RFSH Refresh:
- Clock:
Used
to connect a single
phase frequency source.
The
Z80 CPU
B
U
F
F
E
R
8
INTERNAL DATA BUS (8 BIT)
MUX
INSTRUCTION
REGISTER
MUX
W'
Z'
B'
C'
D'
E'
H'
L'
DECODER
A'
F'
DATA BUS
TMP
ACT
IX
IY
SP
CONTROLLER
SEQUENCER
CONTROL
SECTION
ALU
PC
k
k
ADDRESS BUS
B
U
F
F
E
R
CONTROL BUS
B
U
F
F
E
R
16
13
Accumulator and a
flag register (8-bit)
General-purpose
register arrays (8-bit)
registers as memory
pointers
(16-bit)
special-purpose
registers
(8-bit)
Register Set
General-purpose registers
Part of the arithmetic logic unit (ALU) and is also identified as register A
All 8-bit arithmetic and logical instructions take one of the operands from the
accumulator and return the result to the accumulator
The shortest and fastest data transfers between the microprocessor and I/O
devices are performed through the accumulator.
More memory reference instructions move data between the accumulator and
memory than between any other register and memory.
Register Set
includes six flip-flops that are set or reset according to data conditions after
an ALU operation
7
6
5
4
3
2
1
0
D0 - D7 are the ALU status flag
S Z X H X PV N C
S
Z
H
P
V
N
C
Register Set
Alternate registers (A F B C D E H L)
A duplicate set of general-purpose registers. Exchange
instructions select and deselect all alternate registers.
EXX
EX AF, AF (AF)<->(AF')
Register Set
Register Set
What is Stack ?
Top of the Stack is indicated by the contents of the SP. That is the
SP shows the address of the most recently made entry, because
the memory locations are organized as a last-in first-out file.
Register Set
Memory Refresh register (R)
Only the lower 7 bits are included in the addition (bit 7 unchanged)
During instruction fetch from memory, the low order address is
used to supply a 7-bit address for refresh