PDC Lab Manual

PULSE & DIGITAL CIRCUITS
LAB MANUAL
Department of Electronics and Communication Engineering
PULSE AND DIGITAL CIRCUITS LAB

INDEX
S.NO 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. NAME OF THE EXPERIMENT LINEAR WAVE SHAPING NON LINEAR WAVE SHAPING CLIPPERS NON LINEAR WAVE SHAPING CLAMPERS TRANSISTOR AS A SWITCH ASTABLE MULTIVIBRATOR MONOSTABLE MULTIVIBRATOR BISTABLE MULTIVIBRATOR SCHMITT TRIGGER UJT RELAXATION OSCILLATOR BOOTSTRAP SWEEP CIRCUIT SAMPLING GATES STUDY OF LOGIC GATES AND APPLICATIONS STUDY OF FLIP-FLOPS AND APPLICATIONS PAGE 16 7 -14 15 18 19 23 24 27 28 31 32 36 37 41 42 46 47 51 52 54 55 64 65 - 74
LAB MANUAL
1. LINEAR WAVE SHAPING

Aim: Design a RC LPF and HPF at various time constants and verify the responses for Square wave input (choose C = 0.1f, Vi =v= 4 VP-P, f = 10 K Hz). Apparatus: S.No 1. 4. 5. 6. 7. 8. 9. Name of the component/Equipments Resistors Capacitors Bread board Connecting wires Function generator CRO Decade resistance box Specification 100 1k 10K 0.1uf Quantity 1 1 1 1 1 1 Bunch 1 1 1
Circuit diagram: High Pass Filter:
Theory: The output of HP RC network is the diffrentiation of the applied input signal. Hence this type of network is called diffrentiator . It was seen that for a high pass RC network,
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d/dt(Vi)=d/dt(Vo)+V0/RC
LAB MANUAL
= > d/dt(Vo)=d/dt(Vi) - 1/RC
If the time constant =RC is far less than the periodic time (RC/T<<1) , the transient response becomes insignificant and the steadt state response becomes predominent, Ignoring the transient response , (1/RC) V0 = d/dt(vi) (or) V0 =RC d/dt(vi) Since R and C are of fixed magnitude V0 d/dt(vi) i.e; the output is proportional to the time derivative of the input. Hence the circuit is called as differentiator Design / Calculations:
a) RC = T Given T = 1/10KHz = 0.1 mSec R= (0.1 X10 -3) /0.1f = 1 K ohms . V1= V / (1+ e T/2RC) =2.49v V1 = V
1+e T/2RC =1.51 v % tilt =2 (V1-V1)/V =(2.49-1.51)/2 = 49% Model Graph:
T1=T2=T/2 b) RC >> T Choose RC = 10T = 1 m Sec

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R= (10 -3)/(0.1x10 -6) =10 k ohms The output waveform will be identical to input
LAB MANUAL
Model Graph:
T1=T2=T/2
b) RC << T RC = 0.1 T R= (0.1x 10 -4)/(0.1x10 -6) Model Graph:
LAB MANUAL
Low Pass Filter: Circuit Diagram:
Theory: We know that for a low pass RC circuit V0/RC +d/dt(V0) =Vi/RC Where RC is the time constant of the circuit. Let it be assumed that RC >>T , the periodic time of the input signal Vi . For a large time constant, it is evident that the output takes a fairly long time to come to steady state and as such the transient response is very predominant and the steady state response becomes insignificant and hence can be ignored. Put, (1/RC)V0=0, we have d/dt(Vo) =(1/RC)Vi By integrating on both sides, we get V0 = (1/RC) Vi dt.
V0 Vi dt
i.e; R,C are fixed magnitude .
And the output is proportional to the time integral of the input. For this reason the low pass RC circuit with RC>>T is called integrator.
Design / Calculations:
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(a) RC=T C=0.1f , R= 1K Ohms V2=V(e T/2RC -1) /2 (e T/2RC +1) =0.49V V1=-0.49v
LAB MANUAL
Model Graph:
( b)
RC >> T R = 10 K, C = 0.1 f V2=V(e T/2RC -1) /2 (e T/2RC +1) =0.05V
V1=0.05V Model Graph:
(c) RC << T R = 100,

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C = 0.1 f
LAB MANUAL
Model Graph:
Note: Low Pass Filter allows the DC component of I/P signal and High Pass Filter block the DC component of I/P Signal. Procedure: 1. Connect the circuit as shown in figure (LPF / HPF) 2. Apply the Square wave input to this circuit (Vi = 4 VP-P, f = 10KHz) 3. Observe the output waveform for (a) RC = T, (b) RC>>T, (c) RC>>T 4. Verify the values with theoretical calculations. Precautions: Use two CRO probes and observe I/P & O/P waveforms simultaneously by putting CRO on DC modes. Result: LPF and HPF are designed at various time constants and the responses for square wave input is observed & hence plotted Questions:
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1. When HP-RC circuit is used as Differentiator? 2. Draw the responses of HPF to step, pulse, ramp inputs? 3. Draw the responses of LPF to step, pulse, ramp inputs? 4. Define % tilt and rise time? 5. When LP-RC circuit is used as integrator? 6. Why noise immunity is more in integrator than differentiator?
LAB MANUAL
2. NON-LINEAR WAVE SHAPING CIRCUITS - CLIPPERS

Aim: a) To study the clipping circuits using diodes. b) To observe the transfer characteristics of all the clipping circuits in CRO. Apparatus: S.No 1. 3. 4. 5. 6. 7. Name of the component/Equipments Resistors Diodes Bread board Connecting wires Function generator CRO Specification 1k 10K 1N4007 Quantity 1 1 1 1 1 Bunch 1 1
Circuit Diagram Series Diode Clipper:Shunt Diode Clipper:

Series Diode Clipper with Bias:
LAB MANUAL Shunt Diode Clipper with Bias
Slicer:
Theory: A clipping circuit comprises of linear elements like resistors and non-linear elements like diodes or transistor, but it does not contain energy storage elements capacitors. Clipping circuits basically limit the amplitude of the input signal either below or above certain voltage level. They are referred to as Voltage limiters, Amplitude selectors or Slicers. A clipping circuit is one, in which a small section of input waveform is missing or cut or truncated at the out put section. Clipping circuits are classified based on the position of Diode. 1. Series Diode Clipper 2. Shunt Diode Clipper. Procedure: 1. Connect the circuit as shown in fig.1 2. In each case apply 10 VP-P, 1KHz Sine wave I/P using a signal generator. 3. O/P is taken across the load RL. 4. Observe the O/P waveform on the CRO and compare with I/P waveform. 5. Sketch the I/P as well as O/P waveforms and mark the numerical values. 6. Note the changes in the O/P due to variations in the reference voltage VR = 2V,3V.. 7. Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y mode.
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Precautions:
8. Repeat the above steps for all the circuit.
LAB MANUAL
1. Set the CRO O/P channel in DC mode always. 2. Observe the waveform simultaneously by keeping common ground. 3. See that there is no DC component in the I/P. 4. To find transfer characteristics apply input to the X-Channel, O/P to Y-Channel, adjust the dot at the center of the screen when CRO is in X-Y mode. Both the channels must be in ground, then remove ground and plot the transfer characteristics.
Model Graph: Input Wave Form
Out put wave form for Series Diode Clipper:
Out put wave form for Shunt Diode Clipper:
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LAB MANUAL
Out put wave form for series Diode Clipper with bias:
Out put wave form for shunt Diode Clipper with bias:
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LAB MANUAL
Result: Different types of clipping circuits have been studied and observed the responses for various combinations of VR and clipping diodes.
Questions: 1. Define clipping circuit? 2. What are the different types of clippers? 3. What is a break region? 4. Which kind of a clipper is called a slicer circuit? 5. What are the disadvantages of the shunt clipper? 6. What are the disadvantages of the series clipper? 7. What is piecewise linear mode of a diode?
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LAB MANUAL
3. NON-LINEAR WAVE SHAPING CIRCUITS - CLAMPERS
Aim: To study the clamping circuits using diodes and capacitors. Apparatus: S.No 1. 2. 3. 4. 5. 6. 7. Name of the component Resistors Diodes Capacitor Bread board Connecting wires Function generator CRO
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Specification 100k 1N4007 0.1f
Quantity 1 1
1 1 Bunch 1 1

8.
Dual Regulated Power supply
(0-30) V DC
LAB MANUAL 1
Circuit Diagrams: Negative Clamper

C1 0.1uf IN4007 R1 100 k
Positive Clamper
C1 0.1uf IN4007 R1 100 k
Biased Ve clamper (-Vr)

C1 0.1uf IN4007 5V R1 100 k
Biased +Ve Clamper:
Theory:
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LAB Clamping circuits add a DC level to an AC signal. A clamper is also refer to MANUAL as DC
restorer or DC reinserted. The Clampers which clamp the given waveform either above or below the reference level, which are known as positive or negative clamping respectively. They are of two types (i) (ii) Negative clamper. Positive clamper.
Negative clamper is also termed as positive peak clamper , since circuit clamps the positive peak to zero level. Similarly positive clamper is termed as negative peak clamper , since the circuit clamps the negative peak to zero level. Procedure: 1. Connect the circuit as shown in fig.1. 2. Apply a Sine wave of 10VP-P, 1KHz at the input terminals with the help of SignalGenerator. 3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and mark the values with VR =2 V, 3V 4. O/P is taken across the load RL. 5. Repeat the above steps for all clamping circuits as shown. 6. Waveforms are drawn assuming diode is ideal. Model graph: I/P Wave Form
Out put wave forms for ve Clamper:
Out put wave forms for +ve Clamper:
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LAB MANUAL
Biased Ve Clamper
Biased +Ve Clamper:
Result: Different types of clamping circuits are studied and observed the response for different combinations of VR and diodes. Questions: 1.What are the applications of clamping circuits? 2.What is the synchronized clamping? 3.Why is a clamper called a dc inserter? 4.What is clamping circuit theorem. How dose the modified clamping Circuit theorem differs from this?
4. TRANSISTOR AS A SWITCH
Aim: Design Transistor to act as a Switch and verify the operation. Choose VCC = 10V, ICmax = 10 m A, hfe =50, VCE Sat = 0.2, V in = 4Vp-p, VBE Sat = 0.6 V. Apparatus: S.No 1. 3. Name of the component Resistors Transistor
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Specification 1k 8.2k BC 107
Quantity 1 1 1

4. 5. 6. 7. 8. Bread board Connecting wires Function generator CRO Dual Regulated Power supply (0-30) V DC
LAB MANUAL 1
1 Bunch 1 1 1
Circuit Diagram:
Theory: When the I/P voltage Vi is negative or zero, transistor is cut-off and no current flows through Rc , henceV0 VCC when I/P Voltage Vi jumps to positive voltage, transistor will be driven into saturation. Then V0 = Vcc ICRC VCEsat Design procedure: When Q is ON, Rc= (Vcc- VCE sat) / Ic max = (10-0.2)/10 mA =1 k ohms IB ICmax / hfe 10mA / 50
IB 0.2 mA To keep transistor remain in ON, IB should be greater than Vin = IBRB + VBE Sat 2V = 0.2 mA RB + 0.6V
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Procedure:-
RB= 7 K ohms (choose practical values as 8.2 K )
LAB MANUAL
1. Connect the circuit as shown in figure. 2. Apply the Square wave 4 Vp-p frequency of 1 KHz 3. Observe the waveforms at Collector and Base and plot it. Precautions: 1. When you are measuring O/P waveform at collector and base, keep the CRO in DC mode. 2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2 or 0.5 position. 3. When you are applying the square wave see that there is no DC voltage in that. This can be checked by CRO in either AC or DC mode, there should not be any jumps/distortion in waveform on the screen. Model Graph:
Result: Transistor as a switch has been designed and O/P waveforms are observed. .
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Questions: 1. Differentiate between Diode and Transistor as a switch? 2. Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors? 3. Define ON time, OFF time of the transistor? 4. In which regions Transistor acts as a switch?
LAB MANUAL
5. Explain phenomenon of latching in a Transistor switch? 6. Define Rise time & fall time of a transistor switch?
5. ASTABLE MULTIVIBRATOR
Aim :19

= 1nf, 10nf, 100nf. Apparatus: S.No 1.
LAB MANUAL To design an Astable Multivibrator to generate a Square wave of 1KHzfrequency. Choose C
Name of the component Resistors
5. 6. 7. 8. 9.
Transistor Bread board Connecting wires CRO Dual Regulated Power supply
Specification 1k 72k 724k 7.2k BC 107
Quantity 2 2 2 2 2 1 1 Bunch 1
(0-30) V DC
Circuit diagram:-
Theory: The astable circuit has two quasi-stable states. Without external triggering signal the astable configuration will make successive transitions from one quasi-stable state to the other. The astable circuit is an oscillator. It is also called as free running multivibrator and is used to generate Square Wave. Since it does not require triggering signal, fast switching is possible.
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Design: The period T is given by T = T1 + T2 = 0.69 (R1C1 + R2C2) For symmetrical circuit with R1 = R2 = R & C1 = C2 = C T = 1.38 RC 10-3 = 1.38 x 10-9 x R R = 72.4K (When c=1nf) ; R= (10 -3) /1.38X10X10 -9 =72.4 K (where c=10nf) R=7.24 K (where c=100nf) Let Vcc=15V ,hfe=51(for BC 107) Vbe sat=0.7V , Vce sat=0.3 V Choose Ic max=10 mA RC = (VCC VCESat) / ICmax = (15 0.3) / (10 x 10-3) = 1.47K RC 1K Procedure: 1. Connect the circuit as shown in figure. 2. Apply the supply voltage Vcc =15V
LAB MANUAL
3. Calculate the pulse width (T) of the Astable O/P with the selected values of R & C on the CRO. See that CRO is in DC mode. 4. Connect the CRO channel-1 to the collector and base of the Transistor Q1&Q2.. 5. Measure the pulse width and verify with the theoretical value. 6. Obtain waveforms at different points like VB1, VB2, VC1 & VC2. .
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Expected wave forms:-
LAB MANUAL
Result : An Astable Multivibrator is designed, the waveforms are observed and verified the results theoretically. Questions: 1. Is it possible to change time period of the waveform with out changing R & C? Support your answer? 2. Collector waveforms are observed with rounded edges. Explain? 3. Explain charging and discharging of capacitors in an Astable Multivibrator? 4. How can an Astable multivibrator be used as VCO? 5. Why do you get overshoots in the Base waveforms? 6. What are the applications of Astable Multivibrator? 7. How can Astable multivibrator be used as a voltage to frequency converter? 8. What is the formula for frequency of oscillations? 9. What are the other names of Astable multivibrator?
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PULSE & DIGITAL CIRCUITS 6.MONOSTABLE MULTIVIBRATOR

Aim : To design a monostable multivibrator for the Pulse width of 0.03mSec. Apparatus: S.No 1. Name of the component Resistors Specification 1k 72k 724k 7.2k BC 107
LAB MANUAL
5. 6. 7. 8. 9.
Transistor Bread board Connecting wires CRO Dual Regulated Power supply
Quantity 2 2 2 2 2 1 1 Bunch 1
(0-30) V DC
1. Monostable Multivibrator trainer kit. 2. Function Generator. 3. CRO. 4. Multi-meter. 5. Connecting patch cards. Circuit Diagram:-
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LAB MANUAL
Theory: The monostable circuit has one permanently stable and one quasi-stable state. In the monostable configuration, a triggering signal is required to induce a transition from the stable state to the quasi-stable state. The circuit remains in its quasi-stable for a time equal to RC time constant of the circuit. It returns from the quasi-stable state to its stable state without any external triggering pulse. It is also called as one-shot a single cycle, a single step circuit or a univibrator
Design:To design a monostable multivibrator for the Pulse width of 0.03mSec. Choose ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10K. T = RC ln 2 T = 0.69 RC Choose C = 10nf 0.3 x 10-3Sec = 0.69 x R x 10 x 10-9 R = 43.47 K.
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Rc= (Vcc- Vce sat)/ Ic max. RC = (15 0.2) / 15mA 1K
LAB MANUAL
For more margin Given, VB1= -1.185 VB1= -VBB R1 + R1+R2 Vce sat R2 R1+R2
-1.18=( -15 R1+ 0.2 R2) / (R1+R2)
Given R1=10 K
We will R2= 100K
Procedure: 1. Wire the circuit as shown in the circuit diagram. 2. Calculate the pulse width (T) of the Monostable O/P with the selected values of R & C on the CRO. See that CRO is in DC mode. 3. Select the triggering pulse such that the frequency is less than 1/T 4. Apply the triggering input to the circuit and to the CROs channel 1 . Connect the CRO channei-2 to the collector and base of the TransisterQ1&Q2.. 5. Adjust the triggering pulse frequency to get stable pulse on the CRO and now measure the pulse width and verify with the theoretical value. 6. Obtain waveforms at different points like VB1, VB2, VC1 & VC2. 7. Repeat the experiment for different combinations of R & C (C = 1nf, 100nf). Calculate R for same value of T = 0.3 mSec. Result : A collector coupled Monostable Multivinbrator is designed, the waveforms are observed and verified the results theoretically.
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LAB MANUAL
Expected wave forms:-
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LAB MANUAL
7. BISTABLE MULTIVIBRATOR
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Aim: a) Design the Bi-stable Multivibrator circuit and verify the operation. b) Obtain the resolving time of Bi-stable Multivibrator and verify theoretically Choose R1 = 10K, C = 0.3f, Vce(sat) = 0.2V, ICmax = 15mA, VCC = 15V, VBB = 15V, VB1 = -1.2V Apparatus: s.no 1. 2. 3. 4. 5. 6. 7. 8. Theory: Name of the component Transistor Diode Resistors Capacitors RPS Bread board Connecting wires CRO Specification BC107b IN4007 1k 10k 100k 0.33uf 0.001uf
LAB MANUAL
Quantity 2 3 5 2 2 3 2 1 1 --1
A Bistable circuit is one which can exist indefinitely in either of two stable states and which can be induced to make an abrupt transition from one state to the other by means of external excitation. The Bistable circuit is also called as Bistable multivibrator, Eccles jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, FlipFlop & Binary. A bistable multivibratior is used in a many digital operations such as counting and the storing of binary information. It is also used in the generation and processing of pulse-type waveform. They can be used to control digital circuits and as frequency dividers . There are two outputs available which are complements of one another. i.e. when one output is high the other is low and vice versa .
Design : Rc = [Vcc Vce (sat) ] / Ic(max)

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RC = (15 0.2) / 15mA 1K Choose RC = 1K, VB1 = (-Vbb R1 / R1+ R2) / (Vce (sat) R2 / R1+R2) -1.2 = (-15x10+0.2R2)/(10+ R2); R2 = 100k
LAB MANUAL
fmax = (R1+R2 )/2CR1R2 = (10+100k)/(2x0.3x10-6x10kx100k) = 55khz Procedure: 1. Check the square wave output from CRO to conform the voltage is 0.5Vpp. 2. Connect the circuit as shown in the circuit diagram 3. Apply sine wave as input at the transistor Q1 across collector and emitter terminals 4. Check whether the output waveform at the transistor Q2 is square wave or not 5. Measure the amplitude of output wave form and check whether the loop gain is less than 1 6. Similarly apply the input at transistor Q2 7. Repeat the steps 3 and 4 and note down the amplitude and output waveform Result: Bistable Multivibrator circuit is designed and output waveforms are observed
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LAB MANUAL
Circuit diagram:
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LAB MANUAL
Expected waveforms:
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LAB MANUAL
Questions: 1. What are the applications of a Bitable multivibrator? 2. Describe the operation of commutating capacitors? 3. Why is a Binary also called a flip-flop? 4. Mention the name of different kinds of triggering used in the circuit shown? 5. What are the disadvantages of direct coupled Binary? 6. How many types of unsymmetrical triggering are there? 7. What are catching diodes? 8. Which triggering is used in binary counting circuits?
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LAB MANUAL
8. SCHMITT TRIGGER
Aim:To study the operation of Schmitt trigger circuit and find the UTP and LTP voltages & compare with the theoretical values. Apparatus: s.no 1. 2. 4. 5. 6. 7. 8. 9. Theory: Schmitt trigger is a special type of bistable multivibrator which has several important practical applications. The Schmitt trigger is a emitter coupled binary. Since the emitter of Q1 and Q2 are joined and they are grounded through a common resistor Re. The base of Q1 is connected to a voltage source Vi. The output is an unsymmetrical square wave. Thus the Schmitt trigger converts the sinusoidal wave to square. It is therefore termed as sine to square wave converter or squaring circuit. However the output of a Schmitt trigger is a square wave, whatever the waveforms of the input signal. Another application of Schmitt trigger is as a flip-flop. Name of the component Transistor Resistors Capacitors RPS Bread board Connecting wires Function generator CRO Specification BC107a 1k 10k 100k 0.1uf Quantity 2 2 2 2 1 1 1 ----1 1
Theoretical calculations: i) Calculation of V1 [UTP] V1 = V1-0.1V where V1 = (Vcc R2)/(RC1+R1+R2)
V1 = (Vcc R2)/(RC1+R1+R2)
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V1 = UTP = V1 0.1V
=>12x10k / (1k+10k+10k) = 5.714V
LAB MANUAL
= 5.714V 0.1V = 5.61V ii) Calculation of V2 [LTP] a = R2/(R1+ R2) = 10k/(10k+10k) =0.5 V1 = aVT => 0.5x12V =6V (since VT = Vcc)
R = RC1(R1+ R2)/ (RC1+R1+R2) = 1k(10k+10k)/( 1k+10k+10k) = 952.38 VBE1 = 0.6V & V2 = 0.6V V2 = VBE1 + (Re/aR+ Re)( V1- V2) = 0.6+[100/(0.5x952.38)+100](6-0.6) = 1.53V Procedure:
1. Connect the circuit on the bread board as per circuit diagram 2. Keep the peak to peak input voltage 10V using function generator 3. Keep the VCC voltage at 12V constant using regulated power supply 4. Observe the output waveform in the CRO 5. Plot the values and draw the graph 6. Calculate the upper triggering point & lower triggering point Result:
The operation of Schmitt trigger is verified and the UTP & LTP voltages in both theoretically and practically compared and verified
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LAB MANUAL
Circuit diagram :
V c c ( 1 2
v )
2 1 k 0 . 1 u f
4 1 k
1 o R 1 k V 1 1
V o
1 0 1
V p - p k h z
3 1 0 k
3 1 0 0 o h m s
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LAB MANUAL
Expected wave form
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LAB MANUAL
Questions: 1. What are the applications of Schmitt Trigger? 2. Define hysteresis action? 3. Why is Schmitt Trigger called a squaring circuit? 4. What is UTP? 5. What is LTP? 6. What is the difference between a Binary and Schmitt Trigger?
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LAB MANUAL
9. UJT RELAXATION OSCILLATOR

Aim: To study the operation of UJT Relaxation Oscillator Apparatus: s.no 1. 2. 4. 5. 6. 7. 8. 9. Name of the component UJT Resistors Capacitors RPS Bread board Connecting wires Function generator CRO Specification 2N2646 68 560 100k 0.1uf Quantity 1 1 1 1 1 1 1 ----1 1
Theory: The UJT exhibits a negative resistance characteristics, it can be used to provide time delayed trigger pulses for activating other devices like SCR. The basic trigger circuit is shown in the figure. The external resistances R B1and R B2 are of the UJT base. The emitter potential Ve is varied depending on the charging rate of capacitor C. The Charging resistance Rc should be such that the load line intersects the device characteristics only, in the negative resistance region AB. If the Rc load line intersects the device characteristics either in region PR or in BQ ,the resulting operating point will be stable and the circuit will not oscillate. This sets the max and minimum limits on the permissible values of Rc. As the Capacitor charges, when the emitter voltage goes to the peak point voltage
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B1
LAB (Vb+VD ) , regeneration will start and the capacitor will discharges through MANUAL resistor R
. The rise time of the output pulse will depend on the switching speed of the UJT, and the duration will be proportional to the time constant RB1C of the discharge
circuit. The emitter base -1 diode will again be reverse biased until the capacitor is charged to (Vb+VD ) . The output pulses are shown in figure and the duration and their period T is given by T = RC ln (1/1-) Procedure: 1. Connect the circuit on the bread board as per circuit diagram 2. A resistor of 68 is connected to B1 and 560 resistor is connected to B2 3. Apply VCC= 8V to the resistor 100k and B2 4. Take the output across the emitter of UJT 5. Note down the time period and amplitudes of output waveform Result: The waveforms are plotted as shown and the practical T is verified to the theoretical value.
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LAB MANUAL
Circuit diagram:
+ 8 R B 2 R 2 6 8 0 o h m s R 3 1 0 0 k V
B 2
B 1
o u t p u t R 1 6 8 o h m s C 1 0 . 1 u
R B 1
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LAB MANUAL
Expected waveforms:
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LAB MANUAL
Questions: 1. What is a relaxation oscillator? 2. Specifications of UJT? 3. What is the importance of UJT? 4. When will be UJT is switched
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LAB MANUAL
10. BOOTSTRAP SWEEP GENERATOR

Aim: To study the operation of a Boot strap sweep generator Apparatus: s.no 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Theory: The circuit employs positive feed back and it generates positive going ramp and employs an emitter follower whose gain is nearly unity. The amplifier must have high input resistance. In this the capacitor current can be maintained constant by incorporating an auxiliary voltage source such that the source voltage is always equal to the capacitor voltage but acts in opposition to it. In this circuit both V & R are fixed magnitude current I is constant. This constant current I flowing through the capacitor develops a ramp voltage across it. Boot strap sweep circuit uses to generate a ramp voltage. When the input Vi goes positive ,Q1 off , potential of A rises. This increases of voltage at A is transmitted to B through Q2 and capacitor CB. The result is that the potential of B alsom rise by the same amount. This is the principle of Boot strap.
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Name of the component Transistor Resistors Diode Capacitors RPS Bread board Connecting wires Function generator CRO Decade resistance box
Specification CL100S 10 1k 470 IN4148 0.1uf 100uf
Quantity 1 1 1 1 1 1 2 1 1 ----1 1 1
LAB MANUAL
Procedure: 1. Connect the circuit as per the circuit diagram on bread board 2. Apply 8VPP square wave input in function generator and VCC = 12V & VEE = -12V 3. Place the 300kpf from the decade capacitance box and note the output wave form across emitter of second transistor 4. Repeat the same by placing 400kpf & 500kpf in the place of variable capacitor 5. Plot the graph between Vi vs t & Vo vs t
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LAB MANUAL
Circuit diagram:
C 1 R 1 1 k 0
1 0 u f
R C 1 8 s q u a r e V p - p w a v e i n p u t 0 2 0 u 1 f
2 0 k
R 4 C 5 C 0 4 . 1 u f
3 7 0 k
V E E ( 1 2 v )
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LAB MANUAL
Expected wave forms:
Result: Thus the operation of Boot strap sweep generator is observed

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LAB MANUAL
Questions: 1. Explain the basic principle involved in Bootstrap Sweep generator. 2. Mention the type of feed back employed in Bootstrap Sweep generator. 3. Mention the characteristics of the amplifier used in Bootstrap sweep generator.
11. SAMPLING GATES

Aim:
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Apparatus: s.no 2. 3. 4. 5. 6. 7. 8. 9. Theory:
LAB To study the output wave form of the Uni-directional diode sampling gate MANUAL
Name of the component Resistors Diode Capacitors RPS Bread board Connecting wires Function generator CRO
Specification 10k 1k IN4007 0.1uf
Quantity 2 1 2 1 1 1 ----1 1
In the absence of the control signal, it is easily seen that diode D1 is forward biased and hence it conducts. The current through R develops a large voltage drop across it with the result that the voltage at A is less than the cut-in voltage of D0. Hence there is no conduction through D0, and the output is zero. If a positive going control signal is applied, it is evident that diode D1 gets reverse biased and hence conduction through it stops. Diode D0 gets forward biased and as a result the input signal gets transmitted through the gate for the duration of control signal. Procedure: 1. Connect the circuit as per the circuit diagram on bread board 2. Apply input 12V dc supply and control signal is 6V square wave 3. Take the output across the RL and note the amplitude and time period 4. Tabulate the readings and draw the graph
Result: Thus the out put wave form of sampling gate is observed
Circuit diagram:
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R 1 + 1 2 v D C 0 2 k I N 4 D 0 2 0 7
LAB MANUAL
i n p u t C 1 0 . 1 u f
c o n t r o l 6 V , 1
i n pR u t 1 K h z w a v e 1 1 0 k
R 1
3o u t p u t k
s q u a r e
Expected wave forms:
49
LAB MANUAL
12. Study of Logic gates and Applications

50

Aim:
LAB MANUAL
To verify the truth table of logic gates and also verify the truth table of half adder & full adder using basic gates Apparatus: 1. Digital logic trainer containing bread board and 5V dc supply 2. 7400 IC Quadrant two input NAND gate 3. 7402 IC Quadrant two input NOR gate 4. 7408 IC Quadrant two input AND gate 5. 7404 IC Quadrant two input NOT gate 6. 7432 IC Quadrant two input OR gate 7. 7486 IC Quadrant two input EX-OR gate 8. Connecting patch chords Theory : NOT, AND, OR gates are called as basic gates & NAND, NOR gates are called as Universal gates We can implement the basic logic gates using the universal gates i) NOT gate:- The NOT gate is also called as an inverter, since it performs the inversion operation on the given input. For instance if the input is logic 1, the out put is the compliment of it i.e. logic 0. And if the input is logic 0 then the out put is logic 1 vice versa. ii) AND gate:- The out put of this gate is 1 if and only if both the inputs are high i.e. logic 1, otherwise logic 0. iii) OR gate:- The out put of this gate is low only when both the inputs are low, otherwise logic 1 iv) NAND gate: This gate is compliment to the AND gate .The out put of this gate is LOW only when both the inputs are high, otherwise 1 v) NOR gate :- This gate is the compliment of the OR gate. The output of this gate is high only when both the inputs are low otherwise 0 vi) EX-OR gate:- The output of this gate is 1 only when the no.of inputs are odd otherwise 0
51

Half adder:-
LAB MANUAL
This is a combinational circuit which can add two binary bits and in result it give sum & carry The Boolean expression for sum is A xor B and for carry is A.B Full adder:This is also a combinational circuit which can add two binary bits along with the input carry. The Boolean expression for SUM is A xor B xor Cin and carry is given by AB+BCin+Cin A Procedure :1. Connect the logic gates on the digital logic trainer as per the circuit diagram 2. Apply 5V to one terminal and 0V to another terminal of AND gate and note down the output voltage same way take input voltages as (0V,5V), (0V,0V) & (5V,5V) and note the output voltages. 3. Similarly repeat this procedure for all the logic gates and universal gates like NAND & NOR and note down the o/p voltages in each case 4. Then construct the Half adder & Full adder circuits on the logic trainer and verify the out put voltages as per the truth table
Result:
The truth tables of all the logic gates (NOT,AND, OR) ,Universal gates (NAND, NOR) and Half adder, Full adder circuits are also verified successfully.
52

I. Verifying the logic gates using ICs:
LAB MANUAL
s.no 1.
Gate NOT (IC 7404)

A 1
Symbol A 0 1
2 A'
Input B -
Out put C 1 0
2.
AND (IC 7408)
4 2 5
C =
A B
3.
OR (IC 7432)
A 4 5 B 2 C
4.
NAND (7400)
A 1 2 B C= (AB)' 3
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0
5.
NOR (7402)
A 4 5 B
C = 2
( A + B ) '
6.
EX-OR (7486)
A
14
1 2
C= A'B+AB' 3
II. REALIZATION OF ALL GATES USING NOR GATE:

53

NOT gate:
LAB MANUAL
4 5
C
2
A '
OR gate: A B
4 5
( A + B ) '4
5
C
2
( A + B )
AND gate: A
4 5 2
A '
4 5
C
2
A B
4 2 5
B '
NAND gate: A
4 5 2
A '
4 5
C
2
4 5
A B
C
2
( A B ) '
4 2 5
B '
54

NOT gate:
III. REALIZATION USING NAND GATE:
LAB MANUAL
1 2
A'
AND gate: C=AB

1 2 3
A B
1 2
(AB)'
3
OR gate:
1 2
A'
3
1 2
C = (A+B)
3
1 2
B'
NOR gate:
55

A
1 2
LAB MANUAL
A'
3
1 2
C = (A+B) 1
2
C=(A+B)'
3
1 2
14
B'
IV. VERIFYING THE LOGIC GATES USING DISCRETE COMPONENTS AND gate
V C C
4 . 7 k A B C Y = A B C
OR gate:
A B C
4 . 7 k Y = A + B + C
56

NOT gate:
V C C
LAB MANUAL
5 V
2 . 2 k 0 . 0 1 u f Y = A ' A
2 3
4 . 7 k 4 . 7 k
0
B C
1
5 4 7
NAND gate:
V C C
5 V
2 . 2 k 4 . 7 k
Y = ( A B C ) '
A B C
I N 4 0 0 7 I N 4 0 0 7 I N 4 0 0 7
I N 4 0 0 I N 4 0 0 7 7
2
B C
1
5 4 7
4 . 7 k
0
57

Logic diagram of Half adder :
A B
LAB MANUAL
1 2
Sum=A'B+AB'
3
4 5
Carry=AB
2
Truth table for Half adder: Input A 0 0 1 1 B 0 1 0 1 Output Sum 0 1 1 0 carry 0 0 0 1
Logic diagram of Full adder :

58

A B C
LAB MANUAL
1 2
Sum=(A'B+AB')xor C
3
4 5
4 5
4 5
Carry=AB+BC+CA
4 5
Truth table for Full adder:
Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1
Output Sum 0 1 1 0 1 0 0 1
carry 0 0 0 1 0 1 1 1
Questions:
59
1. Why NAND & NOR gates are called universal gates? 2. Realize the EX OR gates using minimum number of NAND gates.
LAB MANUAL
3. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates. 4. Realize the given logic function using NAND and also using NOR gates. F = ABC+ABC+ABC
5. Explain the operation of NAND gate when realized using discrete components. 6. In what regions does the transistor is operated such that it behaves like a Switch. 7. What are the logic low and High levels of TTL ICs and CMOS ICs. 8. Compare TTL logic family with CMOS family. 9. Which logic family is called fastest and which logic family is called low power dissipated. 10. Explain the operation of OR, NOR gates when realized using discrete Components 11. Why the transistor operates as NOT gate.
60
PULSE & DIGITAL CIRCUITS 13. STUDY OF FLIP FLOPS & APPLICATIONS
Aim: To verify the truth tables of different flip flops i) SR flip flop (set/ reset flip flop) ii) D flip flop (delay flip flop) iii) JK flip flop iv) T flip flop (Toggle) v) Master slave JK flip flop
LAB MANUAL
Apparatus: i) Digital logic trainer kit for flip flops ii)7400 IC Quadrant two input NAND gate iii) 7404 IC One input NOT gate iv) 7476 IC Dual JK flip flop
Theory: Flip flop is nothing but a 1-bit storage device. There are many types of flip flops used in different digital applications. They are SR, Clocked SR, D, T, JK & Master slave JK flip flop. In SR flip flop if S=0 & R=0 the next state is an indeterminate state. This problem can be rectified by using JK flip flop. But there is another problem in this Jk flip flop i.e. for J=1 & K=1 the next state of the flip flop is toggle state. This can be rectified by using Master slave JK flip flop. D flip flop is also called as delay flip flop. Whatever the input given to this flip flop, at the out put we will get the same but with a small amount of time delay. The main application of D flip flops are in the ports of the microprocessors.
61
LAB MANUAL T flip flop is also called as toggle flip flop, if T=1 then the next state of the flip flop is
compliment of the present state. Otherwise the next state is also same as the present state means unchanged.
Procedure: 1. Make the connections as per the circuit diagram on logic trainer kit 2. Take the clock pulse from the kit 3. Apply possible conditions for each flip flop 4. Verify the truth tables of each flip flop
62
LAB MANUAL
Circuit diagrams:
SR flip flop clocked version:
63

S
1 2
LAB MANUAL
1 2
CLK PULSE
1 3 2
Q'
Truth table for SR flip flop:
Input S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1
Present state Qn 0 1 0 1 0 1 0 1
Next state Qn+1 0 1 0 0 1 1 X X
Truth table (characteristic table) for clocked SR flip flop:
R 0
Inputs S 0
CLK
64
Outputs Q Q0

0 1 1 1 0 1
1 0 Indeterminate
LAB MANUAL
Symbol of Clocked SR flip flop:
S S R c l k R f l i p f l o p
Q '
D flip flop: Logic Symbol:
D D c l k f l i p f l o p
Q '
Logic diagram for D flip flop:
65

14
1 2
LAB MANUAL
3 1 2
14
CP
1 3 2
14
Q'
Truth table (characteristic) for D flip flop:
Inputs Preset 0 1 0 1 1 1
Clear 1 0 0 1 1 1
Clock X X X 0
D X X X 1 0 X
Outputs Q 1 0 1 1 0 Q0
Q1 0 1 1 0 1 Q01
JK flip flop:
66
LAB MANUAL
Logic symbol:
J J K C P f l i p f l o p
Q '
Logic diagram for JK flip flop:
K C P
4 5
4 2 5 5
Q '
Truth table (characteristic) for JK flip flop:

67
LAB MANUAL
Preset 0 1 0 1 1 1 1 1
Clear 1 0 0 1 1 1 1 1
Clock X X X 1
J X X X 0 1 0 1 X
K X X X 0 0 1 1 X Q 1 0 1* Q0 1 0
Outputs Q1 0 1 1* Q01 0 1 Toggle Q0 Q01
Note: *Unstable condition. It will not remain after Cn and Pn inputs return to their inactive (high) state
Truth table for JK flip flop:
Inputs J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1
Outputs Qn+1 0 0 0 0 1 1 1 0
T flip flop:
68

Logic symbol:
LAB MANUAL
T C P
f l i p
f l o p
Q '
Logic diagram for T flip flop:
T C P
4 2 5 5 4 2
4 4 2 5 5 2
Q '
Characteristic table for T flip flop:
Preset 0 1 0 1 1 1
Inputs Clear Clock 1 X 0 X 0 X 1 1 1 0
Outputs T X X X 1 0 X Q 1 0 1 TOGGLE 1 TOGGLE 0 Q1 0 1 1
Truth table for T flip flop:
69

Inputs T 0 0 1 1 Outputs Qn 0 1 0 1 Qn+1 0 1 1 0
LAB MANUAL
Master slave Jk flip flop: Logic diagram for M/S JK flip flop:
1 2 3 1 2 3 1 2 3 1 2 3
C P
1
C P
1 2 3 1 3 2
1 2
Q '
Characteristic table for M/S JK flip flop:
Inputs J 0 0 1 1 K 0 1 0 1
output Q No change 0 1 Qn1
Questions: 1.Difference between latch and flip-flop. 2.List the applications of flip-flops.
70
3.Explain the operation of JK master slave flip-flop. 4.What is the difference between SR-flip flop and clocked SR-FF. 5.What is ment by level triggering and edge triggering in flip-flops. 6. Explain the difference between +ve edge and ve edge triggering. 7. Which type of edge triggering is used in IC 7476 J-K M/S Flip-flop? 8. Explain the preset and clear inputs of a flip-flop and why are these Called asynchronous inputs. 9. What is ment by toggle and where do the T-FFs are used. 10. Where do the D-FFs are used and why it is called a delay flip flop. 11. Explain the race around problem in JK-FF and how it is eliminated in master slave JK- FF.
LAB MANUAL
71

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PULSE & DIGITAL CIRCUITS

Department of Electronics and Communication Engineering

PULSE AND DIGITAL CIRCUITS LAB

PULSE & DIGITAL CIRCUITS

1. LINEAR WAVE SHAPING

Circuit diagram: High Pass Filter:

PULSE & DIGITAL CIRCUITS

= > d/dt(Vo)=d/dt(Vi) - 1/RC

1+e T/2RC =1.51 v % tilt =2 (V1-V1)/V =(2.49-1.51)/2 = 49% Model Graph:

T1=T2=T/2 b) RC >> T Choose RC = 10T = 1 m Sec

PULSE & DIGITAL CIRCUITS

b) RC << T RC = 0.1 T R= (0.1x 10 -4)/(0.1x10 -6) Model Graph:

PULSE & DIGITAL CIRCUITS

Low Pass Filter: Circuit Diagram:

i.e; R,C are fixed magnitude .

PULSE & DIGITAL CIRCUITS

RC >> T R = 10 K, C = 0.1 f V2=V(e T/2RC -1) /2 (e T/2RC +1) =0.05V

V1=0.05V Model Graph:

(c) RC << T R = 100,

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS

2. NON-LINEAR WAVE SHAPING CIRCUITS - CLIPPERS

Circuit Diagram Series Diode Clipper:Shunt Diode Clipper:

PULSE & DIGITAL CIRCUITS

LAB MANUAL Shunt Diode Clipper with Bias

PULSE & DIGITAL CIRCUITS

8. Repeat the above steps for all the circuit.

Model Graph: Input Wave Form

Out put wave form for Series Diode Clipper:

Out put wave form for Shunt Diode Clipper:

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS

3. NON-LINEAR WAVE SHAPING CIRCUITS - CLAMPERS

Specification 100k 1N4007 0.1f

PULSE & DIGITAL CIRCUITS

Dual Regulated Power supply

Circuit Diagrams: Negative Clamper

Biased Ve clamper (-Vr)

Biased +Ve Clamper:

PULSE & DIGITAL CIRCUITS

Out put wave forms for ve Clamper:

Out put wave forms for +ve Clamper:

PULSE & DIGITAL CIRCUITS

Biased +Ve Clamper:

Specification 1k 8.2k BC 107

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS

RB= 7 K ohms (choose practical values as 8.2 K )

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS

Name of the component Resistors

Specification 1k 72k 724k 7.2k BC 107

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS 6.MONOSTABLE MULTIVIBRATOR

PULSE & DIGITAL CIRCUITS

PULSE & DIGITAL CIRCUITS