(Updated) Rajan Microprocessor Lab Manual-1 (16!11!2012)
(Updated) Rajan Microprocessor Lab Manual-1 (16!11!2012)
(Updated) Rajan Microprocessor Lab Manual-1 (16!11!2012)
SL.NO
CYCLE II
9 10 11 12 13 14 15
PROGRAM FOR STEPPER MOTOR INTERFACE USING 8085 MICROPROCESSOR PROGRAM FOR SERIAL COMMUNICATION USING 8085 MICROPROCESSOR PROGRAM FOR ELEVATOR SIMULATION USING 8085 MICROPROCESSOR PROGRAM FOR ADC INTERFACE USING 8085 MICROPROCESSOR PROGRAM FOR DAC INTERFACE USING 8085 MICROPROCESSOR PROGRAM FOR DC MOTOR INTERFACE USING 8085 MICROPROCESSOR PROGRAM FOR TRAFFIC LIGHTCONTROL INTERFACE 8085 MICROPROCESSOR
H.O.D
1
LAB INCHARGE
SYLLABUS
INTEL 8085 is one of the most popular 8-bit microprocessor capable of addressing 64 KB of memory and its architecture is simple. The device has 40 pins, requires +5 V power supply and can operate with 3MHz single phase clock.
ALU (Arithmetic Logic Unit): The 8085A has a simple 8-bit ALU and it works in coordination with the accumulator, temporary registers, 5 flags and arithmetic and logic circuits. ALU has the capability of performing several mathematical and logical operations. The temporary registers are used to hold the data during an arithmetic and logic operation. The result is stored in the accumulator and the flags are set or reset according to the result of the operation. The flags are affected by the arithmetic and logic operation. They are as follows: Sign flag After the execution of the arithmetic - logic operation if the bit D7 of the result is 1, the sign flag is set. This flag is used with signed numbers. If it is 1, it is a negative number and if it is 0, it is a positive number. Zero flag The zero flag is set if the ALU operation results in zero. This flag is modified by the result in the accumulator as well as in other registers. Auxillary carry flag In an arithmetic operation when a carry is generated by digit D3 and passed on to D4, the auxillary flag is set. Parity flag After arithmetic logic operation, if the result has an even number of 1s the flag is set. If it has odd number of 1s it is reset. Carry flag If an arithmetic operation results in a carry, the carry flag is set. The carry flag also serves as a borrow flag for subtraction.
Timing and control unit This unit synchronizes all the microprocessor operation with a clock and generates the control signals necessary for communication between the microprocessor and peripherals. The control signals RD (read) and WR (write) indicate the availability of data on the data bus.
Instruction register and decoder The instruction register and decoder are part of the ALU. When an instruction is fetched from memory it is loaded in the instruction register. The decoder decodes the instruction and establishes the sequence of events to follow.
Register array The 8085 has six general purpose registers to store 8-bit data during program execution. These registers are identified as B, C, D, E, H and L. they can be combined as BC, DE and HL to perform 16-bit operation.
Accumulator Accumulator is an 8-bit register that is part of the ALU. This register is used to store 8bit data and to perform arithmetic and logic operation. The result of an operation is stored in the accumulator.
Program counter The program counter is a 16-bit register used to point to the memory address of the next instruction to be executed.
Stack pointer It is a 16-bit register which points to the memory location in R/W memory, called the Stack.
Communication lines 8085 microprocessor performs data transfer operations using three
communication lines called buses. They are address bus, data bus and control bus. Address bus it is a group of 16-bit lines generally identified as A0 A15. The address bus is unidirectional i.e., the bits flow in one direction from microprocessor to the peripheral devices. It is capable of addressing 2 16 memory locations. Data bus it is a group of 8 lines used for data flow and it is bidirectional. The data ranges from 00 FF. Control bus it consist of various single lines that carry synchronizing signals. The microprocessor uses such signals for timing purpose.
START
CLEAR CREGISTER
INCREMENT HL PAIR
STOP
10
EXPT. NO.2- PROGRAM FOR 8 BIT ARITHMETIC OPERATIONS WITH 8085 MICROPROCESSOR
AIM: To Perform 8-bit arithmetic operations using 8085 Microprocessor i) 8 bit addition iv) 8 bit division ii) 8 bit subtraction iii) 8 bit Multiplication
i) 8- BIT ADDITION
ALGORITHM: 1. Load the address of the data memory in HL pair 2. Clear C-Register 3. Move the first data from memory to accumulator 4. Increment the pointer (HL pair) 5. Add the content of memory addressed by HL with accumulator 6. Check for carry if carry=1, go to step7 or if carry=0 , go to step8 7. Increment the C-Register 8. Increment the pointer and Store the sum 9. Increment the pointer and store the carry 10. Stop the process. ADDRESS 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 11 MOV INX ADD JNC A,M H M LOOP1 MVI C, 00H LABEL MNEMONIC LXI OPERAND H, 4900 OPCODE COMMENTS
START
STOP
12
C H M,A H M,C
ii)
8- BIT SUBTRACTION
ALGORITHM: 1. Load the subtrahend (the data to be subtracted) from memory to accumulator and move it to B-register 2. Load the minuend from memory to accumulator 3. Subtract the content of B-register (subtrahend) from the content of accumulator(minuend) 4. Store the difference (accumulator) in memory 5. Stop the process.
ADDRESS 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 400B
LABEL
MNEMONIC LDA
OPERAND 4201
OPCODE
COMMENT
MOV LDA
B,A 4202
SUB STA
B 4203
HLT
13
START
USING HL AS ADDRESS POINTER GET IDATA IN B-REGISTER AND II-DATA IN C-REGISTER ADD THE CONTENT OF CREGISTER TO A-REGISTER
DECREMENT B-REGISTER
STOP
14
iii)
8- BIT MULTIPLICATION
ALGORITHM: 1. Load the address of the first data in HL pair(pointer) 2. Move the first data to B-register (count) 3. Increment the pointer 4. Move the record data to D-register (multiplicand) 5. Add the content of D-register to accumulator 6. Decrement B-register (count) 7. Check whether count has reached zero, if ZF=0 repeat step5 through 7, or if ZF=1 go to next step. 8. Store the result in memory 9. Stop the process. ADDRESS 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 400B 400C 400D 400E 400F HLT STA 4902 LOOP1 MOV INX MOV XRA ADD DCR JNZ B,M H C,M A C B LOOP1 LABEL MNEMONIC LXI OPCODE H,4900 OPCODE COMMENTS
15
START
CHECK WHETHER CY=0 NO SUBTRACT CONTENT OF BREG FROM A-REG INCREMENT QUOTIENT (C-REGISTER)
YES
MOVE THE CONTENT OF C-REGISTER TO A-REGISTER AND STORE QUOTIENT IN MEMORY STOP 16
5. Subtract the content of B-register from accumulator 6. Increment the content of C-register (quotient) 7. Go to step4 8. Store the content of accumulator (reminder) in memory 9. Move the content of C-register (quotient) to accumulator and store in memory 10. Stop the process. ADDRESS 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 400B 400C 400D 400E 400F 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 HLT MOV STA A,C 4202H STORE STA 4203H SUB INR JMP B C AGAIN AGAIN CMP JC B STORE MVI C,00H MOV LDA B,A 4200H LABEL MNEMONIC OPERAND OPCODE COMMENTS LDA 4201H
17
ADDRESS
ADDRESS
OBSERVATION - 8 BIT SUBTRACTION INPUT ADDRESS DATA 1 DATA 2 OUTPUT ADDRESS DATA 1 DATA 2
ADDRESS
ADDRESS
ADDRESS
ADDRESS
18
RESULT: Thus the 8-Bit ALP programs were executed and the results also verified by using 8085 Microprocessor
19
START
[L][4050H] [H][4051H]
[DE][HL]
[L][4052H] [H][4053H]
[A]00H
[HL][HL]+ [DE]
IS THERE A CARRY
NO
[A][A]+1
YES
[4054][L]
[4055][H]
[4056][A]
STOP 20
i)
16- BIT ADDITION LABEL MNEMONIC OPERAND LHLD 4200H OPCODE COMMENTS
ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108
XRA DAD
A D 21
START
[L][4050H] [H][4051H]
[DE][HL]
[L][4052H] [H][4053H]
[HL][HL]- [DE]
IS THERE A BORROW
NO
[C][C]+1
YES
[4054][L]
[4055][H]
[4056][L]
STOP 22
4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 AHEAD
JNC
AHEAD
INR SHLD
A 4202H
STA
4206H
HLT
PROGRAM FOR 16- BIT SUBTRACTION ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B LDA 4203H SUB STA B 4204H MOV LDA B,A 4200H LABEL MNEMONIC OPERAND LDA 4202H OPCODE COMMENTS
23
START
[L][4200H] [H][4201H]
[BC][BC]+1 [DE][DE]+1
NO
[4204][L] [4205][H]
410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 HLT SUB STA B 4205H MOV LDA B,A 4201H
PROGRAM FOR16- BIT MULTIPLICATION ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 25 XCHG LXI H,0000H SPHL LHLD 4202 LABEL MNEMONIC OPERAND LHLD 4200H OPCODE COMMENTS
START A [L][4200H] [H][4201H] [L][4054] [H][4055] HL [DE] AC [L][4050H] [H][4051H] [4056]A BC0000H AB AL: AAE: LA AH: AA-H-Br: HA
[4057]A
STOP
[BC][BC]+1
[BC][BC]-1 HLHL+DE
A 26
410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 HLT MOV MOV SHLD L,C H,B 4206H SHLD 4204H AHEAD INX DCX MOV ORA JNZ B D A,E D NEXT NEXT DAD JNC SP AHEAD LXI B,0000H
OBSERVATION - 16 BIT ADDITION INPUT ADDRESS DATA 1 DATA 2 OUTPUT ADDRESS DATA 1 DATA 2
OBSERVATION - 16 BIT SUBTRACTION INPUT ADDRESS DATA 1 DATA 2 OUTPUT ADDRESS DATA 1 DATA 2
OBSERVATION - 16 BIT MULTIPLICATION INPUT ADDRESS DATA 1 DATA 2 OUTPUT ADDRESS DATA 1 DATA 2
ADDRESS
ADDRESS
28
PROGRAM FOR16- BIT DIVISION ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E MOV STA A,B 4057 29 MOV STA A,C 4056 DCX DAD SHLD B D 4054 LOOP MOV SUB MOV MOV SBB MOV INX JNC A,L E L,A A,H D H,A B LOOP LXI B,0000H XCHG LHLD 4050 LABEL START MNEMONIC OPERAND LHLD 4052 OPCODE COMMENTS
30
RESULT Thus the 16-Bit ALPs were performed and the outputs also verified by using 8085.
31
ADD THE CONTENT OF B-REGISTER TO A-REGISTER AND PERFORM DECIMAL ADJUST AFTER ADDITION
NO
STOP
32
33
START A GET THE LOW ORDER 2DIGITS OF I-DATA IN A & MOVE IT TO B STORE THE SUM IN MEMORY GET THE LOW ORDER 2 DIGITS OF II-DATA IN A-REGISTER MOVE THE CONTENT OF CREGISTER TO A-REGISTER AND STORE IN MEMORY
ADD THE CONTENT OF B TO A AND PERFORM DAA STORE THE RESULT IN MEMORY STOP GET THE HIGH ORDER 2DIGITS OF I-DATA IN A & MOVE IT TO B
YES
INCREMENT C-REGISTER
34
410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 HLT MOV STA A,C 4203H AHEAD INR STA C 4202H
(ii) 16-bit BCD Addition ALGORITHM 1. Load the low order two digits of first data in accumulator and move it to Bregister 2. Load the low order two digits of second data in accumulator 3. Clear C-register for storing carry 4. Add the content of B-register to accumulator 5. Execute DAA register 6. Store the low order two digits of the result in memory 7. Load the high order two digits of first data in accumulator and move it to Bregister 8. Load the high order two digits of second data in accumulator 9. Add the content of B-register and carry to accumulator 10. Execute DAA instruction 11. Check for carry, if carry=1, go to step 12 or if carry =0 go to step 13 12. Increment C-register to account for final carry 13. Store the high order two digits of the result in memory 14. Move the carry (contents of C-register) to accumulator and store in memory 15. Stop PROGRAM: 16-BIT BCD ADDITION ADDRESS 4100 4101 4102 4103 4104 4105 35 MOV LDA B,A 4202H LABEL MNEMONIC OPERAND LDA 4200H OPCODE COMMENTS
START
PERFORM THE SUBTRACTION OF LOW BYTE AND STORE THE RESULT IN MEMORY
STOP
36
4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 HLT AHEAD INR MOV STA C A,C 4206H JNC AHEAD ADC DAA STA 4205H B MOV LDA B,A 4203H LDA 4201H ADD DAA STA 4204H B MVI C,00H
(iii) 8-bit BCD subtraction ALGORITHM 1. Load the Subtrahend in accumulator and move it to B-register 2. Move 99 to accumulator and subtract the content of B-register from accumulator 37
OBSERVATION
(i) 8-BIT BCD ADDITION
OUTPUT DATA
OUTPUT DATA
OUTPUT DATA
38
3. 4. 5. 6. 7. 8. 9.
Increment the accumulator Move the content of accumulator to B-register Load the minuend in accumulator Add the content of B-register to accumulator Execute DAA instruction Store the result in memory Stop
PROGRAM: 8-BIT BCD SUBTRACTION ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 HLT ADD DAA STA 4202H B SUB INR MOV LDA B A B,A 4200H MOV MVI B,A A,99H LABEL MNEMONIC OPERAND LDA 4201H OPCODE COMMENTS
Result Thus the BCD ALPs were performed and the outputs also verified by using 8085.
39
START
MOVE THE CONTENT IN M-REG. TO A-REG. STORE THE RESULT IN DE REG. PAIR
DECREMENT C-REGISTER
YES
40
1. Microprocessor kit
2. Power supply (+5V) 3. Op-code sheet
OPCODE
COMMENTS
MOVE THE CONTENT IN M-REG. TO A-REG. STORE THE RESULT IN DE REG. PAIR
DECREMENT C-REGISTER
YES
42
JNZ
L1
HLT
43
OBSERVATION
(i) TRANSFER CONTENTS TO OVERLAPPING MEMORY BLOCKS
OUTPUT DATA
(ii)
OUTPUT DATA
44
RESULT
Thus the block operation (overlapping & non-overlapping) by using 8085 microprocessor were verified and the output also verified. 45
46
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet ALGORITHM (HEXA DECIMAL TO ASCII) 1. Load the given data in A-register and move to B-register 2. Mark the upper nibble of the binary(hexa)data in A-register 3. Call subroutine SUB1 to get ASCII code of the lower nibble and store in memory 4. Move B-register to A-register and mask the lower nibble 5. Rotate the upper nibble to lower nibble position 6. Call subroutine SUB1 to get the ASCII code of upper nibble and store in memory 7. Stop 8. Compare the content of A-register with 0A 9. If CY=1, go to step11. If CY=0, go to next step. 10. Add 07H to A-register 11. Add 30H to A-register 12. Return to main program ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 47 CALL SUB MOV ANI B,A 0F LABEL MNEMONIC LDA OPERAND 4200 OPCODE COMMENTS
START
CALL SUBROUTINE SUB1 TO GET THE ASCII CODE FOR LOWER NIBBLE IN AREGISTER STORE ASCII CODE (A-REGISTER) IN MEMORY
MOVE HEXA DATA FROM B-REGISTER TO AREGISTER AND MASK THE LOWER NIBBLE
CALL SUBROUTINE SUB 1 TO GET THE ASCII COE FOR UPPER NIBBLE IN AREGISTER STORE THE ASCII CODE (A-REGISTER) IN MEMORY
STOP
48
4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 SKIP SUB 1
STA
4201
MOV ANI
A,B F0
STA
4202
HLT CPI 0A
JC
SKIP
ADI
07
ADI
30
RET
ALGORITHM (ASCII to HEXA DECIMAL) 1. Start the process. 2. Get the ASCII code number in the accumulator through memory. 49
START
NO
50
3. 4. 5. 6. 7.
Subtract 30 from the ASCII code number. If the different is less than 0A go to step 6 If not, subtract 07 from first difference value. Store the difference in the specified memory location. Stop the process. LABEL MNEMONIC LDA OPERAND 4500 OPCODE COMMENTS
ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F
SUI
30
CPI
0A
JC
SUI
07
STA
4501
HLT
ALGORITHM (BINARY TO BCD CODE CONVERSION) 1. Load the given data in A-register 2. Move the immediate data of 64H in B-register 3. Move the immediate data of 0AH in C-register 4. Move the immediate data of 00H in D-register 5. Move the immediate data of 00H in E-register 6. Compare B-register with accumulator 7. If CY=0 go to next step else go to step11 8. Subtract the content of B-register with A-register 9. Increment the E-register 10. Jump to the step6 11. Compare C with A-register 12. If CY=0 then go to next step else store the result in memory 13. Increment D-register 14. Then jump to step11 15. Store the result in memory 16. Move the content of d-register to A-register 51
START
NO
YES
STOP
52
17. Store the result in memory 18. Move the content of E-register to A-register 19. Store the result in memory 20. Stop the process ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 53 SUB INR JMP C D L2 L2 CMP JC C L3 SUB INR JMP B E L1 L1 CMP JC B L2 MVI E,00H MVI D,00H MVI C,0AH MVI B,64H LABEL MNEMONIC LDA OPERAND 4200 OPCODE COMMENTS
START
IF CHECK CY=1 NO
YES
B 54
411C 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 HLT MOV STA A,E 4203 MOV STA A,D 4202 L3 STA 4201
BCD TO BINARY CONVERSION Load the given data in A-register Move the content of A-register to B-register Mask the upper nibble of the binary data in A-register Move the content of A-register to C-register Move the content of B-register to A-register Mask the lower nibble of the binary data in A-register Rotate the upper nibble to lower nibble position Move the content of A-register to B-register Move the immediate data of 00H to A-register Move the immediate data of 00H to D-register Add the content of D-register with A-register Decrement the B-register If zero flag is set then proceed to next step else go to step 11 Add the content of C-register with A-register Store the result in memory Stop LABEL MNEMONIC LDA OPERAND 4200 OPCODE COMMENTS
MOV
B,A 55
CHECK IF, CY=1 NO SUBTRACT C-REGISTER WITH A-REGISTER INCREMENT D-REGISTER JUMP
YES
STORE THE RESULT IN MEMORY MOVE D-REGISTER TO A-REGISTER STORE THE RESULT IN MEMORY MOVE E-REGISTER WITH A-REGISTER
STOP
56
4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C L1
ANI
OF
C,A A,B OF
MVI
D,0A
D B L1
ADD STA
C 4102
HLT
57
INPUT OUTPUT INPUT OUTPUT ADDRESS DATA ADDRESS DATA ADDRESS DATA ADDRESS DATA
OBSERVATION - BINARY TO BCD CODE CONVERSION INPUT DATA 1 DATA 2 OUTPUT DATA 1 DATA 2
ADDRESS
ADDRESS
OBSERVATION - BCD TO BINARY CODE CONVERSION INPUT ADDRESS DATA 1 DATA 2 OUTPUT ADDRESS DATA 1 DATA 2
58
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet ALGORITHM 1. Initialize HL pair as memory pointer 2. Get the count at 4200 into C-register 3. Copy it in D-register 4. Get the first value in A-register 5. Compare it with the value at next location 6. If they are out of order, exchange the contents of A-register and memory 7. Decrement D-register content by 1 8. Repeat step 5&7 until the value of D-register becomes zero 9. Decrement C-register content by 1 10. Repeat steps 3 to 9 till the value in C-register becomes zero 11. Stop the process
LABEL
OPCODE
COMMENTS
59
OBSERVATION Sorting (Ascending order) INPUT (Array size-5) ADDRESS DATA OUTPUT (Array size-5) ADDRESS DATA
60
4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 SKIP
LOOP
LXI MOV INX CMP JC MOV MOV DCX MOV INX DCR JNZ DCR JNZ HLT
RESULT Thus the sorting (Ascending) was and executed and output also verified by using 8085 microprocessor.
61
OBSERVATION Sorting (Descending order) INPUT (Array size-5) ADDRESS DATA OUTPUT (Array size-5) ADDRESS DATA
62
MICROPROCESSOR
AIM:
To write a program to arrange an array of data in descending order using 8085 microprocessor
APPARATUS REQUIRED:
ALGORITHM 1. Initialize HL pair as memory pointer 2. Get the count at 4200 into C-register 3. Copy it in D-register 4. Get the first value in A-register 5. Compare it with the value at next location 6. If they are out of order, exchange the contents of A-register and memory 7. Decrement D-register content by 1 8. Repeat step 5&7 until the value of D-register becomes zero 9. Decrement C-register content by 1 10. Repeat steps 3 to 9 till the value in C-register becomes zero 11. Stop the process PROGRAM ADDRESS 4100 4101 4102 4103
REPEAT
LABEL
OPCODE
COMMENTS
63
64
4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 SKIP
LOOP
LXI MOV INX CMP JNC MOV MOV DCX MOV INX DCR JNZ DCR JNZ HLT
RESULT Thus the sorting (Descending) was and executed and output also verified by using 8085 microprocessor.
65
OBSERVATION - LARGEST NUMBER INPUT ADDRESS DATA 1 DATA 2 OUTPUT ADDRESS DATA 1 DATA 2
66
PROGRAM ADDRESS LABEL MNEMONICS 4300 LXI H 4200 4301 4302 4303 MOV B , M 4304 MVI A , 00 4305 4306 XXX INX H 4307 CMP M 4308 JNC YYY 4309 430A 430B MOV A , M 430C YYY DCR B 430D JNZ XXX 430E 430F 4310 STA 4500 4311 4312 4313 HLT OP CODE COMMENTS
67
ADDRESS
ADDRESS
68
(ii) 1. 2. 3. 4. 5. 6.
Start the process. Initialize memory for getting array of element(data) Get the block size in any register through accumulator from memory. Initialize accumulator to FF. Compare accumulator content with array element. Check for carry. If there is no carry, copy the memory content (smallest number) to accumulator. 7. Increment the memory pointer & Decrement the count. 8. Check for zero. If there is no zero go to step5. 9. Store accumulator content (smallest t no) in the specified memory location. 10. Stop the process. PROGRAM ADDRESS LABEL MNEMONICS 4400 LXI H , 4200 4401 4402 4403 MOV B , M 4404 MVI A , FF 4405 4406 XYZ INX H 4407 CMP M 4408 JC CCC 4409 440A 440B MOV A , M 440C CCC DCR B 440D JNZ XYZ 440E 440F 4410 STA 4201 4411 4412 4413 HLT OP CODE COMMENTS
RESULT
Thus the array operation was and executed and output also verified by using 8085 microprocessor.
69
70
(i)
16-bit addition
ALGORITHM
1. 2. 3. 4. 5. Move the content of memory location to AX register Move the content of memory location to BX register Add the content of AX with BX Move the content of AX register to memory location 1204 stop
PROGRAM
MOV AX, [1200] MOV BX, [1202] ADD AX, BX MOV [1204], AX HLT
(ii)
16-bit subtraction
ALGORITHM
1. 2. 3. 4. 5. Move the content of memory location to AX register Move the content of memory location to BX register Subtract the content of BX with AX Move the result in memory stop
PROGRAM
MOV AX, [1200] MOV BX, [1202] SUB AX, BX MOV [1204], AX HLT 71
START
STOP
72
(iii)
16-bit subtraction
ALGORITHM
6. Move the content of memory location to AX register 7. Move the content of memory location to BX register 8. Subtract the content of BX with AX 9. Move the result in memory 10. stop
PROGRAM
MOV AX, [1200] MOV BX, [1202] SUB AX, BX MOV [1204], AX HLT
73
START
STOP
74
(iv)
16-bit Multiplication
ALGORITHM
1. 2. 3. 4. 5. Move the content of memory location to AX register Move the content of memory location to BX register Multiply BX with Accumulator Move the result in memory stop
PROGRAM
MOV AX, [1200] MOV BX, [1202] SUB AX, BX MOV [1204], AX HLT
75
START
STOP
76
(v)
16-bit Division
ALGORITHM
1. 2. 3. 4. 5. Move the content of memory location to AX register Move the content of memory location to BX register Divide the content of BX with AX Move the content of AX register to memory stop
PROGRAM
MOV AX, [1200] MOV BX, [1202] DIV BX MOV [1204], AX HLT
Result
Thus the 16-but arithmetic operations was executed using 8086 microprocessor
77
START
STOP
78
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Stepper motor 4. Op-code sheet
Program
ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C DELAY NOP DCX D LXI D,0303H
REPEAT
LABEL START
MNEMONIC LXI
OPERAND
H, LOOK UP
OPCODE
COMMENTS
MVI
B,04,H
MOV OUT
A,M 0C0H
79
80
410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D
LOOK UP
A,E D DELAY
H B REPEAT
JMP
START
DB
09 05 06 0A
RESULT Thus the serial communication was performed by using 8085 microprocessor.
81
82
APPARATUS REQUIRED:
1. Microprocessor kit
2. Power supply (+5V) 3. Op-code sheet PROGRAM: ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F OUT 0C2H MVI A,4E OUT 0C8H MVI A,4E OUT 0C8H MVI A,0A OUT 0CEH LABEL START MNEMONIC MVI OPERAND A,36 OPCODE COMMENTS
83
84
4110 4111 4112 4113 4114 4115 4116 4117 4118 ADDRESS 4200 4201 4202 4203 4204 4205 LABEL
MVI
A,37
OUT
0C2H
MVI
A,41
OUT
0C0H
RST MNEMONIC IN
STA
4150
32 50 41
RST
CF
Result Thus the serial communication was performed by using 8085 microprocessor.
85
86
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet 4. Interface UBMB-022
Program
ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E OUT LIFT 1 MVI A,80H OUT STAT_OU MVI A,02 CALL DELAY OUT STAT_OU LABEL START MNEMONIC MVI OPERAND A,03 OPCODE COMMENTS
87
88
411F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F
MVI
A,01
OUT
LIFT 2
CALL
DELAY
MVI
A,40H
OUT
LIFT 1
CALL
DELAY
MVI
A,20H
OUT
LIFT1
CALL
DELAY
MVI
A,10H
OUT
LIFT1
CALL
DELAY
MVI
A,08H
OUT
LIFT1
MVI
A,0BH 89
90
4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 413A 413B 413C 413D 413E 413F 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 414A RET DCR JNC LOOP2 DCX MOV ORA JNZ LOOP1 LXI DELAY HLT MVI OUT STAT_OU MVI A,03H CALL DELAY OUT STAT_OU
Result Thus the output for elevator simulation is obtained and it was verified
91
C0 C4 C8 CC
DATA 80 40 20 10 08 04 02 01
LIFT POSITION GROUND FLOOR I-FLOOR II-FLOOR III-FLOOR IV-FLOOR V-FLOOR VI-FLOOR VII-FLOOR
92
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 OUT 0D0H XRA XRA XRA MVI A A A A,00 OUT 0D0H MVI A,01 OUT 0C8H MVI A,18 OUT 0C8H LABEL START MNEMONIC MVI OPERAND A,10 OPCODE COMMENTS
93
94
4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121
LOP
IN
0D8H
ANI
01
CPI
01
JNZ
LOP
IN
0C0H
STA
4150H
HLT
Procedure 1. Place the jumper J2 in A Position 2. Place the jumper J5 in A position 3. Enter and execute the program 4. Vary the analog input(using trim pot) and verify the digital data displayed with that data stored in memory location 4150h
Result Thus the digital data obtained from the given analog signal was verified using 8085
95
OBSERVATION ADC Interfacing using 8085 INPUT MSB LSB ADDRESS OUTPUT DATA
96
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 DELAY MVI B,05 JMP START CALL DELAY OUT 0C9H MVI A,0FF CALL DELAY OUT 0C8H LABEL START MNEMONIC MVI OPERAND A,00 OPCODE COMMENTS
97
98
4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D
L1
MVI
C,0FF
L2
DCR JNZ
C L2
DCR JNZ
B L1
RET
RESULT Thus the square wave at the DAC2 out put was generated using 8085
99
OBSERVATION ADC Interfacing using 8085 INPUT MSB LSB ADDRESS OUTPUT DATA
100
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet PROGRAM ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 OUT 0C8H MVI A,0FFH OUT 0CEH MVI A,30H CALL DELAY OUT 0D8H MVI A,00 OUT 0C0H LABEL MNEMONIC MVI OPERAND A,0FFH OPCODE COMMENTS
101
102
4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F 4130 4131 LOOP LO2 DELAY
OUT
0C8H
MVI
A,00
OUT
0D0H
CALL
DELAY
MVI
A,00
OUT
0D8H
IN
0C8H
STA
4500
MVI
A,00
STA
45H
LXI
H,0A3C3H
DCX MOV
H A,L
103
104
ORA JNZ
H LOOP
DCR JNZ
C LO2
RET
105
106
APPARATUS REQUIRED: 1. Microprocessor kit 2. Power supply (+5V) 3. Op-code sheet 4. Traffic Light controller interface
Program:
ADDRESS 4100 4102 4104 4107 410A 410D 410E 410F 4111 4114 4115 4116 4117 411A 411B 411C 411E
REPEAT
LABEL START
MNEMONIC MVI OUT LXI LXI CALL XCHG MOV OUT CALL XCHG INX INX CALL XCHG MOV OUT CALL
OPERAND A,80H
CONTRL
H,DATA_SQ
OPCODE
COMMENTS
D,DATA_E OUT
D H OUT
A,M PORT B
DELAY 1
107
108
4121 4122 4123 4124 4127 4128 4129 412B 412E 412F 4130 4131 4134 4135 4136 4138 4139 413A 413C 413F 4142 4143 4145 4146 4147 4149 414A 414B 414D 4150 4151 DELAY OUT
XCHG INX INX CALL XCHG MOV OUT CALL XCHG INX INX CALL XCHG MOV OUT INX MOV OUT CALL JMP MOV OUT INX MOV OUT INX MOV OUT CALL RET PUSH A,M PORT C H A,M PORT A DELAY 1 REPEAT A,M PORT B H A,M PORT B H D H OUT A,M PORT C
DELAY 1
D H OUT
109
110
4152 4155 4158 4159 415A 415B 415E 415F 4160 4161 4164 4165 4166 4167 416A 416D 416E 416F 4170 4173 4174 4175 4176 4179 417A 417B 4180 4185 4187 418C RESULT L2 LOOP2
DELAY1
LXI L1 LOOP LXI DCX MOV ORA JNZ DCX MOV ORA JNZ POP RET PUSH LXI LXI DCX MOV ORA JNZ DCX MOV ORA JNZ POP RET
H,0001FFH
DATA_EDB
END
Thus the traffic light controller was performed using 8085 microprocessor and the output was verified. 111
112
113