PAL16R8 Family 20-Pin TTL Programmable Array Logic
PAL16R8 Family 20-Pin TTL Programmable Array Logic
PAL16R8 Family 20-Pin TTL Programmable Array Logic
PAL16R8 Family
20-Pin TTL Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s As fast as 4.5 ns maximum propagation delay s Popular 20-pin architectures: 16L8, 16R8, 16R6, 16R4 s Programmable replacement for high-speed TTL logic s Register preload for testability s Power-up reset for initialization
s Extensive third-party software and programmer support through FusionPLD partners s 20-Pin DIP and PLCC packages save space s 28-Pin PLCC-4 package provides ultra-clean high-speed signals
GENERAL DESCRIPTION
The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6, PAL16R4) includes the PAL16R8-5/4 Series which provides the highest speed in the 20-pin TTL PAL device family, making the series ideal for high-performance applications. The PAL16R8 Family is provided with standard 20-pin DIP and PLCC pinouts and a 28-pin PLCC pinout. The 28-pin PLCC pinout contains seven extra ground pins interleaved between the outputs to reduce noise and increase speed. The devices provide user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the following options: Variable input/output pin ratio Programmable three-state outputs Registers with feedback Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Unused input pins should be tied to VCC or GND. The entire PAL device family is supported by the FusionPLD partners. The PAL family is programmed on conventional PAL device programmers with appropriate personality and socket adapter modules. Once the PAL device is programmed and verified, an additional connection may be opened to prevent pattern readout. This feature secures proprietary circuits.
Amendment /0
2-3
AMD
BLOCK DIAGRAMS
PAL16L8
INPUTS
10
O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
O8 16492D-1
PAL16R8
CLK INPUTS OE
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
O1
O2
O3
O4
O5
O6
O7
O8 16492D-2
2-4
PAL16R8 Family
AMD
BLOCK DIAGRAMS
PAL16R6
CLK INPUTS OE
D Q
D Q
D Q
D Q
D Q
D Q
I/O1
O2
O3
O4
O5
O6
O7
I/O8
16492D-3
CLK
PAL16R4
OE
D Q
D Q
D Q
D Q
I/O1
I/O2
O3
O4
O5
O6
I/O7
I/O8
16492D-4
PAL16R8 Family
2-5
AMD
20-Pin PLCC
(Note 10) (Note 1) 1
I2
3 I3 I4 I5 I6 I7 4 5 6 7 8
I1
(Note 10)
VCC
28-Pin PLCC
VCC I6 I7 I5 I4 I3 I2
16492D-6
PIN DESIGNATIONS
CLK GND I I/O O OE VCC
Note: Pin 1 is marked for orientation.
16492D-7
= = = = = = =
Note 1 2 3 4 5 6 7 8 9 10
16R8 CLK OE O1 O2 O3 O4 O5 O6 O7 O8
2-6
PAL16R8 Family
AMD
FAMILY TYPE PAL = Programmable Array Logic NUMBER OF ARRAY INPUTS OUTPUT TYPE R = Registered L = Active-Low Combinatorial NUMBER OF OUTPUTS SPEED -4 = 4.5 ns tPD -5 = 5 ns tPD -7 = 7.5 ns tPD D = 10 ns tPD VERSION Blank = First Revision /2 = Second Revision
OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial (0C to +75C) PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) 28-Pin Plastic Leaded Chip Carrier for -4 (PL 028) D = 20-Pin Ceramic DIP (CD 020)
Valid Combinations PAL16L8 PAL16R8 PAL16R6 PAL16R4 PAL16L8-7 PAL16R8-7 PAL16R6-7 PAL16R4-7 PAL16L8D/2 PAL16R8D/2 PAL16R6D/2 PAL16R4D/2 PC, JC PC, JC, DC -5PC, -5JC, -4JC
Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
2-7
AMD
PAL
16
R 8 B -2 C N
a. b. c.
FAMILY TYPE PAL = Programmable Array Logic NUMBER OF ARRAY INPUTS OUTPUT TYPE R = Registered L = Active-Low Combinatorial NUMBER OF OUTPUTS SPEED B = Very High Speed (15 ns35 ns tPD) A = High Speed (25 ns35 ns tPD)
i. h.
OPTIONAL PROCESSING Blank = Standard Processing PACKAGE TYPE N = 20-Pin Plastic DIP (PD 020) NL = 20-Pin Plastic Leaded Chip Carrier (PL 020) J = 20-Pin Ceramic DIP (CD 020) OPERATING CONDITIONS C = Commercial (0C to +75C)
d.
g.
f.
POWER Blank = Full Power (155 mA180 mA ICC) -2 = Half Power (80 mA90 mA ICC) -4 = Quarter Power (55 mA ICC)
Valid Combinations PAL16L8 PAL16R8 PAL16R6 PAL16R4 B, B-2, A, B-4 CN, CNL, CJ
Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
2-8
PAL16R8/B/B-2/A/B-4 (Coml)
AMD
Register Preload
The register on the AMD marked 16R8, 16R6, and 16R4 devices can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery.
Pinouts
The PAL16R8 Family is available in the standard 20-pin DIP and PLCC pinouts and the PAL16R8-4 Series is available in the new 28-pin PLCC pinout. The 28-pin PLCC pinout gives the designer the cleanest possible signal with only 4.5 ns delay. The PAL16R8-4 pinout has been designed to minimize the noise that can be generated by high-speed signals. Because of its inherently shorter leads, the PLCC package is the best package for use in high-speed designs. The short leads and multiple ground signals reduce the effective lead inductance, minimizing ground bounce. Placing the ground pins between the outputs optimizes the ground bounce protection, and also isolates the outputs from each other, eliminating cross-talk. This pinout can reduce the effective propagation delay by as much as 20% from a standard DIP pinout. Design files for PAL16R8-4 Series devices are written as if the device had a standard 20-pin DIP pinout for most design software packages.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL16R8 Family will be HIGH due to the active-low outputs. The VCC rise must be monotonic and the reset delay time is 1000 ns maximum.
Security Fuse
After programming and verification, a PAL16R8 Family design can be secured by programming the security fuse. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed.
Technology
The PAL16R8-5, -7 and D/2 are fabricated with AMDs oxide isolated bipolar process. The array connections are formed with highly reliable PtSi fuses. The PAL16R8B, B-2, A and B-4 series are fabricated with AMDs advanced trench-isolated bipolar process. The array connections are formed with proven TiW fuses for reliable operation. These processes reduce parasitic capacitances and minimum geometries to provide higher performance.
PAL16R8 Family
2-9
AMD
0 0
7 8
11 12
15 16
19 20
23 24
27 28
31
20 VCC (23)
19 O8
7
I1 2
(22) GND
(25)
(21) 18 I/O7
15
I2 3 (26)
(20)
GND
16
23
I3 4 (27)
GND
24
31
I4 5 (28)
VCC (1)
GND
32
(15)
15 I/O4 (14)
39
GND
I5 6 (2)
40
(13)
14 I/O3
47
I6 7 (3)
(12) GND
48
(11)
13 I/O2 (10)
55
I7 8
(4)
GND
56
(9)
12 O1 (8)
63
I8 9 (5)
11 I9 (7)
0
GND 10 (6)
7 8
11 12
15 16
19 20
23 24
27 28
31
16492D-8
2-10
PAL16R8 Family
AMD
0 0
7 8
11 12
15 16
19 20
23 24
27 28
31
20 VCC (23)
D Q
7
I1 2 (25)
19 O 8 (22)
GND
8
D Q
(21)
15
I2 3 (26)
18 O 7 (20)
GND
16
D Q
(19)
23
I3 4 (27)
17 O 6 (18)
GND
24
D Q
(17)
31
I4 5 (28)
16 O5 (16)
GND
32
D Q
(15)
15 O 4 (14)
VCC
(1)
39
I5 6 (2)
GND
40
D Q
(13)
14 O 3 (12)
47
I6 7 (3)
GND
48
D Q
(11)
55
I7 8 (4)
13 O 2 (10)
GND
56
D Q
(9)
12 O1 (8) 11 OE (7)
63
I8 9 (5)
0
GND 10 (6)
7 8
11 12
15 16
19 20
23 24
27 28
31
16492D-9
PAL16R8 Family
2-11
AMD
0 0
7 8
11 12
15 16
19 20
23 24
27 28
31
20 VCC (23)
7
I1 2 (25)
19 I/O8 (22)
GND
8
D Q
(21)
15
I2 3 (26)
18 O 7 (20)
GND
16
D Q
(19)
23
I3 4 (27)
17 O 6 (18)
GND
24
D Q
(17)
31
I4 5 (28)
VCC
(1)
16 O5 (16)
GND
32
D Q
(15)
15 O 4 (14)
39
I5 6 (2)
GND
40
D Q
(13)
14 O 3 (12)
47
I6 7 (3)
GND
48
D Q
(11)
13 O 2 (10)
55
I7 8 (4)
GND
56
(9)
12 I/O1 (8)
63
I8 9 (5)
11 OE (7)
0
GND 10 (6)
7 8
11 12
15 16
19 20
23 24
27 28
31
16492D-10
2-12
PAL16R8 Family
AMD
0 0
7 8
11 12
15 16
19 20
23 24
27 28
31
20 VCC (23)
19 I/O8 (22)
7
I1 2 (25)
GND
(21)
18 I/O7
(20)
15
I2 3 (26)
GND (19)
D Q
16
17 O6 (18)
23
I3 4 (27)
GND (17)
D Q
24
16 O5
(16) GND
31
I4 5 (28)
VCC
(15)
D Q
32
(1)
39
I5 6 (2)
15 O4 (14)
GND
40
D Q
(13)
14 O3 (12)
47
I6 7 (3)
GND (11)
13 I/O2 (10)
48
55
I7 8 (4)
GND
56
(9)
12 I/O1 (8)
63
I8 9 (5)
11 OE (7)
0
GND 10 (6)
7 8
11 12
15 16
19 20
23 24
27 28
31
16492D-11
PAL16R8 Family
2-13
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.7 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-14
PAL16R8-4/5 (Coml)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance CLK, OE I1I8 Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = 25C f = 1 MHz Typ 8 5 8 Unit
pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
-4 Max 5 Min (Note 3) 1 4.5 0 4.0 1 1 3.5 0.5 4 4 125 125 125 6.5 5 6.5 5 1 1 2 2 6.5 5 6.5 5 Max 4.5 Unit ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
fMAX
Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. Skew testing takes into account pattern and switching direction differences between outputs. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) tS.
PAL16R8-4/5 (Coml)
2-15
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.7 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-16
PAL16R8-7 (Coml)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = 25C f = 1 MHz Typ 5 8 Unit pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
Setup Time from Input or Feedback to Clock Hold Time Clock to Output Skew Between Registered Outputs (Note 4) Clock Width LOW HIGH External Feedback Internal Feedback (fCNT) No Feedback
fMAX
OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. Skew is measured with all outputs switching in the same direction. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) tS.
PAL16R8-7 (Coml)
2-17
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.4 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-18
PAL16R8D/2 (Coml)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = 25C f = 1 MHz 8 5 pF Typ Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
fMAX
Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) tS.
PAL16R8D/2 (Coml)
2-19
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.4 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-20
PAL16R8B (Coml)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = 25C f = 1 MHz Typ 8 9 pF Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
PAL16R8B (Coml)
2-21
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.7 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-22
PAL16R8B-2 (Coml)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = 25C f = 1 MHz Typ 7 pF 7 Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) tS.
PAL16R8B-2 (Coml)
2-23
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.7 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VCC = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-24
PAL16R8A (Coml)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = 25C f = 1 MHz Typ 7 pF 7 Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
fMAX
Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) tS.
PAL16R8A (Coml)
2-25
AMD
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIN = 18 mA, VCC = Min VIN = 2.4 V, VCC = Max (Note 2) VIN = 0.4 V, VCC = Max (Note 2) VIN = 5.5 V, VCC = Max VOUT = 2.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V as been chosen to avoid test problems caused by tester ground degradation.
2-26
PAL16R8B-4 (Coml)
AMD
OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected.
PAL16R8B-4 (Coml)
2-27
AMD
SWITCHING WAVEFORMS
Input or Feedback tS Input or Feedback VT tPD Combinatorial Output VT
16492D-12
VT tH VT
tCO VT
16492D-13
Combinatorial Output
Registered Output
Clock
Registered Output 1
VT tSKEWR Clock VT
16492D-14
tWH VT tWL
16492D-15
Registered Output 2
Clock Width
VT OE tEA VT
16492D-16
16492D-17
OE to Output Disable/Enable
Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2 ns3 ns typical.
2-28
PAL16R8 Family
AMD
S1
CL
16492D-18
Commercial Specification tPD, tCO tPZX, tEA tPXZ, tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 50 pF 5 pF CL R1 All but B-4: 200 B-4: 800 R2 All but B-4: 390 B-4: 1.56 k
PAL16R8 Family
2-29
AMD
tPD, ns
4.0
3.5
10
tPD, ns
6 5 4
16492D-20
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tPD may be affected.
2-30
PAL16R8-5
AMD
0.2
0.4
0.6
Output, LOW
20
IOH, mA VOH, V
1 20 40
60 80 90
16492D-22
Output, HIGH
II, A 20 1 3 2 1 50 100 150 200
16492D-23
3 VI, V
Input
PAL16R8-5
2-31
AMD
tPD, ns 6.5
6 1 2 3 4 5 6 7 8
16492D-24
tPD, ns 6
5 10 30 50 CL, pF
16492D-25
70
90
110
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tPD may be affected.
2-32
PAL16R8-7
AMD
0.2
0.4
0.6
Output, LOW
IOH, mA 20 VOH, V 3 2 1 1 20 40 60 80
16492D-27
Output, HIGH
II, A 20 1 3 2 1 20 40 60 80
16492D-28
3 VI, V
Input
PAL16R8-7
2-33
AMD
Input
Program/Verify Circuitry
16492D-29
Typical Input
VCC 40 NOM
Output
16492D-30
Typical Output
2-34
PAL16R8-5
AMD
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will be HIGH due to the inverting output buffer. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Parameter Symbol tPR tS tWL Parameter Description Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:
s The VCC rise must be monotonic. s Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feedback setup times are met.
Max 1000 Unit ns
4V Power
VCC tPR
tS
Clock
tWL
16492D-31
PAL16R8 Family
2-35