Virtuoso Foundation IP Characterization

A complete solution for fast and accurate IP modeling and validation

Cadence Virtuoso Foundation IP Characterization delivers the industrys most comprehensive and robust solution for the characterization and validation of your foundation IPfrom standard cells and I/Os to complex I/Os and memory. Its patented inside view technology delivers better correlation to silicon by improving library throughput and ensuring timing, power, noise, and statistical coverage of your cells.

A Complete Solution
Virtuoso Foundation IP Characterization is a suite of highperformance tools for characterizing, validating, and generating libraries for standard cells, I/Os, and memories. The suite achieves both accuracy and high speed through the powerful combination of Inside Viewpatented technology for generating and optimizing characterization stimuluscoupled with a parallel processing capability that takes advantage of enterprise-wide compute resources. The solution includes Virtuoso Liberate, Virtuoso Liberate MX, Virtuoso Liberate LV, and Virtuoso Variety. Virtuoso Foundation IP Characterization also integrates with Virtuoso Spectre Circuit Simulator, the industry-standard SPICE simulator, delivering even greater throughput than when used with standalone thirdparty simulators.
so

ation IP Cha und rac Fo te

ced Model ing van Ad
lls Ce
Com pl

Standard cells Speed, automation (inside view), modeling (CCS, ECSM, power, noise) Complex I/Os Speed, control, accuracy, modeling (IBIS, CCS, ECSM) Memory and custom blocks Speed, accuracy, capacity, modeling (CCS, ECSM, power, noise) Variation and validation Accuracy, modeling (CCS-VA, S-ECSM, AOCV, POCV) Completeness, integration (PT, Encounter Timing System), ease of use

ion at cess Variation riz Pro

SIM Integration MM

Vir tu o

s I/O ex

Std

Inside View
Bl
ock

m
e

Lib

r ar y Valid atio

Figure 1: Virtuoso Foundation IP Characterization with inside view technology

Benefits
Ultra-fast cell library characterization for standard cells and complex I/Os Automatic pre-characterization of each cell using the inside view transistor-level circuit analysis technology to learn all internal logic states and enable automatic vector generation. Complex cell characterization for low-power and/or high-speed designs

or

C ust

om

Support for larger macro blocks such as memory and custom cores employing a unique dynamic partitioning technology to optimize runtime. Ultra-fast throughput to complete library validation overnight on a small number of multi-core computers Variation-aware timing model creation accounting for process variations (systematic and random) for any set of correlated or uncorrelated process parameters.

Virtuoso Foundation IP Characterization

MMSIM
Spectre
Vir tu o
m IC Desig usto nP oC la os t g Prototypin u alo
An

Vi rt

ustom Routin ll C g Fu

SIM Integration MM

De s

n ig

Ve r
ify

Correct by Construction
t
en

Spectre APS Accurate, high-performance simulatioin

Std

Spectre RF Analog and RF-IC noise analysis

Spectre XPS High-speed, high-capacity full-chip variation analysis

AMS Designer Mixed-signal verification at all abstraction levels

so

ation IP Cha und rac Fo te

ced Model ing van Ad
lls Ce
Com pl

ion at cess Variation riz Pro

rm fo

cision Layout Pre

s I/O ex

Inside View
Bl
ock
s
M

C ust

ac

tur

Imp

le

Pa

ras

i t i c - A a re D e w

n si g

Spectre Infrastructure Common infrastructure, advanced simulation database, versatile front-end parser, robust device library Spectre Applications Comprehensive coverage, integrated with Virtuoso, LEA, Liberate, Allegro, and Encounter Timing System technologies

Lib

ra ry Vali d ati o

Figure 2:A complete solution for custom simulation and characterization, with Virtuoso Multi-Mode Simulation and integrated Spectre technology

Virtuoso Liberate
Standard cell and complex I/O characterization

Virtuoso Liberate MX
Memory characterization

Virtuoso Liberate LV
Library validation

Virtuoso Variety
Process variation modeling

Ultra-fast library characterization Patented inside view technology for optimized runtime Advanced timing, power, and signal integrity DC current source models

Characterization of large embedded memories Unique dynamic partitioning technology for optimized runtime Timing constraints and current source models for timing and noise

Comprehensive system validation Library function equivalence and data consistency checking Revision analysis Timing and power correlation

Generation of libraries that can be used by multiple statistical static timing anlysis tools Local and global process variation AOCV tables

Furthermore, for accurate modeling of instance-specific voltage variation or temperature gradients, it is necessary to characterize each library corner at two or three different voltages or temperatures. For the most advanced processes it is becoming common to offer alternative cell libraries that improve yield at the expense of area and performance. Consequently, creation and upkeep of all these library views is becoming a major bottleneck in the design flow.

Figure 3: The solution comprises four main product technologies

The inside view

Virtuoso Liberate uses patented inside view pre-characterization circuit analysis to perform vector generation and pruning (binning), automatic indices selection, as well as optimization of timing constraint characterization. This results in an orderof-magnitude speedup over traditional characterization flows, enabling fully automated library creation overnight.

Virtuoso Liberate
Virtuoso Liberate is an ultra-fast standard cell and I/O library creator. As part of our complete Foundation IP Characterization solution, it generates electrical cell views for timing, power, and signal integrity including advanced current source models (CCS and ECSM). Our patented inside view approach automatically pre-characterizes each cell using transistor-level circuit analysis, which yields all the necessary stimulus and internal logic states to ensure a complete, accurate, and highly efficient characterization of that cell. Virtuoso Liberate supports complex cells including those required for high-speed and/or low-power design such as pulse latches, multi-bit flip-flop arrays, custom

cells, state retention flip-flops, level shifters, power switches, and cells with sleep modes.

Creation and upkeep of library views

Designing in nanometer process technologies requires many additional library views to achieve high-quality silicon and avoid silicon re-spins due to inaccurate signoff analysis. To manage leakage power it is common to have low, typical, and high threshold cells each with different power and performance characteristics.

Parallel characterization
Virtuoso Liberate can fully exploit a large network of multi-core CPUs via intelligent job distribution (with or without a job queue management system) to achieve almost linear speedup per CPU. Virtuoso

Patented inside view technology

Transistor-level analysis

Complex cell recognition and vetor reduction

Figure 4: Pre-characterization circuit analysis

www.cadence.com 2

m
e

or

M an

om

uf

Virtuoso Foundation IP Characterization

Existing .lib Subckts, Spice Model Tcl

Liberate Server
Inside View Circuit Analysis Parallel Job Manager

the input and output channel connected logic stages and all the intermediate internal probe points.

Model generation
Virtuoso Liberate generates Liberty, Verilog, Vital, and IBIS models, supporting the latest approved format updates. The models are generated from a central library characterization database (ldb). Multiple versions of library models can be generated from the database to support tools that use older versions of the formats without re-characterization. All the data in the database can be accessed via a Tcl API that can be used to generate proprietary model formats and user-specific datasheets by modifying provided examples. The database supports incremental update and can be used to recover from characterization failures caused by network problems.

Liberate Client

Liberate Client

.ldb

Liberate Client

Liberate Client

ALAPI Model Creation Model Validation Liberate flow with multiple clients
Figure 5: Parallel characterization

.v .lib

.vhd .ibs

Liberate characterization client is autonomous, greatly reducing network traffic, file I/O, and queue requests. Furthermore, multiple characterization tasks consisting of arcs from a number of cells can be grouped into packets of work for optimal use of CPU resources. Characterization tasks can be performed using Virtuoso Spectre, Virtuoso Spectre APS, Virtuoso Liberates internal SPICE simulator or by an external simulators such as Eldo, Finesim, Analog FastSPICE, and HSpice at any level of granularity, from a single arc to a complete cell. Commercial job management systems such as LSF, Sungrid, and FlowTracer are all supported.

waveform segments to minimize the volume of data while ensuring accuracy and consistency with non-linear delay models (NLDMs). For multi-latch cells, Virtuoso Liberate automatically determines internal probe points for characterizing timing constraints. For noise view generation, it automatically determines

Advanced characterization algorithms

Virtuoso Liberate supports advanced characterization algorithms providing models with better correlation and minimized pessimism within static timing

Complex cell and model support

Virtuoso Liberate can characterize highly complex cells (including I/Os such as DDR, USB, and PCIX), clock dividers, pipeline flip-flops, one-hot muxes, and custom cells with domino logic. It supports a user-specified truth table to drive characterization in addition to automatic vector generation. Complex termination conditions and differential inputs and outputs are also supported, as well as simultaneous input switching for creating best-case corners. Virtuoso Liberate natively generates current source models for both CCS and ECSM, automatically adjusting the

Figure 6: Advanced characterization algorithms

www.cadence.com

Virtuoso Foundation IP Characterization

Cadence Memory Characterization Server TCL static Inside View Probing Vector generation Boundary Modeling Block level simulation Fast-Spice Power Characterization Dynamic Partitioning

Bi-modal view characterization

Virtuoso Liberate MX uses both a fullblock view and partitioned sub-block views to characterize large macro blocks efficiently and accurately. The full-block view is used to characterize power and to drive the creation of sub-block partitions. Typically a FastSPICE simulator such as Virtuoso UltraSim Full-Chip Simulator, Hsim, FineSim Pro, or ADiT is used for fullblock circuit analysis; a traditional SPICE simulator is used for characterizing the sub-blocks. Virtuoso Liberate MX optionally supports a single-block view characterization using only a FastSPICE simulator.

Spice netlist(s) dynamic

.tbl

.vec

Partition Characterization True-Spice

Liberate MX Clients

.ldb

Circuit partitioning
To partition each macro, Virtuoso Liberate MX first determines internal measurement points via propagation of clocks signals and recognition of internal storage elements. It uses two distinct techniques for partitioning: static and dynamic. Static partitions are based solely on circuit topology and are used for fully digital sections of the macro. A typical static partition would be all of the channel connected logic components on the path between a primary input and a first-level flip-flop including all the required clock generation circuitry. Dynamic partitions are derived from a full-block transistor-level simulation using a pattern sequence or a high-level truth table description. From the simulation, an active circuit snapshot can be extracted corresponding to the worst-case timing. Dynamic partitioning is useful for characterizing timing arcs that contain analog circuitry, such as the clock to output data arcs in embedded memories. Once a macro has been partitioned into sub-blocks comprising typically a few hundred transistors, and armed with the worstcase vector set required to characterize each arc of each partition, Virtuoso Liberate MX submits each partition for characterization using the integrated Spectre Accelerated Parallel Simulator (APS) or an external simulator such as Eldo or HSpice.

Model Generation

.ldb (ccs, ecsm)

Figure 7: Memory characterization flow

analysis (STA) tools. These algorithms include Setup and Hold Pessimism Reduction, Minimized Delay to Output, Dependent Setup and Hold, Optimized Internal Power Controls, and many others. These algorithms are activated easily through user-selectable characterization controls.

Virtuoso Liberate MX
Virtuoso Liberate MX extends the ultrafast standard cell and I/O library characterization capabilities of Virtuoso Liberate to cover larger macro blocks such as memory and custom cores. Macro blocks require additional pre-analysis steps to make fast and accurate characterization feasible. Leveraging a network of distributed CPUs and utilizing the patented inside view technology for optimizing characterization runtime, memories and cores can be characterized quickly and easily with the same accuracy and methods as standard cells, including the generation of timing constraints and modeling of current source models for timing and noise.

Memories and large custom macros comprise a large percentage of silicon area on most chips and, consequently, can often be major contributors to chip performance and power consumption. To validate a designs electrical performance, it is essential to have a highly accurate electrical model for each macro equivalent in accuracy of the electrical models used for standard cells and I/Os. Using pre-packaged models provided by an IP provider or memory compiler may not provide sufficient accuracy, especially as the exact context of the macro is not known until it is placed on the chip. The model may be too pessimistic, causing overruns in schedule and increased usage of larger or leakier cells to close timing. It is also common to operate a macro block at a lower voltage to save power. To get an accurate electrical model that reflects the exact usage of the macro, a designspecific and/or instance-specific macro block characterization is required.

www.cadence.com

Virtuoso Foundation IP Characterization

Library generation
Leveraging the same characterization techniques and the same command options as Virtuoso Liberate, arcs from each MX partition are characterized across a distributed network of computers utilizing all available CPUs. The distribution can be controlled using a job management system or using Liberates built-in job scheduler. Current source models (CCS/ECSM) for timing and noise can also be generated. Timing constraints are calculated using the same bi-sectional method as used for standard cells or, even more efficiently, as a difference in clock and data path delay. After characterization, all the characterized library data for each partition is assembled and compressed into a single output library representing the macro in Liberty format.

Using Virtuoso Liberate LV, a complete validation of a library can be completed overnight on a small number of multicore computers. For library providers, this ensures library quality before the library is shipped. For library users, it allows cross-checking of the incoming library and provides a clear understanding of the impact of any changes due to revisions of extracted cell netlists or process models. Library characterization requires a complex combination of circuit simulations, data measurements, data collection, and formattingoften distributed across a large computer network. Since each library view is used for multiple chip designs, it is paramount that the library data is correct and not undermined by mesaurement inaccuracies or incorrect user input. Virtuoso Liberate LV provides the means to validate and verify the final library, ensuring consistency, completeness, and accuracy.

may not be consistent with the underlying transistor-level circuits that comprise the current library to be characterized. Virtuoso Liberate LV checks all function descriptions in the input library directly against the transistor-level circuit and report any differences, thus preventing potential functional errors that may occur later when the design is being formally verified or tested after manufacturing. Virtuoso Liberate LV provides the means to ensure that all the functional information stored in a library (.lib) is consistent between the transistor-level SPICE sub-circuits and the library Verilog and/or Vital descriptions. In addition, Liberate LV will ensure that all the necessary timing, noise, power (both switching and hidden power), and leakage arcs and states are represented in the library, and it will report any that are missing. It will warn where not enough distinct states exist so that potential inaccuracies in downstream tools can be avoided.

Virtuoso Liberate LV
Virtuoso Liberate LV provides a collection of utilities for validating libraries including functional equivalence checking, data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power.

Function and state coverage

When characterizing a cell library, the input directives, vectors, and stimuli often come from a user, provided either as a previous library or hand-coded in the characterization tools input language. However, these vectors and assumptions

Consistency checks
Virtuoso Liberate LV provides a number of data consistency checks such as comparing table-based non-linear delay models (NLDMs) against current (CCS) and voltage (ECSM) data, as well as checking for non-monotonic delay values. For Verilog and Vital models, consistency with the Liberty models (.lib) can be checked by automatically testing SDF backannotation onto a high-level design, which instantiates each cell in the library. Multiple SDF generation tools are supported, along with multiple gatelevel logic simulators such as Cadence Incisive Simulator and other commercial simulators such as Modelsim and VCS.

Verilog/Vital (.v, .vhd)

Cadence Library Verification Functional Validation Consistency Checks Library Comparison Accuracy Validatioin

Tcl

Libraries (.lib)

Validation Reports (txt, xls, htm)

Models and Subckts (.spi)

Library revisions
Circuit Simulation Signoff Analysis Open STA Enviroment

Open Simulation Enviroment

API for custom checks Library verification inputs and outputs

Figure 8: Virtuoso Liberate LV

Virtuoso Liberate LV provides the means to compare a new library against an existing golden library, generating graphical, HTML, and text reports. This includes comparing libraries with different indices, function syntax, states, and cell names. This allows verification of libraries created with different characterization systems. It also highlights the impact

www.cadence.com

Virtuoso Foundation IP Characterization

Virtuoso Variety
Virtuoso Variety is an ultra-fast standard cell characterizer of process variationaware timing models. It generates libraries that can be used with multiple statistical static timing analyzers (SSTAs) without requiring re-characterization for each unique format. Virtuoso Variety calculates non-linear sensitivity, accounting for systematic and random variation for any set of correlated or uncorrelated process parameters. The resulting libraries can be used to model both local (within-cell and within-die) variations and global die-to-die variations.

Virtuoso Liberate LV Timing Validation Comparison Html Report

SSTA provides a more realistic estimation of timing relative to actual silicon performance, often reducing worst-case timing margins by 10-15%, resulting in a higherperforming higher yielding silicon. To accurately predict variation, SSTA needs variation-aware timing models that account for both systematic process variations (due to lithography) and random process variations (due to doping fluctuations between transistors).

Virtuoso Liberate LV Sample Test Circuit

Figure 9: Library validation and correlation

of each new library revision, detailing changes in delay, capacitance, constraints, switching power, noise, and leakage.

Library validation and correlation

To verify that the library data is accurate, Virtuoso Liberate LV performs a correlation using the library data in the appropriate analysis tool against results obtained from circuit simulation. To ensure delay accuracy, Liberate LV will invoke a static timing analyzer and compare the resulting values against simulation of a test circuit using a SPICE simulator. The test circuits are automatically created; for example, as a variablelength chain of cells with interconnect parasitics. Every input-to-output arc will be verified for each logic state, input slew, and load condition. Statistical static timing analysis (SSTA) tools are also supported by comparing the path mean delay and standard deviation to Monte Carlo SPICE simulations. Virtuoso Liberate LV also includes the means to measure the accuracy of timing constraints, switching power, leakage, and noise. It supports multiple analysis tools for timing and noise analysis (e.g.

Synopsys PrimeTime SI, GoldTime, Cadence Encounter Timing System, Incentia TimeCraft, and SPICE simulation with Virtuoso Spectre Circuit Simulator and third-party simulators such as Eldo and HSpice.

Statistical timing models

Virtuoso Variety creates models for SSTA consumption by characterizing each cell for a given set of process parameter variations where the amount of variation is based on statistical SPICE models or actual process measure-

Existing .lib Subckts, Statistical Spice Model Parameter (Tcl)

Variety Server
Inside View Circuit Analysis Parallel Job Manager

Variety Client

Variety Client

.ldb

Variety Client

Variety Client

SSTA Model Creation

.ccs_va (Synopsys) .aocv (Synopsys, Cadence)

.xt (Extreme DA) .s-ecsm (Cadence)

Figure 10: Virtuoso Variety

www.cadence.com

Virtuoso Foundation IP Characterization

Vth sigma=20mV, Vdd=1.0V, TT Virtuoso Variety result (ns)

pre-analysis technology that avoids characterizing every transistor uniquely for every table entry. This proprietary method has been validated to be highly accurate against traditional Monte Carlo simulations. Virtuoso Varietys overhead for random variation characterization is typically less than 3 times nominal characterization. Without the inside view, it would take 25-50 times nominal characterization for each random parameter for a typical standard cell library. Virtuoso Variety can fully exploit a large network of multi-core CPUs via intelligent job distribution (with or without a job queue management system) to achieve almost linear speedup per CPU. Characterization tasks can be performed using Varietys internally integrated SPICE simulator (Virtuoso Spectre Circuit Simulator), or an external simulator such as Eldo or HSpice, at any level of granularity from a single arc to a complete cell.

Monte Carlo reference (ns)

Figure 11: Process parameter variation

ments. The non-linear sensitivity to process variation for all relevant timing constructs is captured including delay tables, slew tables, pin capacitance, and timing constraints. Advanced current source models (CCS and ECSM) are also supported. Virtuoso Variety can generate multiple SSTA formats from a single characterization database (ldb). XT format (used by Extreme Design Automation), S-ECSM format (used by Cadence) and both the multiple Liberty files and compact CCS VA format (used by Synopsys) are supported. Custom SSTA formats can be easily supported using a Tcl API to the characterization database.

together. Partial correlation is supported through the use of a correlation matrix provided by the foundry. Any process parameter present in the input SPICE model can be characterized including physical parameters such as XL or Vth, or intermediate parameters that have been derived from principle component analysis (PCA).

Systematic and random variation

For systematic inter-cell variation, the process varies in the same direction by the same amount for each transistor inside a cell. Systematic variation can be used to model both on-chip (local) and off-chip (global) variation. Random intra-cell variation models the process variations that apply to each transistor independently (also known as mismatch). To characterize random variation efficiently, Virtuoso Variety deploys the patented inside view

Process parameter variation

Parameter variations can be characterized as uncorrelated, correlated, or partially correlated. Uncorrelated parameter sets are simulated independently while correlated parameter sets are simulated

Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
2012 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, Incisive, Spectre, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 23023 11/12 MK/DM/PDF