Question: What is the maximum distance of the I2C bus?

This depends on the load of the bus and the speed you run at. In typical applications, the length is a few meters (9-12ft). The ma imum capaciti!e load has been specified (see also the electrical "pec#s in the I2$ %&'). &nother thing to be ta(en into account is the amount of noise pic(ed up by long cabling. This noise can disturb the signal transmitted o!er the bus so badly that it becomes unreadable. The length can be increased significantly by running at a lower cloc( fre)uency. *ne particular application - cloc(ed at about +,,-. - had a bus length of about 1,,m (/,,ft). If you are careful in routing your 0$1#s and use proper cabling (twisted pair and2or shielded cable), you can also gain some length. If you need to go far at high speed, you can use an acti!e current source instead of a simple pull-up resistor. 0hilips has a standalone product for this purpose. 3sing a charge pump also reduces 4ghost signals4 caused by reflections at the end of the bus lines.

Q&A Sheet 2
Question: I'd like to extend the I2C bus. Is there somethin like a re!eater for I2C? 5es indeed this e ists. 0hilips manufactures a special chip to buffer the bidirectional lines of the I2$ bus. Typically, this is a current amplifier. It forces current into the wiring (a couple of m&). That way you can o!ercome the capacitance of long wiring.

-owe!er, you will need this component on both sides of the line. The charge pump in this de!ices can deli!er currents up to /,m& which is way too much for a normal I2$ chip to handle. 6ith these buffers you can handle loads up to 2n%. The charge amplifier #transforms# this load down to a 2,,p% load which is still acceptable by I2$ components. Question: Can I do al"anic decou!lin of m# I2C bus? This is possible. The circuit is rather comple due to the bi-directional nature of the I2$ bus. The following figure shows a possible solution7

Com!onent $alues: + and +# 7 080 li(e 2n2219 or 1$++9 : and :# 7 808 li(e 2n2222 or 1$ +;9 1 and 1# 7 29, *hm 2 and 2# 7 //,, *hm / and /# 7 1<,, *hm ; and ;# 7 1,,, *hm *ptocouplers 7 :n1/9 , ;n29 or Til 111 8ote7 "ince the speed of the I2$ bus can be rather high, it is recommended to use a fast optocoupler. -owe!er, this circuit will not wor( on speeds higher then 1,=-.. & :81/9 will do the >ob in all cases. The two 080 and the two 808 transistors can be any standard type, e.g. 282219 and 282222 (3"&) or 1$+;9 and 1$++9 (?3@*0?). %o& does it &ork ? The problem with bi-directional lines is that a buffer tends to get stuc( on a certain le!el. This case has been ta(en into account in the abo!e schematic. In the following e planation we assume that the left side is transmitting and the right side is recei!ing (the circuit is symmetrical) Aet#s assume we send a logic 1 into the left side. The A?B of the top optocoupler will stay dar(. "ince its transistor does not recei!e any light, it is not turned on. The ne t transistor does not get dri!en and the line at the end is being pulled high !ia resistors 1# and /#. The 080 transistor +# will not get dri!en. Therefore the A?B connected to it will not light up and there is no feedbac( signal. 8ow let#s see what will happen if we send a logic ,. The first transistor + will be turned on, therefore the led connected to it will start emitting light. This results in the fact that its matching transistor will turn on. The transistor connected to the emitter will be turned on also. The output line is now being pulled low !ia resistor /#. This low le!el would turn on the 080 transistor, which would result in the other optocoupler to light, its transistor to turn on etc. In other words, the circuit would go into a loc(-up. -owe!er, since the 808 transistor is pulling the anode of the A?B to ground, this will not happen. This way we ha!e eliminated the deadloc(.

Are there stand'alone I2C controllers a"ailable? 5es indeed. There is a special chip to do the I2$ interfacing. The 0$B<+<; or 0$%<+<; incorporate a complete I2$ interface. These chips are designed in such way that they can interface to almost any microcontroller around %o& can I enerate a re!eated start condition? Aet#s assume the following situation7 The controller lets the "$A line go high and the de!ice pulls "B& low to ac(nowledge. "o far no problem but how do you generate a repeated start condition nowC The de!ice is pulling "B& low. %irst you ha!e to complete the &$= cycle. To do this, you must pull "$A low again. The sla!e will release the data line when it detects that "$A is low. 8ow you can issue a stop command. To do this, you let the "$A go high again and then pull low the "B& line. This is the confusing part of the procedure. 8ormally, you would suspect that by letting the cloc( line go high again you will be cloc(ing in the first bit of a new byte. &s a matter of fact that is the case. 1ut since the chip will detect a "T&@T condition, this operation gets cancelled Can I abort an on oin I2C bus transmission? Is it o(ay to abort an on-going transmission any time. &ccording to the specification, this should wor(. It depends on the layout of the component. & real I2$ compatible I$ will be able to handle this. It might ma(e sense to test this before you use it. 3sually, when a "T&@T or "T*0 condition is detected, the internal logic of the chip is forced into a certain state. Internally, the logic that detects "T&@T and "T*0 is different from the logic that does all other processing. The "T&@T together with the address register is to be considered as a functional unit inside the chip. 6hen a "T&@T is detected, all internal operations are cancelled and the chip will compare the incoming data with its own address. 6hen a "T*0 is detected, &AA chips on the bus will reset their internal logic to IBA? mode e cept for the "T&@T detector (this is also used to cut power consumption). Therefore, when a start condition is issued on the bus, the "T&@T detector will #wa(e-up# the rest of the internal logic. Wh# does the SC( line ha"e to be bi'directional?

The cloc( line needs to be bi-directional when using a D3ATI-D&"T?@ protocol and when using the synchroni.ation protocol. 6hen you are using only one Daster then this is not re)uired since the cloc( will always be generated by this de!ice. If you run Dulti-master then this changes. *ne master must be able to recei!e data from another master. &t that time it must be able to recei!e cloc( information !ia the cloc( line also Question: %o& can I im!lement an acti"e !ull'u! resistor to enhance the bus len th? 5ou can use an I$ or build it with discrete components. &ll you will need is some resistors and an off-the-shelf analog switch. -ere comes the schematic7

%o& it &orks: @s are serial resistors used to minimi.e cross tal( and undershoot. They also protect the I2* dri!ers of the I2$ de!ices against higher than allowed !oltages and current in>ection. These resistors are ad!ised if you run a long bus on high speed (such as in enhanced I2$ mode). 6hen the bus becomes idle, all output stages on the bus are turned off and "$A and "B&) go high. This will not happen immediately, the !oltage will rather rise during a certain time. 8ow assume the switch (I$1) is not there. The charge time of the bus capacitor would only be determined by the !alue of @1. The larger @1 and @s, the longer it will ta(e for the bus to reach a sufficient stable -IE- le!el. 6e can#t ma(e the @s resistors too small because then we would go out of spec on the ma imum allowable current into one I2$ de!ice when turning on its output dri!er. 6hen we calculate for a current of /m&, we end up at appro imately 1<,, *hms for the serial resistance. +F 2 /m& G 1::: *hms.

To stay somewhere below this /m& rating, we pic( 1<,, *hms. The charge time for a bus capacitance of about 2,,p% would be around /:, ns. That is out of spec. The spec for rise or fall time in %ast I2$ is set to appro /,,ns. 1ut we can#t drop the !alue of our resistor without brea(ing the other spec of /m& of ma imum current. The idea is to change the !alue of the resistor temporarily using the analog switch I$1. If the !oltage le!el sensed by the switch is in the range ,.< to 2 !olts then it will turn on. This means that as soon as the !oltage on the "B& line starts rising, resistor @2 will (ic( in. @1 and @2 in parallel result in a resistance of 92, *hms. This increases the charge current to a !alue of + !olts 2 92, *hms G 9 m&. This is allowable for a brief period of time. *f course all of this is a dynamic process. The actual charge current will change due to the fact that the bus !oltage will rise. & small graphical representation will e plain more7

6a!eform 1 represents turning off the I2$ de!ice, which will release the bus lines so that they can go -IE-. 6a!eform 2 is what you get if you only use a resistor. The bus slowly comes up to + !olts due to @$ constant of the pull-up resistor @1 and the parasitic capacitance of the bus line $p. 6a!eform / shows the analog switch (ic(ing in. If the bus line is at appro ,.9 !olts it closes. It opens again when the bus reaches appro / !olts. 6a!eform ; is how the !oltage on the bus changes. 5ou can see that it rises much faster when the switch is turned on. %inally, wa!eform + shows the current flowing into the I2$ de!ice. It starts at appro /m&.

6hen the output stage is turned off, this current slightly drops due to the fact that the !oltage on the bus is rising. The moment our switch (ic(s in you see the current doubling. The same effect is then present as before the switch closed7 the current drops as the bus !oltage rises. 6hen the switch opens again the current drops a little to charge the capacitor up to + !olts. 1ut at that time, all chips already detect a logic one and are well within the /,,ns rise time %o& can I test ) debu the I2C bus? There is no general way to debug an I2$ bus. -owe!er, a few guidelines might help to get it running. %irst thing is to chec( the le!els on the bus. 5ou should see a clear signal that has a low le!el that is lower then ,.< !olt and a high le!el which is at least /.+ !olts. If the high le!el is not high enough or does not rise fast enough then you can try to lower the !alue of the pull up resistor. 5ou must ta(e care howe!er not to surpass the ma imum allowable current in the I2$ dri!er stage. The minimum allowable resistor for a + !olt dri!en I2$ bus is + F 2 /m& G 1:,, *hms. & typical !alue of ;9,, ohm should wor( fine. Da(e sure the bus is not #stuc(# to #,#. This could be the result of a bad power supply (chips go into latch up during power-on) or a bad chip. There are a few commercial I2$ monitor 2 debuggers around. Information on these de!ices can be found here. Is there an *S2+2 ) I2C con"erter? 5es, there are at least two of them. 0lease !isit one of the following lin(s7 http722www.emicros.com2i2c2/2.htm http722www.pic(eringswitch.com2simrc2simrcspec.html What bus s!eeds are a"ailable &ith I2C? The bus speed for I2$ was increased o!er the years. The following modes are a!ailable7

"tandard mode, with a bit rate up to 1,,(bit2s %ast-mode, with a bit rate up to ;,, (bit2s -igh-speed mode (-s-mode), with a bit rate up to /.; Dbit2s

,roubleshootin

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Right. So you have built your first system using the I2C bus and you find out that it doesn't work as it should. This section covers a few of the common pitfalls involved in using the bus. irst thing to check is! Are the pull-up resistors connected? "robably the most common error is that people forget to connect a pull#up resistor between S$% and &CC and SC' and &CC. Remember! S$% and SC' are open collector or open#drain lines. Resistance value should be between ()* and (*). The longer you make your lines the lower the resistance value should be. This is to force more current into the lines to overcome the capacitance formed by the lines. +This is very important if you want to run on high speeds, Are all the lines toggled between the logic levels? Check that the levels on both S$% and SC' fall into the allowed range. Check this both for high and low levels. -y now you should have a bus that is capable of transporting I2C signals. .ow you can try to send some information to a chip or read some information It is best to connect only one slave device to the I2C bus. The chip is not responding. Check following things in order! Are SCL and SDA connected correctly? Are you accessing the right address? Has the start command been issued correctly? If you have a storage scope you can monitor the bus by connecting Channel / to S$% and channel 2 to SC'. Set the scope on Single shot trigger on channel 2. Set pre#trigger to / division. If you don't have a scope you can use another trick. Send the start command plus the slave address. .ow make the SC' line high. 0our 1aster is now waiting for %C) from the slave device. 0ou can connect a led 2 resistor between &CC and S$%. If the led does not light then something is wrong.

VCC

_____ ---|>|--|___|--- SDA LED 470 Ohms

Send a couple of stop commands and then try again. It is possible that the chip is locking up due to power#on effects. Replace the chip. It could be defective. .ow you can connect the other devices one by one. 3ach time try to access them. I get strange results. Reading a device a couple of times ends up with different data all the time. 4riting does not give predictable results. Sometimes the bus even locks up. The most logic e5planation here is that you have 2 chips on the same address. This can happen. 35ample! 0ou have a circuit that uses 2 "C 67*( I89 ports. In your hurry you forget to wire them for different addresses. +0ou can have up to 6 of these in your circuit, That's about it. In most other cases you will need a storage scope to view what is actually happening on the I2C bus