W78E58B/W78E058B Data Sheet 8-Bit Microcontroller: Table of Contents
W78E58B/W78E058B Data Sheet 8-Bit Microcontroller: Table of Contents
W78E58B/W78E058B Data Sheet 8-Bit Microcontroller: Table of Contents
8-BIT MICROCONTROLLER
Table of Contents1. GENERAL DESCRIPTION ............................................................................................................... 3
2. FEATURES ....................................................................................................................................... 3
3. PIN CONFIGURATIONS .................................................................................................................. 4
4. PIN DESCRIPTION .......................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION ......................................................................................................... 6
5.1
RAM ....................................................................................................................................... 6
5.2
5.3
Clock ...................................................................................................................................... 7
5.4
Crystal Oscillator.................................................................................................................... 7
5.5
External Clock........................................................................................................................ 7
5.6
Power Management............................................................................................................... 7
5.7
5.8
Reset...................................................................................................................................... 7
5.9
Port 4 ..................................................................................................................................... 9
5.10
5.11
5.12
5.13
5.14
6. SECURITY ...................................................................................................................................... 19
6.1
6.2
6.3
Encryption ............................................................................................................................ 20
6.4
7. ELECTRICAL CHARACTERISTICS............................................................................................... 21
7.1
7.2
D.C. Characteristics............................................................................................................. 21
7.3
7.3.2
7.3.3
7.3.4
7.3.5
-1-
W78E58B/W78E058B
8. TIMING WAVEFORMS................................................................................................................... 25
8.1
8.2
8.3
8.4
9.2
40-pin DIP............................................................................................................................ 29
10.2
10.3
-2-
W78E58B/W78E058B
1. GENERAL DESCRIPTION
The W78E058B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E058B is fully compatible with the standard 8052.
The W78E058B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional
4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the
W78E058B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78E058B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
y
32K bytes of in-system programmable Flash EPROM for Application Program (APROM)
512 bytes of on-chip RAM (including 256 bytes of AUX-RAM, software selectable)
64K bytes program memory address space and 64K bytes data memory address space
Code protection
Packaged in
Lead Free (RoHS) DIP 40:
W78E058B40DL
Lead Free (RoHS) PLCC 44: W78E058B40PL
Lead Free (RoHS) PQFP 44: W78E058B40FL
-3-
W78E58B/W78E058B
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
40
T2EX, P1.1
39
P0.0, AD0
P1.2
38
P0.1, AD1
P1.3
37
P0.2, AD2
P1.4
36
P0.3, AD3
P1.5
35
P0.4, AD4
P1.6
34
P0.5, AD5
P1.7
33
P0.6, AD6
RST
32
P0.7, AD7
RXD, P3.0
10
31
TXD, P3.1
11
30
EA
ALE
INT0, P3.2
12
29
PSEN
INT1, P3.3
13
28
P2.7, A15
T0, P3.4
14
27
P2.6, A14
T1, P3.5
15
26
P2.5, A13
WR, P3.6
16
25
P2.4, A12
RD, P3.7
17
24
P2.3, A11
XTAL2
18
23
P2.2, A10
XTAL1
19
22
P2.1, A9
VSS
20
21
P2.0, A8
44-Pin QFP
44-Pin PLCC
P
1
.
4
P
1
.
3
P
1
.
2
T
2
E
X
,
P
1
.
1
T
2
,
P
1
.
0
2
/
I
N
T
3
,
P
4 V
. D
2 D
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P
1
.
4
P1.5
P1.6
1 44 43 42 41 40
39
38
P1.7
37
P0.7, AD7
P0.4, AD4
P0.5, AD5
P0.6, AD6
RST
10
36
RXD, P3.0
11
35
EA
INT2, P4.3
TXD, P3.1
12
34
P4.1
13
33
ALE
INT0, P3.2
14
32
INT1, P3.3
15
31
T0, P3.4
T1, P3.5
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
VDD
V
S
S
P
4
.
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
PSEN
P2.7, A15
-4-
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
44 43 42 41 40 39 38 37 36 35 34
33
P0.4, AD4
P1.6
32
P0.5, AD5
P1.7
31
P0.6, AD6
RST
30
P0.7, AD7
RXD, P3.0
29
EA
INT2, P4.3
28
P4.1
ALE
TXD, P3.1
27
INT0, P3.2
26
INT1, P3.3
25
PSEN
P2.7, A15
10
11
24
23
P2.6, A14
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
2
.
4
,
A
1
2
A
D
0
,
P
0
.
0
T1, P3.5
P2.5, A13
T
2
,
P
1
.
0
/
I
N
T
3
,
P
4 V
. D
2 D
P1.5
T0, P3.4
P2.6, A14
P
1
.
3
T
2
E
X
,
P P
1 1
. .
2 1
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V
S
S
P
4
.
0
P
2
.
0
,
P
2
.
1
,
A A
8 9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P2.5, A13
W78E58B/W78E058B
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.
PSEN
O H
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ALE
O H
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RST
I L
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
XTAL1
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
VSS
VDD
P0.0 P0.7
P1.0 P1.7
P2.0 P2.7
I/O H
P3.0 P3.7
P4.0 P4.3
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
-5-
W78E58B/W78E058B
5. FUNCTIONAL DESCRIPTION
The W78E058B architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
5.1
RAM
The internal data RAM in the W78E058B is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
y
RAM 0H 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
RAM 80H FFH can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
AUX-RAM 0H FFH is addressed indirectly as the same way to access external data memory
with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and
DPTR register. An access to external data memory locations higher than FFH will be performed
with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset.
Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is
enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing
from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and
RD .
Example,
CHPENR
REG
F6H
CHPCON
BFH
REG
MOV
CHPENR, #87H
MOV
CHPENR, #59H
ORL
MOV
CHPENR, #00H
MOV
R0, #12H
MOV
A, #34H
MOVX
@R0, A
5.2
Timers 0, 1 and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
-6-
W78E58B/W78E058B
5.3
Clock
The W78E058B is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E058B relatively insensitive to duty
cycle variations in the clock.
5.4
Crystal Oscillator
The W78E058B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
5.5
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
5.6
Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered.
5.7
The W78E058B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
5.8
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E058B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
-7-
W78E58B/W78E058B
W78E058B Special Function Registers (SFRs) and Reset Values
FF
F8
F0
+B
CHPENR
00000000
00000000
F7
E8
EF
+ACC
E0
E7
00000000
+P4
D8
DF
xxxx1111
+PSW
D0
D7
00000000
C8
+T2CON
RCAP2L
00000000
XICON
C0
P4CONA
00000000
B8
RCAP2H
TL2
P4CONB
SFRAL
98
90
88
80
SFRCN
CHPCON
00000000
0xx00000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
A0
SFRFD
+IP
P43AL
00000000
A8
SFRAH
CF
+P3
B0
TH2
P43AH
P42AH
00000000
BF
B7
00000000 00000000
P42AL
00000000
C7
P2ECON
0000xx00
AF
A7
SBUF
xxxxxxxx
TMOD
00000000
SP
00000111
9F
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
P41AL
00000000
TH0
00000000
P40AL
00000000
P41AH
00000000
TH1
00000000
P40AH
00000000
Notes:
1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
-8-
97
8F
PCON
00110000
87
W78E58B/W78E058B
5.9
Port 4
Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0 P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt INT3 and INT2 if enabled.
Mode 1: P4.0 P4.3 are read strobe signals that are synchronized with RD signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0 P4.3 are write strobe signals that are synchronized with WR signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0 P4.3 are read/write strobe signals that are synchronized with RD or WR signal at
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
EX3
IE3
IT3
PX2
EX2
IE2
IT2
-9-
W78E58B/W78E058B
Eight-source interrupt information
INTERRUPT
SOURCE
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
03H
0 (highest)
IE.0
TCON.0
Timer/Counter 0
0BH
IE.1
External Interrupt 1
13H
IE.2
TCON.2
Timer/Counter 1
1BH
IE.3
Serial Port
23H
IE.4
Timer/Counter 2
2BH
IE.5
External Interrupt 2
33H
XICON.2
XICON.0
External Interrupt 3
3BH
7 (lowest)
XICON.6
XICON.3
P4CONB (C3H)
BIT
NAME
FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
7, 6
P43FUN1
P43FUN0
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
5, 4
P43CMP1
P43CMP0
01: Compare the 15 high bits (A15 A1) of address bus with the base address
register P43AH, P43AL.
10: Compare the 14 high bits (A15 A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15 A8) of address bus with the base address
register P43AH, P43AL.
3, 2
1, 0
P42FUN1
P42FUN0
P42CMP1
P42CMP0
The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.2 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
- 10 -
W78E58B/W78E058B
P4CONA (C2H)
BIT
7, 6
5, 4
3, 2
1, 0
NAME
FUNCTION
P41FUN1
The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P41FUN0
P41CMP1
P41CMP0
P40FUN1
P40FUN0
P40CMP1
P40CMP0
The P4.1 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.0 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
P2ECON (AEH)
BIT
NAME
FUNCTION
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
7
P43CSINV
1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe
signal.
0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
Reserve
Reserve
P41AH, P41AL
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
- 11 -
W78E58B/W78E058B
P42AH, P42AL
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.
P4 (D8H)
BIT
NAME
FUNCTION
Reserve
Reserve
Reserve
Reserve
P43
P42
P41
P40
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H
1237H and positive polarity, and P4.1 P4.3 are used as general I/O ports.
MOV P40AH, #12H
MOV P40AL, #34H
MOV P4CONA, #00001010B
MOV P4CONB, #00H
MOV P2ECON, #10H
Then any instruction MOVX @DPTR, A (with DPTR = 1234H 1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of
data #XX to pin P4.3 P4.1.
- 12 -
W78E58B/W78E058B
P4xCSINV
P4 REGISTER
P4.x
DATA I/O
RD_CS
MUX 4->1
WR_CS
READ
WRITE
RD/WR_CS
PIN
P4.x
ADDRESS BUS
P4xFUN0
P4xFUN1
EQUAL
REGISTER
P4xAL
P4xAH
Bit Length
Selectable
comparator
REGISTER
P4xCMP0
P4xCMP1
- 13 -
W78E58B/W78E058B
applications, the in-system programming feature make it possible to easily update the system
firmware without opening the chassis.
SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order
byte of address.
SFRFD: The programming data for on-chip ROM in programming mode.
SFRCN: The control byte of on-chip ROM programming mode.
SFRCN (C7)
BIT
NAME
FUNCTION
Reserve.
On-chip ROM bank select for in-system programming.
WFWIN
OEN
CEN
3, 2, 1, 0
MODE
WFWIN
CTRL<3:0>
OEN
CEN
SFRAH, SFRAL
SFRFD
0010
0001
Address in
Data in
0000
Address in
Data out
0010
0001
Address in
Data in
0000
Address in
Data out
- 14 -
W78E58B/W78E058B
5.13 In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT
NAME
FUNCTION
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will
SWRESET enforce microcontroller reset to initial condition just like power on reset. This
(F04KMODE) action will re-boot the microcontroller and start to normal operation. To read this
bit in logic-1 can determine that the F04KBOOT mode is running.
Reserve.
Reserve.
ENAUXRAM
Must set to 0.
Must set to 0.
FBOOTSL
programmability
- 15 -
W78E58B/W78E058B
F04KBOOT Mode
P4.3
P2.7
P2.6
MODE
FO4KBOOT
FO4KBOOT
P2.7
Hi-Z
P2.6
Hi-Z
RST
30 mS
10 mS
- 16 -
W78E58B/W78E058B
procedure of entering
In-System Programming Mode
Enter In-System
Programming Mode ?
(conditions depend on
user's application)
No
Yes
END
Go
- 17 -
W78E58B/W78E058B
Procedure of Updating
the 32KB APROM
Is F04KBOOT Mode?
(CHPCON.7=1)
Yes
End of Programming ?
No
Yes
No
Reset the CHPCON Register:
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Yes
Is currently in the
F04KBOOT Mode ?
No
Hardware Reset
to re-boot from
new 32 KB APROM.
(S/W reset is
invalid in F04KBOOT
Mode)
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
MOV SFRCN,#21H
End of erase
operation. CPU will
be wakened by Timer
interrupt.
END
Executing new code
from address
00H in the 32KB APROM.
PGM
- 18 -
W78E58B/W78E058B
6. SECURITY
During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly.
Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM
and those operations on it are described below.
The W78E058B has a Security Register that can be accessed in programming mode. Those bits of
the Security Registers can not be changed once they have been programmed from high to low. They
can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the
LDROM space.
B7 Reserved
B2 B1 B0
Security Bits
0000h
32KB On-chip ROM
Program Memory
0FFFh
Reserved
Reserved
Security Register
APROM
7FFFh
FFFFh
Lock Bit
This bit is used to protect the customer's program code in the W78E058B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Security Register can not be accessed again.
6.2
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
- 19 -
W78E58B/W78E058B
6.3
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
6.4
Oscillator Control
W78E058B/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and
C1, C2 may need some adjustment while running at lower gain.
- 20 -
W78E58B/W78E058B
7. ELECTRICAL CHARACTERISTICS
7.1
SYMBOL
MIN.
MAX.
UNIT
VDD VSS
-0.3
+6.0
Input Voltage
VIN
VSS -0.3
VDD +0.3
Operating Temperature
TA
70
Storage Temperature
TST
-55
+150
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
7.2
D.C. Characteristics
PARAMETER
SYM.
SPECIFICATION
MIN.
MAX.
UNIT
TEST CONDITIONS
Operating Voltage
VDD
4.5
5.5
RST = 1, P0 = VDD
Operating Current
IDD
20
mA
No load
VDD = 5.5V
IIDLE
mA
Idle mode
VDD = 5.5V
IPWDN
50
Power-down mode
VDD = 5.5V
Input Current
P1, P2, P3, P4
IIN1
-50
+10
VDD = 5.5V
VIN = 0V or VDD
Input Current
RST
IIN2
-10
+300
VDD = 5.5V
0V < VIN < VDD
ILK
-10
+10
VDD = 5.5V
0V < VIN < VDD
ITL[*4]
-500
VDD = 5.5V
VIN = 2.0V
VIL1
0.8
VDD = 4.5V
V IL2
0.8
VDD = 4.5V
Idle Current
Power Down Current
- 21 -
W78E58B/W78E058B
D.C. Characteristics, continued
PARAMETER
[*3]
Sink current
P1, P3, P4
Sink current
P0, P2, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
Output High Voltage
P0, ALE, PSEN
[*3]
Source Current
P1, P2, P3, P4
Source Current
P0, P2, ALE, PSEN
SYM.
SPECIFICATION
TEST CONDITIONS
MIN.
MAX.
UNIT
V IL3
0.8
VDD = 4.5V
VIH1
2.4
VDD +0.2
VDD = 5.5V
VIH2
3.5
VDD +0.2
VDD = 5.5V
VIH3
3.5
VDD +0.2
VDD = 5.5V
VOL1
0.45
VOL2
0.45
Isk1
12
mA
Isk2
10
20
mA
VOH1
2.4
VOH2
2.4
Isr1
-120
-250
Isr2
-8
-20
mA
VDD = 4.5V
IOL = +2 mA
VDD = 4.5V
IOL = +4 mA
VDD = 4.5V
VIN = 0.45V
VDD = 4.5V
VIN = 0.45V
VDD = 4.5V
IOH = -100 A
VDD = 4.5V
IOH = -400 A
VDD = 4.5V
VIN = 2.4V
VDD = 4.5V
VIN = 2.4V
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
- 22 -
W78E58B/W78E058B
7.3
A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a 20 nS variation. The numbers below represent the performance
expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
7.3.1
XTAL1
T CH
T CL
F OP,
PARAMETER
TCP
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
FOP
40
MHz
Clock Period
TCP
25
nS
Clock High
TCH
10
nS
Clock Low
TCL
10
nS
MAX.
UNIT
NOTES
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
7.3.2
SYMBOL
MIN.
TYP.
TAAS
1 TCP-
nS
TAAH
1 TCP-
nS
1, 4
TAPL
1 TCP-
nS
TPDA
2 TCP
nS
TPDH
1 TCP
nS
TPDZ
1 TCP
nS
TALW
2 TCP-
2 TCP
nS
TPSW
3 TCP-
3 TCP
nS
Notes:
1. P0.0 P0.7, P2.0 P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
- 23 -
W78E58B/W78E058B
7.3.3
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
TDAR
3 TCP-
3 TCP+
nS
1, 2
TDDA
4 TCP
nS
TDDH
2 TCP
nS
TDDZ
2 TCP
nS
RD Pulse Width
TDRD
6 TCP-
6 TCP
nS
Notes:
1. Data memory access time is 8 TCP.
2. "" (due to buffer driving delay and wire loading) is 20 nS.
7.3.4
SYMBOL
MIN.
TYP.
MAX.
UNIT
TDAW
3 TCP-
3 TCP+
nS
TDAD
1 TCP-
nS
TDWD
1 TCP-
nS
WR Pulse Width
TDWR
6 TCP-
6 TCP
nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
7.3.5
SYMBOL
MIN.
TYP.
MAX.
UNIT
TPDS
1 TCP
nS
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 24 -
W78E58B/W78E058B
8. TIMING WAVEFORMS
8.1
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
TALW
ALE
TAPL
PSEN
TPSW
TAAS
PORT 2
TPDA
TAAH
TPDH, TPDZ
PORT 0
Code
8.2
A0-A7
Data
A0-A7
Code
A0-A7
Data
A0-A7
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
T DAR
T DDA
T DDH, T DDZ
RD
T DRD
- 25 -
W78E58B/W78E058B
8.3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
XTAL1
ALE
PSEN
PORT 2
PORT 0
A8-A15
A0-A7
DATA OUT
WR
T DWR
T DAW
8.4
T DWD
TDAD
S5
S6
S1
XTAL1
ALE
TPDS
T PDA
TPDH
DATA OUT
PORT
INPUT
SAMPLE
- 26 -
S3
W78E58B/W78E058B
9. TYPICAL APPLICATION CIRCUITS
9.1
VDD
31
19
XTAL1
R 18
XTAL2
10 u
CRYSTAL
8.2 K
9
C1
EA
C2
RST
INT0
12
13
14
15
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0 3
AD1 4
AD2 7
AD3 8
AD4 13
AD5 14
AD6 17
AD7 18
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
A15
GND 1
RD
WR
PSEN
ALE
TXD
RXD
17
16
29
30
11
10
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
OC
11 G
74LS373
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND 20 CE
22
OE
27512
W78E58B/W78E058B
Figure A
CRYSTAL
C1
C2
6 MHz
47P
47P
16 MHz
30P
30P
24 MHz
15P
10P
40MHz
5P
5P
6.8K
- 27 -
W78E58B/W78E058B
9.2
31
19
10 u
8.2 K
OSCILLATOR
EA
XTAL1
18
XTAL2
RST
12
13
14
15
1
2
3
4
5
6
7
8
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
RD
WR
17
16
29
30
11
10
PSEN
ALE
TXD
RXD
AD0 3
AD1 4
AD2 7
AD3 8
AD4 13
AD5 14
AD6 17
AD7 18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND 1 OC
11 G
74LS373
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND 20
22
27
CE
OE
WR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
20256
W78E58B/W78E058B
Figure B
- 28 -
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
W78E58B/W78E058B
10. PACKAGE DIMENSIONS
10.1 40-pin DIP
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
eA
S
20
1
S
c
A1
Base Plane
Seating Plane
L
B
e1
eA
B1
5.334
0.210
0.010
0.254
3.81
1.219 1.27
2.055 2.070
52.20 52.58
3.937 4.064
1.372
2.54
3.302 3.556
15
2.794
15
2.286
Notes:
A A2
Dimension in inchDimension in mm
Min. Nom. Max. Min. Nom. Max.
44
40
Symbol
7
39
17
HE
GE
29
18
28
b
b1
4.699
0.508
0.66
0.711 0.813
1.27
BSC
2.54 2.794
0.004
0.10
0.185
0.020
Notes:
A2 A
Seating Plane
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
A1
y
GD
- 29 -
W78E58B/W78E058B
10.3 44-pin PQFP
HD
Dimension in inch
Symbol
34
44
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
33
E HE
11
12
22
Dimension in mm
---
---
---
0.002
0.01
0.02
0.05
0.25
0.5
0.075
0.081
0.087
1.90
2.05
2.20
0.01
0.014
0.018
0.25
0.35
0.45
0.004
0.006
0.010
0.101
0.152
0.254
0.390
0.394
0.398
9.9
10.00
10.1
0.390
0.394
0.398
9.9
10.00
10.1
0.025
0.031
0.036
0.635
0.80
0.952
0.510
0.520
0.530
12.95
13.2
13.45
0.510
0.520
0.530
12.95
13.2
13.45
0.025
0.031
0.037
0.65
0.8
0.95
0.051
0.063
0.075
1.295
1.6
1.905
---
0.08
0.003
0
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
c
A2 A
Seating Plane
See Detail F
A1
y
L
L1
Detail F
- 30 -
---
W78E58B/W78E058B
11. APPLICATION NOTES
11.1 In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W78E058B ROM
microcontroller. In this example, microcontroller will boot from 32KB APROM bank and waiting for a
key to enter in-system programming mode for re-programming the contents of 32KB APROM. While
entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM
bank. The loader program erases the 32KB APROM then reads the new code data from external
SRAM buffer (or through other interfaces) to update the 32KB APROM.
EXAMPLE 1:
;*******************************************************************************************************************
;* Example of 32K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system
;* programming mode for updating the content of APROM code else executes the current ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON
CHPENR
SFRAL
SFRAH
SFRFD
SFRCN
EQU
EQU
EQU
EQU
EQU
EQU
BFH
F6H
C4H
C5H
C6H
C7H
ORG
0H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR
TR0
; TR0 = 0, STOP TIMER0
MOV
TL0, R6
MOV
TH0, R7
RETI
;************************************************************************
;* 32K APROM MAIN PROGRAM
;************************************************************************
ORG 100H
MAIN_32K:
MOV A, P1
; SCAN P1.0
ANL A, #01H
CJNE A, #01H, PROGRAM_32K; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE
PROGRAM_32K:
MOV CHPENR, #87H
MOV CHPENR, #59H
MOV CHPCON, #03H
- 31 -
W78E58B/W78E058B
MOV TCON, #00H
MOV IP, #00H
MOV IE, #82H
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TMOD, #01H
MOV TCON, #10H
MOV PCON, #01H
; TR = 0 TIMER0 STOP
; IP = 00H
; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
; TL0 = F0H
; TH0 = FFH
; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMING
;********************************************************************************
;* Normal mode 32KB APROM program: depending user's application
;********************************************************************************
NORMAL_MODE:
.
.
.
.
EXAMPLE 2:
;******************************************************************************************************************************
Example of 4 KB LDROM program: This loader program will erase the 32KB APROM first, then reads the new ;*
code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz
;*****************************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON
CHPENR
SFRAL
SFRAH
SFRFD
SFRCN
ORG
LJMP
EQU
EQU
EQU
EQU
EQU
EQU
000H
100H
BFH
F6H
C4H
C5H
C6H
C7H
;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0
; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI
;************************************************************************
;* 4KB LDROM MAIN PROGRAM
;************************************************************************
ORG 100H
- 32 -
W78E58B/W78E058B
MAIN_4K:
MOV SP, #C0H
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE.
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV A, CHPCON
ANL A, #80H
CJNE A, #80H, UPDATE_32K ; CHECK F04KBOOT MODE ?
MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE
MOV TCON, #00H
MOV TMOD, #01H
MOV IP, #00H
MOV IE, #82H
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TCON, #10H
MOV PCON, #01H
UPDATE_32K:
MOV CHPENR, #00H
MOV TCON, #00H
MOV IP, #00H
MOV IE, #82H
MOV TMOD, #01H
MOV R6, #E0H
;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN, #0H
; READ 32KB APROM MODE
MOV SFRAH, #0H
; START ADDRESS = 0H
MOV SFRAL, #0H
MOV R6, #FEH
; SET TIMER FOR READ OPERATION, ABOUT 1.5 S.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
BLANK_CHECK_LOOP:
SETB TR0
; ENABLE TIMER 0
MOV PCON, #01H
; ENTER IDLE MODE
MOV A, SFRFD
; READ ONE BYTE
CJNE A, #FFH, BLANK_CHECK_ERROR
- 33 -
W78E58B/W78E058B
INC SFRAL
; NEXT ADDRESS
MOV A, SFRAL
JNZ BLANK_CHECK_LOOP
INC SFRAH
MOV A, SFRAH
CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH
JMP PROGRAM_32KROM
BLANK_CHECK_ERROR:
MOV P1, #F0H
MOV P3, #F0H
JMP $
;*******************************************************************************
;* RE-PROGRAMMING 32KB APROM BANK
;*******************************************************************************
PROGRAM_32KROM:
MOV DPTR, #0H
; THE ADDRESS OF NEW ROM CODE
MOV R2, #00H
; TARGET LOW BYTE ADDRESS
MOV R1, #00H
; TARGET HIGH BYTE ADDRESS
MOV DPTR, #0H
; EXTERNAL SRAM BUFFER ADDRESS
MOV SFRAH, R1
; SFRAH, TARGET HIGH ADDRESS
MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 32K)
MOV R6, #BEH
; SET TIMER FOR PROGRAMMING, ABOUT 50 S.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
PROG_D_32K:
MOV SFRAL, R2
MOVX A, @DPTR
MOV SFRFD, A
MOV TCON, #10H
MOV PCON, #01H
INC DPTR
INC R2
CJNE R2, #0H, PROG_D_32K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, PROG_D_32K
;*****************************************************************************
; * VERIFY 32KB APROM BANK
;*****************************************************************************
MOV R4, #03H
; ERROR COUNTER
MOV R6, #FEH
; SET TIMER FOR READ VERIFY, ABOUT 1.5 S.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV DPTR, #0H
; The start address of sample code
MOV R2, #0H
; Target low byte address
MOV R1, #0H
; Target high byte address
MOV SFRAH, R1
; SFRAH, Target high address
MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE)
- 34 -
W78E58B/W78E058B
READ_VERIFY_32K:
MOV SFRAL, R2
; SFRAL(C4H) = LOW ADDRESS
MOV TCON, #10H
; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H
INC R2
MOVX A, @DPTR
INC DPTR
CJNE A, SFRFD, ERROR_32K
CJNE R2, #0H, READ_VERIFY_32K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, READ_VERIFY_32K
;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR, #87H
; CHPENR = 87H
MOV CHPENR, #59H
; CHPENR = 59H
MOV CHPCON, #83H
; CHPCON = 83H, SOFTWARE RESET.
ERROR_32K:
DJNZ R4, UPDATE_32K
.
.
.
.
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W78E58B/W78E058B
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A3
March, 2002
Formerly issued
A4
June, 2004
A5
34
A6
June 7, 2005
A7
October 3, 2006
A8
December 4, 2006
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Taipei Office
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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