SIMPLIFICATION OF BOOLEAN FUNCTION

OBJECTIVES
 To construct a given circuit and obtain its truth table.
 To obtain the simplified Boolean function of the given circuit by means of a K-map.
 To design and construct a circuit that implements the simplified Boolean function using
a minimum number of NAND gates.
 To verify that the original circuit and the one derived from the simplified Boolean
function produce identical logic level outputs for all possible input combinations.

MATERIALS
 Alexan Digital Trainer
 two 7400 quad two-input NAND gate
 one 7410 tri three-input NAND gate
 insulated connecting wires
 cutter or scissors

Figure 7-1 Circuit diagram—with pin assignments and logic gate analysis—
for the implementation of the original circuit to be simplified
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7400 7410

Figure 7-2. Connection diagram of the circuit in Figure 7-1

PROCEDURE
Figure 7-1 shows the original logic diagram requiring both a 7400 and a 7410 IC. This circuit is
constructed on the digital trainer as shown in Figure 7-2, and a truth table is generated based
on the circuit’s logic level outputs for all eight possible combinations of the three inputs 𝑥, 𝑦,
and 𝑧. The results of this initial set of observations are illustrated in Figure 7-3, and
consequently interpreted in Table 7-1.

As illustrated in Figure 7-3, LED4 of the data status monitor, which corresponds to the
single output of the original logic diagram lights up at four input combinations: 011, 100, 101,
and 111. Since the ON state of LED4 represents a logic-1 output, we obtain the resulting truth
table depicted in Table 7-1. The four 1’s from the last column of the table can be plotted
accordingly in a three-variable K-map as shown in Figure 7-4. The first two 1’s in the second
row can be combined to give the two-literal term 𝑥𝑦′. The remaining two 1’s in the third
column form two adjacent squares that can be represented by the two-literal term 𝑦𝑧. The
simplified function then becomes

𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 .

This simplified function can now be implemented using only a single 7400 quad two-
input NAND gate as shown in Figure 7-5. This new circuit is constructed on the digital trainer as
shown in Figure 7-6. Then, after double-checking all pin connections and supplying power to
the trainer, the ON-OFF state of LED4 is again monitored for all eight possible input
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combinations. The results of this second set of observations are illustrated in Figure 7-7 and
converted into truth values in Table 7-2.

SWITCHES DATA STATUS

INPUT INPUT OUT
S1 S2 S3 LED1 LED2 LED3 LED4

Table 7-1. Truth Table

1
Corresponding to Figure 7-3

2 INPUT OUTPUT
D1 D2 D3 IN4
3
𝒙 𝒚 𝒛 𝑭

4 0 0 0 0
0 0 1 0
5 0 1 0 0
0 1 1 1
6
1 0 0 1
1 0 1 1
7
1 1 0 0
D1 D2 D3 IN1 IN2 IN3 IN4
1 1 1 1

Figure 7-3. Output diagram of the

original circuit shown in Figure 7-1

yz
x 00 01 11 10
𝑚0 𝑚1 𝑚3 𝑚2
0 1
𝑚4 𝑚5 𝑚7 𝑚6
1 1 1 1 0

𝒙𝒚′ 𝒚𝒛
Figure 7-4. K-map
corresponding to Table 7-1
Figure 7-5 Circuit diagram—with pin assignments and logic gate
analysis—for the implementation of 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 using a single 7400 quad
two-input NAND gate

7400

Figure 7-6. Connection diagram of the circuit in Figure 7-5

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RESULTS AND DISCUSSION

SWITCHES DATA STATUS

INPUT INPUT OUT
S1 S2 S3 LED1 LED2 LED3 LED4

0
Table 7-2. Truth Table
of 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧
1

𝒙 𝒚 𝒛 𝒙𝒚′ 𝒚𝒛 𝑭
2
0 0 0 0 0 0

3 0 0 1 0 0 0
0 1 0 0 0 0
4 0 1 1 0 1 1
1 0 0 1 0 1
5 1 0 1 1 0 1
1 1 0 0 0 0
6
1 1 1 0 1 1
7

D1 D2 D3 IN1 IN2 IN3 IN4

Figure 7-7. Output diagram of the

simplified circuit 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧

As expected, the circuit derived from the simplified Boolean function 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧

produces exactly the same logic level outputs for all eight possible combinations of the three
input variables 𝑥, 𝑦, and 𝑧 . We can further verify this result by generating the (theoretical)
truth table for 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 , as shown in Table 7-2. Again, as expected, the truth values of 𝐹
consist of four 1’s corresponding to the minterms 𝑚3 , 𝑚4 , 𝑚5 , and 𝑚7 . This proves that the
original and the simplified logic diagrams shown in Figures 7.1 and 7-5, respectively,
implement the same Boolean function and are therefore equivalent.

CONCLUSION

The results of this experiment prove that a complex logic diagram consisting of several gates or
ICs can be reduced to a simpler logic diagram that consists of fewer gates or ICs but still
produces the same output.