Ec25&Ec21&Ec20 R2.0: Quecopen Developer Guide

EC25&EC21&EC20 R2.
0
QuecOpen Developer Guide
LTE Module Series
Rev. EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide_V1.0
Date: 2017-05-18
www.quectel.com
LTE Module Series
EC25&EC21&EC20 R2.0 QuecOpen Developer Guide
Our aim is to provide customers with timely and comprehensive service. For any
assistance, please contact our company headquarters:
Quectel Wireless Solutions Co., Ltd.

Office 501, Building 13, No.99, Tianzhou Road, Shanghai, China, 200233
Tel: +86 21 5108 6236
Email: [email protected]
Or our local office. For more information, please visit:
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http://www.quectel.com/support/salesupport.aspx
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For technical support, or to report documentation errors, please visit:
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http://www.quectel.com/support/techsupport.aspx
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Or email to: [email protected]
GENERAL NOTES
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QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION
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PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT
TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT
MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT
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ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR
RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO
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CHANGE WITHOUT PRIOR NOTICE.
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COPYRIGHT
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THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF
QUECTEL CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS
DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT
PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS
ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL
OR DESIGN.
Copyright © Quectel Wireless Solutions Co., Ltd. 2017. All rights reserved.
EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide Confidential / Released 1 / 50

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About the Document
History
Revision Date
t el Author Description
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1.0 2017-05-18 Stanley YONG Initial
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Contents
About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 3
Figure Index ................................................................................................................................................. 5
Table Index ................................................................................................................................................... 6
1 Introduction .......................................................................................................................................... 7
1.1. Applicative Modules ................................................................................................................ 7
2 QuecOpenTM Platform .......................................................................................................................... 8
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2.1. System Architecture ................................................................................................................ 8
2.2. Open System Resources ........................................................................................................ 9
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2.2.1. Processor ......................................................................................................................... 9
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2.2.2. Host System ..................................................................................................................... 9
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2.2.3. Flash Space...................................................................................................................... 9
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2.2.4. RAM Space .................................................................................................................... 10
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2.3. Open Hardware Resources ................................................................................................... 10
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2.3.1. UARTs ............................................................................................................................ 13
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2.3.2. GPIOs ............................................................................................................................. 14
2.3.3. Interrupts ........................................................................................................................ 14
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2.3.4. I2C .................................................................................................................................. 14
2.3.5. SPI .................................................................................................................................. 14
2.3.6. ADC ................................................................................................................................ 14
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2.3.7. PCM................................................................................................................................ 14
2.3.8. SDIO ............................................................................................................................... 14
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2.3.9. SGMII ............................................................................................................................. 15
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2.3.10. USB ................................................................................................................................ 15
3 Work with QuecOpenTM ..................................................................................................................... 16
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3.1. Set up Host Environment ...................................................................................................... 17
3.1.1. System Requirements .................................................................................................... 17
3.1.2. Install USB Driver ........................................................................................................... 17
3.1.3. Install and Set up ADB Driver on PC ............................................................................. 17
3.1.4. Install Cross Compiler .................................................................................................... 19
3.2. Synchronize SDK and Module .............................................................................................. 19
3.3. Compilation............................................................................................................................ 20
3.3.1. Compiling ....................................................................................................................... 20
3.3.2. Compiling Output ........................................................................................................... 20
3.4. Download ............................................................................................................................... 21
3.4.1. During Development Phase ........................................................................................... 21
3.4.1.1. With ADB .............................................................................................................. 21
3.4.1.2. With fastboot ......................................................................................................... 22
3.4.2. For Production ................................................................................................................ 22
3.5. Launch Application ................................................................................................................ 24

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3.6. Debug Application.................................................................................................................. 24
4 Programming Reference ................................................................................................................... 25

4.1. System ................................................................................................................................... 25
4.1.1. Time................................................................................................................................ 25
4.1.2. Timer .............................................................................................................................. 25
4.1.3. Multitasking .................................................................................................................... 27
4.2. AT & URC .............................................................................................................................. 27
4.3. I/O Interfaces ......................................................................................................................... 28
4.3.1. GPIOs ............................................................................................................................. 28
4.3.2. EINT ............................................................................................................................... 28
4.3.3. UARTs ............................................................................................................................ 29
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4.3.3.1. Pin 63/66 as UART ............................................................................................... 30
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4.3.3.2. Pin 38/39 as UART ............................................................................................... 31
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4.3.3.3. Pin 67/68 as UART ............................................................................................... 31
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4.3.3.4. Programming reference ........................................................................................ 32
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4.3.4. ADC ................................................................................................................................ 32
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4.3.5. I2C .................................................................................................................................. 33
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4.3.6. SPI .................................................................................................................................. 34
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4.3.6.1. SPI Mode .............................................................................................................. 34
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4.3.6.2. Install SPI Driver ................................................................................................... 35
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4.3.6.3. SPI Parameters .................................................................................................... 36
4.4. File System ............................................................................................................................ 37
4.5. SD Card/eMMC Flash ........................................................................................................... 38
4.6. Audio...................................................................................................................................... 39
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4.7. TTS ........................................................................................................................................ 39
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4.8. Voice Call ............................................................................................................................... 40
4.9. SMS ....................................................................................................................................... 40
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4.10. Network Service .................................................................................................................... 40
4.11. Data Service .......................................................................................................................... 40
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4.11.1. DSI_NetCtrl .................................................................................................................... 41
4.11.2. Sockets ........................................................................................................................... 43
4.12. GNSS..................................................................................................................................... 45
4.13. Wi-Fi ...................................................................................................................................... 45
4.14. (U)SIM Card .......................................................................................................................... 46
5 Customization .................................................................................................................................... 47
5.1. Pin Multiplexing Function ...................................................................................................... 47
5.1.1. With Linux Kernel Code ................................................................................................. 47
5.1.2. Without Linux Kernel Code ............................................................................................ 47
5.2. Rootfs .................................................................................................................................... 48
6 Appendix A References..................................................................................................................... 49

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Figure Index
TM
FIGURE 1: QUECOPEN ARCHITECTURE ..................................................................................................... 8
TM
FIGURE 2: HOW TO START WORKING WITH QUECOPEN ....................................................................... 16
FIGURE 3: BUILD DIRECTORY ....................................................................................................................... 21
FIGURE 4: DOWNLOAD DIRECTORY ............................................................................................................. 21
FIGURE 5: DOWNLOAD APPLICATION VIA QFLASH .................................................................................... 23
FIGURE 6: SPI 4-LINE MODE .......................................................................................................................... 34
FIGURE 7: SPI 6-LINE MODE .......................................................................................................................... 35
FIGURE 8: SPI 8 CHANNELS ........................................................................................................................... 36
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FIGURE 9: DISASSEMBLE BOOT.IMG ............................................................................................................ 48
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Table Index
TABLE 1: DATA STORAGE PLACES FOR DEVELOPERS ................................................................................ 9

TABLE 2: MULTIPLEXING PINS ....................................................................................................................... 10
TABLE 3: UART PINS........................................................................................................................................ 29
TABLE 4: UART TTY ......................................................................................................................................... 30
TABLE 5: I2C PINS ............................................................................................................................................ 33
TABLE 6: SPI PINS ........................................................................................................................................... 34
TABLE 7: RELATED DOCUMENTS .................................................................................................................. 49
TABLE 8: TERMS AND ABBREVIATIONS ........................................................................................................ 49
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1 Introduction
Quectel QuecOpenTM is an open embedded platform that is built on Linux system. It is designed to
simplify the development for IoT (Internet of Things) applications.
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This guide document mainly provides the following information for developers:
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 General information about QuecOpenTM platform
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 How to start working with QuecOpenTM
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 How to build an application

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How to compile an application
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 How to download an application
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 How to get the application working
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1.1. Applicative Modules
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QuecOpenTM is applicable to the following Quectel LTE modules:
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 EC25
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 EC21
 EC20 R2.0
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2 QuecOpenTM Platform
2.1. System Architecture
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Development Command Line SDK Download Utilities
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Environment Tool
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Environment
Compilation
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Middleware
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Multi-Language Support (C, C++, Shell Script)
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C Runtime Library (GCC 4.9)
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File System Utilities Free Open
Linux Distribution Source
Package
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Linux Kernel (3.18)
Little Kernel boot loader (LK)
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Driver BSP
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Figure 1: QuecOpenTM Architecture

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2.2. Open System Resources
2.2.1. Processor
Cortex-A7 1.2GHz, ARMv7.
2.2.2. Host System
Linux system with kernel 3.18.
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2.2.3. Flash Space
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In QuecOpenTM, customer applications and other data are stored in Linux file system. The places that can
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be used by developers are listed in the following table.
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Table 1: Data Storage Places for Developers
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Filesystem Type Size Used Available Use (%) Mounted on
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ubi0:rootfs ubifs 55.8M 36.8M 19.0M 66% /
ubi0:usrfs ubifs 31.9M 868.0K 31.0M 3% /data
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/dev/ubi0_2 ubifs 48.3M 24.0K 45.8M 0% /cache
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As defined in the table above, there are three UBI partitions that can be used to store application images
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or data in Linux file system. They are “rootfs”, “usrfs” and “cache” partitions.
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ubi0:rootfs (/)
The space available is around 19MB.
 ubi0:usrfs (/data)
The space available is around 31MB. And the partition is mounted to /data. By default, customer
applications are put in this partition.
 /dev/ubi0_2 (/cache)
The space available is around 45MB. And it is mounted to /cache by default. However, this UBI partition is
shared with FOTA option, which means FOTA option will erase and write this partition when there is
firmware (such as modem image, or Linux image) upgraded by FOTA. So developers may temporarily
store some data in /dev/ubi0_2. However, do remember the data will be cleaned up when doing upgrade
by FOTA.

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Totally, the fixed flash space (for application and data) is around 50MB (19MB+31MB), and can be
expanded to around 95MB (50MB+45MB). The runtime flash space is around 45MB.
2.2.4. RAM Space
RAM available: 50M bytes
2.3. Open Hardware Resources
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Table 2: Multiplexing Pins
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Combined Pin Multiplexing
Pin Pin Power Wake-up
Reset2)
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Pin Name Interface Remark
Primary Alternate Alternate Interrupt3)
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No. Location Domain
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(default)
Function1) Function 1 Function 2
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BOOT_
1 GPIO1 Edge GPIO_25 -- -- 1.8V B-PD,L ✔
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CONFIG_2
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2 GPIO2 Edge GPIO_10 -- -- 1.8V B-PD,L ✗
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BOOT_
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5 GPIO5 Edge GPIO_24 -- -- 1.8V B-PD,L ✗
CONFIG_1
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11 DBG_RXD Edge DBG_RXD -- -- 1.8V B-PD,L --
Debug
UART
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12 DBG_TXD Edge DBG_TXD -- -- 1.8V B-PD,L --
USIM_ USIM_
13 Edge GPIO_34 -- 1.8V B-PD,L ✔
PRESENCE PRESENCE
SD_CARD_ SD_CARD_D
23 Edge GPIO_26 -- 1.8V B-PD,L ✔
DET ET
24 PCM_IN Edge PCM_IN GPIO_76 -- 1.8V B-PD,L ✔
25 PCM_OUT Edge PCM_OUT GPIO_77 -- 1.8V B-PD,L ✗

PCM
BOOT_
26 PCM_SYNC Edge interface PCM_SYNC GPIO_79 -- 1.8V B-PD,L ✔
CONFIG_7
BOOT_
27 PCM_CLK Edge PCM_CLK GPIO_78 -- 1.8V B-PD,L ✗
CONFIG_8
SDC2_ SDIO2 SDC2_ LOW SD Dedicated

28 Edge -- -- B-PD,L --
DATA3 (SD card DATA3 Voltage: pin

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interface) 1.8V.
HIGH SD
Voltage:
2.85V.
LOW SD
Voltage:
SDC2_ SDC2_ 1.8V. Dedicated

29 Edge -- -- B-PD,L --
DATA2 DATA2 HIGH SD pin
Voltage:
2.85V.
LOW SD
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Voltage:
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30 Edge -- -- B-PD,L --
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Voltage:
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2.85V.
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LOW SD
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Voltage:
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31 Edge -- -- B-PD,L --
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Voltage:
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2.85V.
LOW SD
Voltage:
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1.8V. Dedicated
32 SDC2_CLK Edge SDC2_CLK -- -- B-NP,L --
HIGH SD pin
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Voltage:
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2.85V.
LOW SD
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Voltage:
1.8V. Dedicated
33 SDC2_CMD Edge SDC2_CMD -- -- B-PD,L --
HIGH SD pin
Voltage:
2.85V.
LOW SD
Voltage:
Power,
1.8V.
34 VDD_SDIO Edge VDD_SDIO -- -- L -- Dedicated
HIGH SD
pin
Voltage:
2.85V.
SPI_CS_N_B UART_RTS_
37 SPI_CS_N Edge GPIO_22 1.8V B-PD,L ✔
LSP6 BLSP6
SPI Interface
SPI_MOSI_B UART_TXD_
38 SPI_MOSI Edge GPIO_20 1.8V B-PD,L ✔
LSP6 BLSP6

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SPI_MISO_B UART_RXD_
39 SPI_MISO Edge GPIO_21 1.8V B-PD,L ✔
LSP6 BLSP6
SPI_CLK_ UART_CTS_ BOOT_

40 SPI_CLK Edge GPIO_23 1.8V B-PU,H ✗
BLSP6 BLSP6 CONFIG_4
I2C_SCL_ UART_CTS_
41 I2C_SCL Edge I2C GPIO_7 1.8V B-PD,L ✗
BLSP2 BLSP2
interface,
I2C_SDA_ UART_RTS_
42 I2C_SDA Edge host only GPIO_6 1.8V B-PD,L ✗
BLSP2 BLSP2
UART1_ UART_TXD_ UART_TXD_

63 Edge GPIO_4 1.8V B-PD,L ✗
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TXD UART BLSP2 BLSP2
UART1_ interface UART_RXD_ UART_RXD_

✔
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66 Edge GPIO_5 1.8V B-PD,L
RXD BLSP2 BLSP2
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UART_CTS_
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64 MAIN_CTS Edge GPIO_3 -- 1.8V B-PD,L ✔
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BLSP3
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UART_RTS_
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✗
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65 MAIN_RTS Edge GPIO_2 -- 1.8V B-PD,L
BLSP3
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Main UART
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UART_TXD_
67 MAIN_TXD Edge GPIO_0 -- 1.8V B-PD,L ✗
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BLSP3
UART_RXD_
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68 MAIN_RXD Edge GPIO_1 -- 1.8V B-PD,L ✔
BLSP3
EPHY_ EPHY_ 1.8V/

119 Bottom GPIO_29 -- BH-PD,L ✔
RST_N RST_N 2.85V
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EPHY_ EPHY_
120 Bottom GPIO_30 -- 1.8V B-PD,L ✔
INT_N INT_N
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SGMII_ SGMII_ 1.8V/
121 Bottom GPIO_28 -- BH-PD,L ✔
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DATA DATA 2.85V
1.8V/
122 SGMII_CLK Bottom SGMII_CLK GPIO_27 -- BH-PD,L ✗
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SGMII 2.85V
SGMII_ interface SGMII_ Analog Dedicated

123 Bottom -- -- L --
TX_M TX_M signal pin
SGMII_ SGMII_ Analog Dedicated

124 Bottom -- -- L --
TX_P TX_P signal pin

125 Bottom -- -- L --
RX_P RX_P signal pin

126 Bottom -- -- L --
RX_M RX_M signal pin
SDC1_ SDC1_
DATA3 DATA3
SDIO1
SDC1_ SDC1_
130 Bottom (WLAN GPIO_13 -- 1.8V B-PD,L ✔
DATA2 DATA2
interface)
SDC1_ SDC1_
131 Bottom GPIO_14 -- 1.8V B-PD,L ✗
DATA1 DATA1

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SDC1_ SDC1_
DATA0 DATA0
133 SDC1_CLK Bottom SDC1_CLK GPIO_16 -- 1.8V B-NP,L ✔
134 SDC1_CMD Bottom SDC1_CMD GPIO_17 -- 1.8V B-PD,L ✔
WLAN_ WLAN_
WAKE WAKE
WLAN BOOT_
136 WLAN_EN Bottom WLAN_EN GPIO_38 -- 1.8V B-PD,L ✔
coexistence CONFIG_12
COEX_ control/ COEX_ FORCE_

UART_RXD management UART_RXD USB_BOOT
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COEX_ COEX_ BOOT_
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UART_TXD UART_TXD CONFIG_3
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NOTES
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1)
1. By default, the module pins support the primary function.
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2)
2. “B”: Bidirectional digital with CMOS input
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“BH”: High-voltage tolerant bidirectional digital with CMOS input
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“PD”: Contain an internal pull-down device
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“PU”: Contain an internal pull-up device
“L”: Low level
“H”: High level
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3)
3. All GPIOs support interrupt option. But not all interrupts can wake up the sleeping module.
“✔” means wake-up interrupt is supported, that is, the pin can wake up the sleeping module.
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“✗” means wake-up interrupt is not supported, that is, the pin cannot be used to wake up the
sleeping module.
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4. GPIO_27 ~ GPIO_30 are not available currently.
5. BOOT_CONFIG_xx & FORCE_USB_BOOT means these pins MUST be kept in the “Reset” status
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when powering up the module. Otherwise, the module might not be able to boot properly.
2.3.1. UARTs
QuecOpen module provides four serial ports: one Debug UART and three application UARTs.
 Debug UART: Pin 11/12 (RXD/TXD), used to debug the AP system and QuecOpenTM applications.
 Application UARTs:
a) Main UART: pin 67/68 (TXD/RXD) + pin 64/65 (CTS/RTS).
b) The other two application UART ports: pin 63/66 (TXD/RXD) + pin 41/42 (CTS/ RTS)
pin 38/39 (TXD/RXD) + pin 37/40 (RTS/CTS)
Please see Chapter 4.3.3 for details about how to program these serial interfaces.

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2.3.2. GPIOs
There are more than 30 I/O pins that can be configured as general purpose I/O pins. They are multiplexed
with other functional pins. All GPIO pins can be accessed by API functions.
Please refer to Chapter 4.3.1 for the API functions for programming GPIO.
2.3.3. Interrupts
All pins that can be multiplexed as GPIO can be interrupt pins. However, not all interrupt pins can wake up
the module that is in low-power-consumption mode. Please see the field "Wake-up Interrupt" in Table 2.
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Please refer to Chapter 4.3.2 for the API functions for programming interrupt.
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2.3.4. I2C
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QuecOpen module provides one hardware I2C interface. Please refer to Chapter 4.3.5 for details.
2.3.5. SPI
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QuecOpen module provides one hardware SPI interface. Please refer to Chapter 4.3.6 for details.
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2.3.6. ADC
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There are two analogue input pins that can be ADC. The pin numbers are 45 and 44. Please refer to
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document [2] for the electrical characteristics of ADC interface.
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2.3.7. PCM
QuecOpen module provides a PCM interface. It is designed for audio codec by default. Combined with
I2C interface, the application can control and manage the codec chip using AT+QIIC command or API
functions defined in Chapter 4.3.5.
2.3.8. SDIO
QuecOpen module provides two SDIO interfaces (SDC1 and SDC2). Both of them are 4-bit bidirectional
data bus.
SDC2 is designed for SD card or eMMC flash, and SDC1 is designed for Wi-Fi.

LTE Module Series
2.3.9. SGMII
QuecOpen module provides an SGMII interface.
2.3.10. USB
The USB interface can be mapped into several different functional interfaces, as shown below:
 USB-AT port
 USB-DM port
 USB-NMEA port
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 USB-Modem port
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 USB-Network adapter
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In QuecOpen module, the GNSS NMEA is outputted to application through a virtual serial port instead of
USB-NMEA port by default.
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The USB-DM port can be used to download firmware to module, and debug the module system. So,
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developers MUST design the USB interface for the convenience of downloading and debugging.
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Please refer to document [1] for USB details.
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3 Work with QuecOpenTM

This chapter introduces how to start working with QuecOpenTM. The flow for working with QuecOpenTM is
described as below.
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Before compiling an application, developers need to update some files according to the current firmware
version. Please refer to the following flow diagram and Chapter 3.2 for more details.
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Obtain QuecOpenTM
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Development Data
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(SDK, document, driver, tools)
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Install USB driver
Refer to Chapter 3.1.2
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Install ADB Driver
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Install Cross-Compiler
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Synchronize SDK with Firmware
Start to Compile Applications

Refer to Chapter 3.2
Refer to Chapter 3.3
Figure 2: How to Start Working with QuecOpenTM

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3.1. Set up Host Environment
3.1.1. System Requirements
QuecOpenTM provides the ready-made compilation software package which includes the host operating
system, compiler and the other required tools.
 Operating system
Ubuntu 64-bit OS, version 12.04 or 14.
 Compiler
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arm-oe-linux-gnueabi
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 ADB
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Android Debug Bridge version 1.0.31.
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 Fastboot
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3.1.2. Install USB Driver
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Please refer to document [1] for details about USB driver installation, and make sure the USB interface
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can work normally.
3.1.3. Install and Set up ADB Driver on PC
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ADB can be used to upload or download files between the host computer and QuecOpen module, and
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execute shell commands of the module.
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Please follow the commands below to install ADB on your host system.
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sudo apt-get update
sudo apt-get install android-tools-adb
If the above installation command fails, please try again with the series of commands shown below.
sudo add-apt-repository ppa:nilarimogard/webupd8

sudo apt-get update
sudo apt-get install android-tools-adb
After ADB installation, developers can check whether it is installed successfully by executing adb
command.

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 List ADB devices
sudo adb devices
If the USB device cannot be listed, follow the steps below.
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 Add module USB VID into ADB configuration
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There is a hidden directory name .android in your work directory. Please create the file adb_usb.ini
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in .android directory, and write into the USB VID in a new line.
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cd
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sudo gedit .android/adb_usb.ini &
Or
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sudo vi .android/adb_usb.ini
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Input the USB VID in a new line in the file, for example 0x2C7C. Developers can check the USB VID with
lsusb command.

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Restart ADB Service

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Now the ADB is ready.
3.1.4. Install Cross Compiler
Quectel provides the development environment software package (please consult Quectel Technical
Supports for the compiler). Developers just need to decompress the package
QuecOpen_CrossCompiler.tar.gz:
sudo tar -xf QuecOpen_CrossCompiler.tar.gz -C /opt
After decompression, developers can verify whether the environment is setup properly:
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/opt/ql-oe/sysroots/x86_64-linux/usr/bin/arm-oe-linux-gnueabi/arm-oe-linux-gnueabi-gcc -v
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If the environment is properly setup, the information of GCC version will be shown.
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3.2. Synchronize SDK and Module
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Since the application image (including the customizations on roofs) compiled under SDK environment is
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merged into the Linux file system on QuecOpen module, developers need to do some preprocessing
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before compiling an application to .ubi image.
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 Check the firmware version that is being used on the module with ATI command.
Suppose that the checked firmware version is EC20CEFAR02A01M4G_OCPU.
 Synchronize the following files in /SDK/target/9x07/ with the ones with the same name in the original
firmware package of version EC20CEFAR02A01M4G_OCPU.
File 1: partition.mbn
File 2: mdm9607-perf-boot.img
File 3: mdm-perf-image-mdm9607-perf.tar.gz
File 4: ENPRG9x07.mbn
File 5: NPRG9x07.mbn
Also see READ ME in SDK about this.

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3.3. Compilation
3.3.1. Compiling
In QuecOpenTM, compiling commands are executed in command line. The clean and compiling
commands are defined as below.
sudo ./build.sh clean

sudo ./build.sh new <path of makefile>
QuecOpenTM SDK provides some examples for developers’ reference. The following illustrates an
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example for compiling “hello world”.
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Quectel_QuecOpen_SDK_V1.0/
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├─example
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│ ├─adc
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│ ├─at
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│ ├─gpio
t
│ ├─hello_world
u
…
Q ide n
Developers need to enter the root directory of SDK, and execute the following command to compile
hellowrld.c. After compiling, an executable file AppImageBinV01 is generated in SDK/build/.
sudo ./build.sh new example/hello_world
n f
3.3.2. Compiling Output
o
In command-line, the processing information of compiler will be outputted during compiling. All
WARNINGs and ERRORs are recorded in /SDK/build/build.log.
C
If the compiling succeeds, the executable program file will be outputted in build/. Additionally, the
compilation environment will create a .ubi file in build/, and generate the downloadable software package
for QFlash tool in download/. Totally, the outputted information includes:
 Executable file
 .ubi file
 download/ directory for QFlash tool

LTE Module Series
Figure 3: Build Directory
t el
e c ia l
u n t
Figure 4: Download Directory
3.4. Download
Q ide
n f
3.4.1. During Development Phase
o
3.4.1.1. With ADB
C
Developers can upload the application executable file to the file system of module Linux system by ADB
shell command.
sudo adb push <local path> <module path>
An example is shown below:
adb push /home/stanley/MyWork/Quectel_QuecOpen_V1.0/example/helloWorld/hellolworld /home/root/
The executing result is:
stanley@stanley-OptiPlex-7020:~/MyWork/Quectel_QuecOpen_V1.0/example/helloWorld$ sudo adb

push /home/stanley/MyWork/Quectel_QuecOpen_V1.0/example/helloWorld/helloworld /home/root
83 KB/s (3692 bytes in 0.043s)
stanley@stanley-OptiPlex-7020:~/MyWork/Quectel_QuecOpen_V1.0/example/helloWorld$

LTE Module Series
3.4.1.2. With fastboot
Developers can download the .ubi file (in build/ directory) to QuecOpen module’s flash, and then reset the
module. The application will be loaded and run automatically.
3.4.2. For Production
In order to improve the production efficiency, Quectel provides the special fixture and download tool which
can download firmware to several modules synchronously. Mass production customers can consult
Quectel Technical Supports for that if needed.
l
Of course, developers can also download the application (.ubi) during the stage of development.
t e
The download port is USB-DM interface.
e c ia l
u n t
Q ide
n f
Co

LTE Module Series
t el
e c ia l
u n t
Q ide
n f
Co
Figure 5: Download Application via QFlash
QuecOpen module will boot automatically after the download finishes, and the application will be loaded
and run.

LTE Module Series
3.5. Launch Application
If developers want to download the executable file, they can use adb shell to login the Linux console of
QuecOpen module and run the executable program directly.
stanley@stanley-OptiPlex-7020:~/MyWork/Quectel_QuecOpen_V1.0/example/helloWorld$ sudo adb

shell
/ # ls /home/root/ -l
total 4
-rwxrwxrwx 1 root root 3692 Jul 5 2016 helloworld
/ # ./home/root/helloworld
l
<Hello QuecOpen !>
e
atoi("19.7")=19
t
/#
c l
If the application (.ubi) is downloaded by PC tool QFlash, the application will be loaded and run
e ia
automatically after the downloading finishes.
u t
If the application (.ubi) is downloaded by fastboot, there is a need to reset the module to run the
n
application by the system automatically.
Q ide
3.6. Debug Application
n f
Generally, there are two ways to debug application.
o
 Output log message to standard output device by calling print(). And developers can catch the log
through Debug UART or adb shell.
C
 Output log message through UART interface.

LTE Module Series
4 Programming Reference
4.1. System
l
4.1.1. Time
e
 Relevant header files
t l
#include <time.h>
e c a

i
API functions
u t
/* Return a string in the form of "Day Mon dd hh:mm:ss yyyy\n" that is the representation of TP in this
n
format. */
Q ide
extern char *asctime (const struct tm *__tp);
/* Get resolution of clock CLOCK_ID. */
f
extern int clock_getres (clockid_t __clock_id, struct timespec *__res);
n
/* Get current value of clock CLOCK_ID and store it in TP. */
o
extern int clock_gettime (clockid_t __clock_id, struct timespec *__tp);
C
/* Set clock CLOCK_ID to value TP. */
extern int clock_settime (clockid_t __clock_id, const struct timespec *__tp);
 Example
Please see example/time/example_time.c for details.
4.1.2. Timer
#include <sys/timerfd.h>
#include <time.h>
#include <unistd.h>

LTE Module Series
 API functions
/* Return file descriptor for new interval timer source. */
extern int timerfd_create (clockid_t __clock_id, int __flags);
/* Set next expiration time of interval timer source UFD to UTMR. If FLAGS has the
TFD_TIMER_ABSTIME flag set the timeout value is absolute. Optionally return the old expiration time in
OTMR. */
extern int timerfd_settime (int __ufd, int __flags,

const struct itimerspec *__utmr,
struct itimerspec *__otmr);
el
/* Return the next expiration time of UFD. */
t
extern int timerfd_gettime (int __ufd, struct itimerspec *__otmr);
c a l
/* Read NBYTES into BUF from FD. Return the number read, -1 for errors or 0 for EOF. */
e t i
extern ssize_t read (int __fd, void *__buf, size_t __nbytes);
u n
/* Create new per-process timer using CLOCK_ID. */
Q ide
extern int timer_create (clockid_t __clock_id,
struct sigevent *__restrict __evp,
timer_t *__restrict __timerid);
f
/* Set timer TIMERID to VALUE, returning old value in OVALUE. */
n
extern int timer_settime (timer_t __timerid, int __flags,
o
const struct itimerspec *__restrict __value,
struct itimerspec *__restrict __ovalue);
C
/* Get current value of timer TIMERID and store it in VALUE. */
extern int timer_gettime (timer_t __timerid, struct itimerspec *__value);
 Example
Please see example/timer/example_timer.c for details.

LTE Module Series
4.1.3. Multitasking
#include <pthread.h>
 API functions
/* Create a new thread, starting with execution of START-ROUTINE getting passed ARG. Creation
attributed come from ATTR. The new handle is stored in *NEWTHREAD. */
extern int pthread_create (pthread_t *__restrict __newthread,
l
const pthread_attr_t *__restrict __attr,
void *(*__start_routine) (void *),
e
void *__restrict __arg) __THROWNL __nonnull ((1, 3));
c t l
/* Terminate calling thread. The registered cleanup handlers are called via exception handling so we
cannot mark this function with __THROW. */
e ia
extern void pthread_exit (void *__retval) __attribute__ ((__noreturn__));
u n t
/* Make calling thread wait for termination of the thread TH. The exit status of the thread is stored in
Q ide
*THREAD_RETURN, if THREAD_RETURN is not NULL. */
extern int pthread_join (pthread_t __th, void **__thread_return);
f
Example
Please see example/pthread/example_pthread.c for details.
4.2. AT & URC
o n
C
The tty device /dev/smd8 is designed to be AT port. Developers may simply open this device file and write
AT commands through it.
Also, all URC messages are outputted through this port.
#define QUEC_AT_PORT "/dev/smd8"

smd_fd = open(QUEC_AT_PORT, O_RDWR | O_NONBLOCK | O_NOCTTY);
iRet = write(smd_fd, "AT\r\n", 4);
 Example
Please see example/at/example_at.c for details.

LTE Module Series
4.3. I/O Interfaces
All kinds of multiplexing interfaces and the quantity of each kind are defined in document [3].
4.3.1. GPIOs
All programmable GPIO pins are defined in Table 2. Except the dedicated pins, all other pins can be
programmed as GPI or GPO.
l
#include “ql_om”
e
#include “ql_gpio_def.h”
t
#include “ql_gpio.h”
c l
#include “gpioSysfs.h”
e ia
 API functions
u t
int Ql_GPIO_Init(Enum_PinName pinName,
n
Enum_PinDirection dir,
Q ide
Enum_PinLevel level,
Enum_PinPullSel pullSel
);
int Ql_GPIO_SetLevel(Enum_PinName pinName, Enum_PinLevel level);
f
int Ql_GPIO_GetLevel(Enum_PinName pinName);
n
int Ql_GPIO_SetDirection(Enum_PinName pinName, Enum_PinDirection dir);
int Ql_GPIO_GetDirection(Enum_PinName pinName);
o
int Ql_GPIO_SetPullSelection(Enum_PinName pinName, Enum_PinPullSel pullSel);
int Ql_GPIO_GetPullSelection(Enum_PinName pinName);
C
int Ql_GPIO_Uninit(Enum_PinName pinName);
 Example
Please see example/gpio/example_gpio.c for details.
4.3.2. EINT
All programmable GPIO pins are defined in Table 2. Except the dedicated pins, all other pins can be
programmed as GPI and interrupt.
#include "ql_oe.h"
#include "ql_eint.h"

LTE Module Series
 API functions
int Ql_EINT_Open(Enum_PinName eintPinName);

int Ql_EINT_Enable(Enum_PinName eintPinName, Enum_EintType eintType);
int Ql_EINT_Disable(Enum_PinName eintPinName);
int Ql_EINT_Close(Enum_PinName eintPinName);
 Example
Please see example/eint/example_eint.c for details.
l
4.3.3. UARTs
e
QuecOpen module provides one debug UART and three UART interfaces for application. All of the three
t
application UARTs support hardware handshaking. The pins are defined in the table below.
e c a l
Table 3: UART Pins
u t i
n
Pin Name Interface Reset Remark
No. Location Primary Alternate Alternate Domain Interrupt
Q ide
(default)
Function Function 1 Function 2
SPI_CS_N_ UART_RTS_
BLSP6 BLSP6
f
SPI_MOSI_ UART_TXD_
38 SPI_MOSI Edge GPIO_20 1.8V B-PD,L ✔
BLSP6 BLSP6
n
SPI Interface
SPI_MISO_ UART_RXD_
BLSP6 BLSP6
o
C
I2C_SCL_ UART_CTS_
41 I2C_SCL Edge GPIO_7 1.8V B-PD,L ✗
I2C interface, BLSP2 BLSP2
host only I2C_SDA_ UART_RTS_

42 I2C_SDA Edge GPIO_6 1.8V B-PD,L ✗
BLSP2 BLSP2
UART_TXD_
63 UART1_TXD Edge GPIO_4 -- 1.8V B-PD,L ✗
UART BLSP2
interface UART_RXD_
66 UART1_RXD Edge GPIO_5 -- 1.8V B-PD,L ✔
BLSP2
UART_CTS_BL
64 MAIN_CTS Edge GPIO_3 -- 1.8V B-PD,L ✔
SP3
Main UART UART_RTS_BL

65 MAIN_RTS Edge GPIO_2 -- 1.8V B-PD,L ✗
SP3
UART_TXD_BL
67 MAIN_TXD Edge GPIO_0 -- 1.8V B-PD,L ✗
SP3

LTE Module Series
UART_RXD_
68 MAIN_RXD Edge GPIO_1 -- 1.8V B-PD,L ✔
BLSP3
The tty device for UART interfaces are defined as below.
Table 4: UART tty
Pin No. Pin Name Signal Direction tty Device Remark
63 UART1_TXD UART TX
/dev/ttyHSL1
l
66 UART1_RXD UART RX
e
38 SPI_MOSI UART TX
t
Need to configure device
/dev/ttyHSL2
l
tree first.
c
39 SPI_MISO UART RX
e a
67 MAIN_TXD UART TX
i
/dev/ttyHS0
u t
68 MAIN_RXD UART RX
Q ide n
As defined in the table above, the default function of pin 38/39 is SPI. So developers need to configure the
Linux device tree to enable the UART option. The default pin function can be UART or GPIO by
configuring Linux device tree. Please refer to the related document to configure device tree.
n f
4.3.3.1. Pin 63/66 as UART
o
The group of pins generate the tty device /dev/ttyHSL1 in Linux system. Developers may simply open this
device to send/receive data.
C
If hardware handshaking is to be used, pin 41/42 (with CTS/RTS function) should be used together with
pin 63/66. Pin 41 & 42 are multiplexing pins designed for I2C function by default, and they can offer
alternate function of CTS/RTS. Developers have to switch the multiplexing mode of pin 41 & 42 by
reconfiguring Linux tree before using them for hardware handshaking.
NOTE
By default, the UART interface (DCD/DTR) cannot be tested directly on EVB board. Something more
(jump wire) need to be done to test the interface. There are two ways that can be utilized, as illustrated
below.

LTE Module Series
 Test Solution I: TE-A Module + EVB (×1)
Step 1: Do not insert the TE-A module into EVB but independently supply power to it.
Step 2: Use jump wires to connect DCD/DTR on TE-A module to TXD_V1.8V/ RXD_V1.8V at J806 on
EVB.
Step 3: Connect the Main UART port on EVB to PC for testing.
 Test Solution II: TE-A Module + EVB (×2)
Step 1: Prepare two EVB boards (EVB-A and EVB-B). Get rid of the resistors in DCD and DTR lines on
l
EVB-A.
Step 2: Insert TE-A module into EVB-A. And use jump wires to connect DCD/DTR on EVB-A to
e
TXD_V1.8V/RXD_V1.8V at J806 on EVB-B.
t
Step 3: Supply power to EVB-B.
c l
Step 4: Connect the Main UART port on EVB-B to PC for testing.
u e t ia
4.3.3.2. Pin 38/39 as UART
Q ide n
The two pins are designed for SPI function by default. Developers have to switch the multiplexing mode of
them by reconfiguring Linux device tree before programming the pins.
The group of pins generate the tty device /dev/ttyHSL2 in Linux system. Developers may simply open this
f
device to send/receive data.
n
If hardware handshaking is to be used, pin 37/40 (with RTS/CTS function) should be used together with
o
pin 38/39. Pin 37 & 40 are multiplexing pins designed for SPI function by default, and they can offer
alternate function of RTS/CTS. Developers have to switch the multiplexing mode of pin 37 & 40 by
C
reconfiguring Linux tree before using them for hardware handshaking.
Test Method:
Use jump wire to connect the pins (pin 38/39) on QuecOpen module to the UART port on Quectel EVB or
your own evaluation board. And the level conversion chip (TTL-to-232) is required.
4.3.3.3. Pin 67/68 as UART
On UMTS & LTE EVB, there are all pinouts for the full-featured main UART.
The group of pins generate the tty device /dev/ttyHS0 in Linux system. Developers may simply open this
device to transfer data.

LTE Module Series
If hardware handshaking is to be used, pin 64/65 (with primary function of CTS/RTS) should be used
together with pin 67/68.
4.3.3.4. Programming reference
#include "ql_oe.h"
#include "ql_uart.h"
l
API functions
int Ql_UART_Open(const char* port, unsigned int baudrate, Enum_FlowCtrl flowCtrl);
t e
int Ql_UART_Read(int fd, char* buf, unsigned int buf_len);
l
int Ql_UART_Write(int fd, const char* buf, unsigned int buf_len);
c
int Ql_UART_SetDCB(int fd, ST_UARTDCB *dcb);
e a
int Ql_UART_GetDCBConfig(int fd, ST_UARTDCB *dcb);
t i
int Ql_UART_IoCtl(int fd, unsigned int cmd, void* pValue);
u
int Ql_UART_Close(int fd);
Q ide n
/* Check the first NFDS descriptors each in READFDS (if not NULL) for read readiness, in WRITEFDS (if
not NULL) for write readiness, and in EXCEPTFDS (if not NULL) for exceptional conditions. If TIMEOUT
is not NULL, time out after waiting the interval specified therein. Returns the number of ready descriptors,
or -1 for errors. */
f
extern int select (int __nfds, fd_set *__restrict __readfds,
n
fd_set *__restrict __writefds,
fd_set *__restrict __exceptfds,
o
struct timeval *__restrict __timeout);
C
 Example
Please see example/uart/example_uart.c and example_uart_at.c for details.
4.3.4. ADC
In hardware, please refer to document [2] for the pin definition.
In software, developers may sample ADC value by sending AT+QADC=0/1 through the tty device
/dev/smd8.

LTE Module Series
 Example
Please see example/adc/example_adc.c for details.
4.3.5. I2C
QuecOpen module provides one I2C interface. The I2C interface can be host only.
Table 5: I2C Pins
l
e
(default)
t
l
I2C_SCL_ UART_CTS_
c
41 I2C_SCL Edge GPIO_7 1.8V B-PD,L ✗
I2C interface, BLSP2 BLSP2
e ia
host only I2C_SDA_ UART_RTS_
42 I2C_SDA Edge GPIO_6 1.8V B-PD,L ✗
t
BLSP2 BLSP2
u n
Q ide
#include "ql_oe.h"
#include "ql_i2c.h"
f
 API functions
n
int Ql_I2C_Init(unsigned char slaveAddr);
int Ql_I2C_Read(int fd, unsigned short slaveAddr, unsigned char ofstAddr, unsigned char* ptrBuff,
o
unsigned short length);
int Ql_I2C_Write(int fd, unsigned short slaveAddr, unsigned char ofstAddr, unsigned char* ptrData,
C
unsigned short length);
/* Perform the I/O control operation specified by REQUEST on FD. One argument may follow. Its
presence and type depend on REQUEST. Return value depends on REQUEST. Usually -1 indicates error.
*/
//extern int ioctl (int __fd, unsigned long int __request, ...) __THROW;
 Example
Please see example/i2c/example_i2c.c for details.

LTE Module Series
4.3.6. SPI
QuecOpen module provides one SPI interface. The interface can be host only.
The baud rate of SPI can be up to 50MHz, and the default is 19.2MHz.
Table 6: SPI Pins

l
(default)
SPI_CS_N_ UART_RTS_
e
BLSP6 BLSP6
t l
SPI_MOSI_ UART_TXD_
✔
c
38 SPI_MOSI Edge GPIO_20 1.8V B-PD,L
SPI BLSP6 BLSP6
a
Interface SPI_MISO_ UART_RXD_
e i
BLSP6 BLSP6
u t
n
Q ide
4.3.6.1. SPI Mode
f
In QuecOpen system, the SPI device drivers have been compiled to .ko modules. There are two .ko
n
modules existing in the Linux system of QuecOpen module: spidev.ko, quec_spi.
cd /usr/lib/modules/3.18.20/kernel/drivers/spi#
o
ls
quec_spi_chn.ko spidev.ko
C
The two SPI driver modules are for different application cases.
 4-line mode: spidev.ko
Figure 6: SPI 4-Line Mode

LTE Module Series
 6-line mode: quec_spi_chn.ko
SCLK
MOSI
Module MCU
MISO
(SPI Master) CS (SPI Slave)
MCU_RDY
MODEM_RDY
Figure 7: SPI 6-Line Mode
el
In 6-line mode SPI, from the module side, MCU_RDY should be an interrupt pin that can wake up the
t
module, and MODEM_RDY can be any GPIO. Please refer to Table 2 for details.
e c ia l
4.3.6.2. Install SPI Driver
u t
By default, the SPI device is not present. Developers need to install the SPI driver (.ko module) before
n
accessing to SPI device.
Q ide
 4-line mode: spidev.ko
//Uninstall SPI driver module.
f
rmmod spidev
n
//Install 4-line mode SPI driver.
o
insmod spidev.ko busnum=6 chipselect=0
C
// install 4-line mode SPI driver with speed parameter (the max speed is 19.2MHz by default).
insmod spidev.ko busnum=6 chipselect=0 maxspeed=50000000
sleep(1);
After the SPI driver module is installed, the SPI device /dev/spidev6.0 will be generated. Developers may
simply open this device to send/receive SPI data.
 6-line mode: quec_spi_chn.ko
//Uninstall SPI driver module.

rmmod quec_spi_chn
//Install 6-line mode SPI driver.

insmod quec_spi_chn.ko busnum=6 chipselect=0 gpiomodemready=78 gpiomcuready=79

LTE Module Series
//Install 6-line mode SPI driver with speed parameter (the max speed is 19.2MHz by default).
insmod quec_spi_chn.ko busnum=6 chipselect=0 gpiomodemready=78 gpiomcuready=79
maxspeed=50000000
//Install 6-line mode SPI driver with SPI mode and speed parameter.
insmod quec_spi_chn.ko busnum=6 chipselect=0 gpiomodemready=78 gpiomcuready=79 spimode=0
maxspeed=50000000
sleep(1);
l
After the SPI driver module is installed, developers may get 8 SPI devices that indicate 8 SPI channels,
which can be used for different business data.
c t e l
u e t ia
Q ide n Figure 8: SPI 8 Channels
f
Developers may execute the previous commands by system call when initializing SPI in application.
n
system("insmod xxxxx");
o
sleep(1);
C
4.3.6.3. SPI Parameters
 SPI customized parameters
<busnum> SPI bus number. Fixed to 6.

<chipselect> 0 is active.
<maxspeed> The default speed is 19.2MHz, and the max speed can be up to 50MHz. The
possible values (unit: Hz): {960000, 4800000, 9600000, 16000000, 19200000,
25000000, and 50000000}.
<spimode> It is decided by SPI device.
0: Mode 0 CPOL=0, CPHA=0

LTE Module Series

<gpiomodemredy> A GPIO number which indicates the modem is ready (not in sleep state), and
simultaneously wake up the external MCU. Please refer to the “Pin Multiplexing”
field for the GPIO number in Table 2.
<gpiomcuready> A GPIO number which indicates the external MCU is ready (not in sleep state),
and simultaneously wake up the module. Please refer to the “Pin Multiplexing”
field for the GPIO number in Table 2.
#include "ql_oe.h"
l
 API functions
t e
Developers may directly call the APIs in standard library, such as open(), ioctl(), to access and control
l
the SPI device /dev/spidev6.0.
c a
 Example
e t i
Please see example/spi/example_spi.c for details.
4.4. File System
u
Q ide n
f
n
#include <sys/types.h>
#include <sys/stat.h>
o
#include <fcntl.h>
C
 API functions
/* Set file access permissions for FILE to MODE. If FILE is a symbolic link, this affects its target instead.
*/
extern int chmod (const char *__file, __mode_t __mode);
/* Get file attributes for FILE and put them in BUF. */
extern int stat (const char *__restrict __file, struct stat *__restrict __buf);
/* Open a file and create a new stream for it. */
extern FILE *fopen (const char *__restrict __filename, const char *__restrict __modes);
extern FILE *freopen (const char *__restrict __filename,
const char *__restrict __modes,
FILE *__restrict __stream) __wur;

LTE Module Series
/* Seek to a certain position on STREAM. */
extern int fseek (FILE *__stream, long int __off, int __whence);
/* Read chunks of generic data from STREAM. */
extern size_t fread (void *__restrict __ptr, size_t __size, size_t __n, FILE *__restrict __stream);
/* Read formatted input from STREAM. */
extern int fscanf (FILE *__restrict __stream, const char *__restrict __format, ...);
/* Write chunks of generic data to STREAM. */
l
extern size_t fwrite (const void *__restrict __ptr, size_t __size, size_t __n, FILE *__restrict __s);
t e
/* Return the current position of STREAM. */
c l
extern long int ftell (FILE *__stream);
e t ia
/* Remove file FILENAME. */
u n
extern int remove (const char *__filename);
Q ide
/* Rename file OLD to NEW. */
extern int rename (const char *__old, const char *__new);
f
/* Close STREAM. */
n
extern int fclose (FILE *__stream);
o
/* Create a new directory named PATH, with permission bits MODE. */
C
extern int mkdir (const char *__path, __mode_t __mode);
 Example
Please see example/file/example_file.c for details.
4.5. SD Card/eMMC Flash
QuecOpen module provides a group of SDIO interface that can connect to SD card or eMMC flash. The
pins are defined in document [2] and [3].
By default, either SD card or eMMC flash is mounted to /media/sdcard/.

LTE Module Series
4.6. Audio
Audio option includes record and playback. The record data is outputted in PCM stream.
QuecOpenTM supports mixer player, and supports playing audio and TTS at the same time.
#include "ql_oe.h"
#include "ql_audio.h"
l
 API functions
e
int Ql_AudPlayer_Open(char* device, _cb_onPlayer cb_func);
t
typedef int(*_cb_onPlayer)(int hdl, int result);
c l
int Ql_AudPlayer_Play(int hdl, unsigned char* pData, unsigned int length);
a
int Ql_AudPlayer_PlayFrmFile(int hdl, int fd, int offset);
e i
int Ql_AudPlayer_Pause(int hdl);
u t
int Ql_AudPlayer_Resume(int hdl);
n
void Ql_AudPlayer_Stop(int hdl);
void Ql_AudPlayer_Close(int hdl);
Q ide
typedef int(*_cb_onRecorder)(int result, unsigned char* pBuf, unsigned int length);
int Ql_AudRecorder_Open(char* device, _cb_onRecorder cb_fun);
f
int Ql_AudRecorder_StartRecord(void);
int Ql_AudRecorder_Pause(void);
n
int Ql_AudRecorder_Resume(void);
o
void Ql_AudRecorder_Stop(void);
void Ql_AudRecorder_Close(void);
C
 Example
Please see audio/example_audio.c for details.
4.7. TTS
Developers may start/stop TTS player by sending AT+QTTS through the tty device /dev/smd8.

LTE Module Series
 Example
Please see tts/example_tts.c for details.
4.8. Voice Call
Developers can open the AT port /dev/smd8 to send AT commands to program telephony option. Please
refer to document [4] for the usage of related AT commands.
el
4.9. SMS
c t l
Developers can open the AT port /dev/smd8 to send AT commands to program SMS option. Please refer
a
to document [4] for the usage of related AT commands.
u
4.10. Network Service
e n t i
Q ide
f
#include "ql_nw.h"
n
 API functions
o
int Ql_NW_GetSignalQuality(unsigned int* rssi, unsigned int* ber);
int Ql_NW_GetRegState(int* state);
C
int Ql_NW_GetServingCell(ST_CellInfo* cell);
int Ql_NW_GetNeighborCell(ST_CellInfo* cell, unsigned int cellCnt);
int Ql_NW_GetRadioAccessTech(void);
int Ql_NW_GetMccMnc(char* mcc, char* mnc);
int Ql_NW_GetNetworkName(char* ptrNetName, unsigned int size);
4.11. Data Service
QuecOpenTM uses the component “DSI_NetCtrl” to perform data services call. DSI_NetCtrl just controls
and manages the data activities and will not provide methods for data transfer explicitly. Developers can
adopt BSD sockets or Unix sockets to create data connections.

LTE Module Series
4.11.1. DSI_NetCtrl
DSI_NetCtrl library API contains a common interface for clients to perform data services call control in the
applications that requires WWAN data services functionality.
Compared to data service QCMAP, DSI_NetCtrl enables developers to create multiple profiles for
different PDN. So if there is a need to program dual-APN, then this way should be selected for application
development.
#include "ql_oe.h"
l
#include “dsi_netctrl.h”
e
#include “ds_util.h”
t l

c
API functions
a
//Initialize the DSI_NetCtrl library
e i
extern int dsi_init_ex( int mode,void (* dsi_init_cb_func)( void * ),void *dsi_init_cb_data );
u n t
//Get data service handle. All subsequent functions use this handle as an input parameter.
extern dsi_hndl_t dsi_get_data_srvc_hndl( dsi_net_ev_cb cb_fn, void * user_data );
Q ide
//Release a data service handle. All resources associated with the library are released.
extern void dsi_rel_data_srvc_hndl(dsi_hndl_t hndl);
f
//Set the data call parameter before trying to start a data call.
n
//Set IP type, APN, user name and password.
o
extern int dsi_set_data_call_param( dsi_hndl_t hndl, dsi_call_param_identifier_t identifier,
dsi_call_param_value_t *info );
C
//Start/stop a data call.
extern int dsi_start_data_call(dsi_hndl_t hndl);
extern int dsi_stop_data_call(dsi_hndl_t hndl);
//Get the number of IP addresses (IPv4 and global IPv6) associated with the DSI interface.
extern unsigned int dsi_get_ip_addr_count( dsi_hndl_t hndl );
//Get the IP address information structure (network order).

extern int dsi_get_ip_addr( dsi_hndl_t hndl, dsi_addr_info_t * info_ptr, int len );
//Return the current data bearer technology on which a call was brought up
(GSM/WCDMA/HSPA/LTE/…).
dsi_data_bearer_tech_t dsi_get_current_data_bearer_tech( dsi_hndl_t hndl );

LTE Module Series
//Query the reason for a call being terminated.

extern int dsi_get_call_end_reason( dsi_hndl_t hndl, dsi_ce_reason_t * ce_reason, dsi_ip_family_t ipf );
//Clean-up the DSI_NetCtrl library.

extern int dsi_release(int mode);
Please refer to document [5] for detailed information about DSI_NetCtrl.
 Example
Before starting data call, parameters for DSI_NetCtrl should be set first. The following are the minimum
settings.
el
//Set profile ID for both CDMA and UMTS. These settings enable the program to cover both CDMA and
t
Non-CDMA networks.
e c ia l
u n t
Q ide
//Set IP version (IPV4, IPV6, IPV4V6).
n f
//Set APN and user name/password.
Co
//Start a data call (Activate PDN, get IP, and feedback via callback).
Please see example /data_service/dsi_netctrl/example_dsi_netctrl.c for details.

LTE Module Series
4.11.2. Sockets
In QuecOpenTM, Unix sockets or BSD sockets can be used to establish data connections.
#include <sys/types.h>
#include <sys/socket.h>
#include <stdio.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#include <unistd.h>
l
#include <string.h>
e
#include <stdlib.h>
t
#include <fcntl.h>
c l
#include <sys/shm.h>
#include <pthread.h>
e ia
#include "ql_network.h"
u t
 API functions
n
/* Create a new socket of type TYPE in domain DOMAIN, using protocol PROTOCOL. If PROTOCOL is
Q ide
zero, one is chosen automatically. Returns a file descriptor for the new socket, or -1 for errors. */
extern int socket (int __domain, int __type, int __protocol);
f
/* Open a connection on socket FD to peer at ADDR (which is LEN bytes long). For connectionless socket
n
types, just set the default address to send to and the only address from which to accept transmissions.
Return 0 on success, -1 for errors. */
o
extern int connect (int __fd, __CONST_SOCKADDR_ARG __addr, socklen_t __len);
C
/* Send N bytes of BUF to socket FD. Returns the number sent or -1. */
extern ssize_t send (int __fd, const void *__buf, size_t __n, int __flags);
/* Read N bytes into BUF from socket FD. Returns the number read or -1 for errors. */
extern ssize_t recv (int __fd, void *__buf, size_t __n, int __flags);
/* Send N bytes of BUF on socket FD to peer at address ADDR (which is ADDR_LEN bytes long).
Returns the number sent, or -1 for errors. */
extern ssize_t sendto (int __fd, const void *__buf, size_t __n,
int __flags, __CONST_SOCKADDR_ARG __addr,
socklen_t __addr_len);

LTE Module Series
/* Read N bytes into BUF through socket FD. If ADDR is not NULL, fill in *ADDR_LEN bytes of it with the
address of the sender, and store the actual size of the address in *ADDR_LEN. Returns the number of
bytes read or -1 for errors. */
extern ssize_t recvfrom (int __fd, void *__restrict __buf, size_t __n,
int __flags, __SOCKADDR_ARG __addr,
socklen_t *__restrict __addr_len);
/* Prepare to accept connections on socket FD. N connection requests will be queued before further
requests are refused. Returns 0 on success, -1 for errors. */
extern int listen (int __fd, int __n);
l
/* Await a connection on socket FD. When a connection arrives, open a new socket to communicate with
e
it, set *ADDR (which is *ADDR_LEN bytes long) to the address of the connecting peer and *ADDR_LEN
t
to the address's actual length, and return the new socket's descriptor, or -1 for errors. */
c l
extern int accept (int __fd, __SOCKADDR_ARG __addr, socklen_t *__restrict __addr_len);
e t ia
/* Shut down all or part of the connection open on socket FD.
u
HOW determines what to shut down:
n
SHUT_RD = No more receptions;
Q ide
SHUT_WR = No more transmissions;
SHUT_RDWR = No more receptions or transmissions.
Returns 0 on success, -1 for errors. */
f
extern int shutdown (int __fd, int __how);
n
/* Check the first NFDS descriptors each in READFDS (if not NULL) for read readiness, in WRITEFDS (if
o
not NULL) for write readiness, and in EXCEPTFDS (if not NULL) for exceptional conditions. If TIMEOUT
is not NULL, time out after waiting the interval specified therein. Returns the number of ready descriptors,
or -1 for errors. */
C
extern int select (int __nfds, fd_set *__restrict __readfds,
fd_set *__restrict __writefds,
fd_set *__restrict __exceptfds,
struct timeval *__restrict __timeout);
 Example
Please see example/data_service/tcp_client/example_tcpClient.c for details.

LTE Module Series
4.12. GNSS
The GNSS chip is built in the module. Developers just need to enable the GNSS option to retrieve NMEA
statements.
The GNSS NMEA can be outputted through USB-NMEA port, Debug UART port and Linux SMD7 port. In
QuecOpenTM application, developers may get NMEA by opening /dev/smd7.
Please follow the three steps below to get GNSS NMEA:
l
Step 1: Open /dev/smd7
e
Step 2: Set the output port of GNSS NMEA to SMD port.
t
Send AT+QGPSCFG=”outport”,”linuxsmd” though AT port (/dev/smd8).
c l
Step 3: Enable GNSS.
e ia
Send AT+QGPS=1 to enable GNSS option though AT port (/dev/smd8).
u n t
Please refer to document [6] or [7] for more AT commands about GNSS configurations.
Q ide
 Example
Please see example/gnss/example_gps.c for details.
4.13. Wi-Fi
n f
o
QuecOpen module provides SDIO interface that can interface to Wi-Fi chip. Also, Quectel provides Wi-Fi
C
module solution (FC20 module) that provides built-in Wi-Fi and Bluetooth functions. That means
developers have two choices to realize Wi-Fi functions: using FC20 module as the Wi-Fi component, or
using their own Wi-Fi chip. The relevant pins (pin 129-138) are defined in Table 2.
 Example
If Quectel FC20 module is used as the Wi-Fi component, please refer to example/wifi/example_wifi.c.

LTE Module Series
4.14. (U)SIM Card
#include "ql_sim.h"
 API functions
int Ql_SIM_GetState(int* state);

int Ql_SIM_GetICCID(char *iccid);
int Ql_SIM_GetIMSI(char *imsi);
l
int Ql_SIM_GetPINTriesCnt();
int Ql_SIM_EnterPIN(const char* pin);
c t e l
u e t ia
Q ide n
n f
Co

LTE Module Series
5 Customization
5.1. Pin Multiplexing Function
l
All programmable GPIO pins defined in Table 2 have the primary function by default when booting.
t e
However, some developers may hope it is one of the alternative functions when the module boots.
c l
Take pin 38/39 as an example:
e ia
The pins are designed for SPI option by default when booting. It means the SPI driver will be loaded for
t
the two pins when Linux system boots. If the two pins need to be configured as UART option, there are
u
two methods available. Basically the two methods work on reconfiguring Linux device tree (DTS), and the
n
details are illustrated in the following two sub-chapters.
Q ide
5.1.1. With Linux Kernel Code
f
Developers can configure the several files shown as below:
n
kernel/arch/arm/boot/dts/qcom/mdm9607.dtsi
kernel/arch/arm/boot/dts/qcom/mdm9607-pinctrl.dtsi
o
kernel/arch/arm/boot/dts/qcom/mdm9607-cdp.dtsi
kernel/arch/arm/boot/dts/qcom/mdm9607-mtp.dtsi
C
5.1.2. Without Linux Kernel Code
The DTS is included in the file mdm9607-perf-boot.img, which is one of released files in firmware. Please
follow the steps below to finish configuration.
Step 1: Unpack mdm9607-perf-boot.img. The outputted files are as below.

LTE Module Series
Figure 9: Disassemble boot.img
l
Step 2: Change .dts file.
e
Step 3: Re-pack these files to generate a new file new_boot.img.
t
Step 4: Download the new_boot.img.
5.2. Rootfs
e c ia l
u n t
In QuecOpenTM, the application is packed into rootfs when compiling. The relevant processing is defined
Q ide
in the following script files in SDK.
SDK/build.sh
f
SDK/tools/packapp
n
If there is a need to customize the rootfs, such as creating folder, adding files, developers can change the
script files to achieve it.
Co

LTE Module Series
6 Appendix A References
Table 7: Related Documents
l
SN Document Name Remark
USB driver installation guide for
e
[1] Quectel_WCDMA&LTE_Linux_USB_Driver_User_Guide
t
UMTS/HSPA/LTE modules
l
Hardware design for QuecOpen
c
[2] Quectel_EC2x_QuecOpen_Hardware_Design
modules
a
Quectel_EC20 R2.0&EC21&EC25_QuecOpen_GPIO_ All multiplexing pins available in
e i
[3]
Assignment_Speadsheet QuecOpen modules
u t
AT commands manual for EC2x
[4] Quectel_EC2x_AT_Commands_Manual
n
modules
Q ide
Qualcomm_DSI_NetCtrl_Library_API_Interface_
[5] API library for network management
Specification
EC20 R2.0 GNSS AT commands
[6] Quectel_EC20_R2.0_GNSS_AT_Commands_Manual
manual
f
EC25&EC21 GNSS AT commands
[7] Quectel_EC25&EC21_GNSS_AT_Commands_Manual
n
manual
o
Table 8: Terms and Abbreviations
C
Abbreviation Description
ADB Android Debug Bridge
API Application Program Interface
CMOS Complementary Metal-Oxide-Semiconductor Transistor
DSI_NetCtrl Data Service Interface Network Controller
FOTA Firmware over The Air
GNSS Global Navigation Satellite System
GPIO General-purpose Input/Output

LTE Module Series
I2C Inter-Integrated Circuit
MIPS Million Instructions Per Section
NMEA National Marine Electronics Association
PCM Pulse Code Modulation
QCMAP Qualcomm Mobile Access Point
QuecOpenTM The Open Embedded Development Platform of Quectel Modules
RAM Random Access Memory
l
SDIO Secure Digital Input and Output Card
t e
SDK Software Development Kit
c l
SGMII Serial Gigabit Media Independent Interface
e ia
SPI Serial Peripheral Interface
u t
TTS Text to Speech
Q ide n
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
f
WLAN Wireless Local Area Network
o n
C

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EC25&EC21&EC20 R2.

LTE Module Series

Rev. EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide_V1.0

Quectel Wireless Solutions Co., Ltd.

Or our local office. For more information, please visit:

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About the Document

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About the Document ................................................................................................................................... 2

2 QuecOpenTM Platform .......................................................................................................................... 8

3 Work with QuecOpenTM ..................................................................................................................... 16

EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide Confidential / Released 3 / 50

3.6. Debug Application.................................................................................................................. 24

4 Programming Reference ................................................................................................................... 25

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TABLE 1: DATA STORAGE PLACES FOR DEVELOPERS ................................................................................ 9

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2.1. System Architecture

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2.2. Open System Resources

Cortex-A7 1.2GHz, ARMv7.

2.2.2. Host System

Linux system with kernel 3.18.

ubi0:usrfs ubifs 31.9M 868.0K 31.0M 3% /data

The space available is around 19MB.

EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide Confidential / Released 9 / 50

2.2.4. RAM Space

RAM available: 50M bytes

2.3. Open Hardware Resources

3 GPIO3 Edge GPIO_42 -- -- 1.8V B-PD,L ✔

24 PCM_IN Edge PCM_IN GPIO_76 -- 1.8V B-PD,L ✔

25 PCM_OUT Edge PCM_OUT GPIO_77 -- 1.8V B-PD,L ✗

SDC2_ SDIO2 SDC2_ LOW SD Dedicated

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SDC2_ SDC2_ 1.8V. Dedicated

SDC2_ SDC2_ 1.8V. Dedicated

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SPI_CLK_ UART_CTS_ BOOT_

62 GPIO6 Edge GPIO_75 -- -- 1.8V B-PD,L ✔

UART1_ UART_TXD_ UART_TXD_

UART1_ interface UART_RXD_ UART_RXD_

EPHY_ EPHY_ 1.8V/

SGMII_ interface SGMII_ Analog Dedicated

SGMII_ SGMII_ Analog Dedicated

SGMII_ SGMII_ Analog Dedicated

SGMII_ SGMII_ Analog Dedicated

EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide Confidential / Released 12 / 50

133 SDC1_CLK Bottom SDC1_CLK GPIO_16 -- 1.8V B-NP,L ✔

134 SDC1_CMD Bottom SDC1_CMD GPIO_17 -- 1.8V B-PD,L ✔

COEX_ control/ COEX_ FORCE_

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QuecOpen module provides an SGMII interface.

EC25&EC21&EC20 R2.0_QuecOpen_Developer_Guide Confidential / Released 15 / 50

3 Work with QuecOpenTM

Start to Compile Applications

Refer to Chapter 3.3

Figure 2: How to Start Working with QuecOpenTM

extern int timerfd_settime (int ufd, int flags,

extern int timer_gettime (timer_t timerid, struct itimerspec *value);

extern int pthread_create (pthread_t *restrict newthread,

extern int pthread_join (pthread_t th, void **thread_return);