EE6301 DIGITAL LOGIC CIRCUITS

SUBJECT CODE/ TITLE : EE6301 DIGITAL LOGIC CIRCUITS

YEAR/ SEM/BRANCH
: II/ III/ EEE
UNIT I -NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES
PART A
.
Show that A(A+B)= A.
Convert the binary [10101101]2 into its Gray code.
If (123)5= (A3)7, then what is the value of A?
Simplify: X+XY.
Convert (26.24)8 to Hexadecimal format.
What is the largest binary number that can be expressed with 12 bits? What is the equivalent decimal &
Hexadecimal?
7. What is the value of b if 41b = 5?

List the advantages of Karnaugh map.

State and prove Distributive laws.
What are weighted Binary codes? Give two examples.
Convert 62.37510 into binary.
Use de Morgans theorem find:
(A+B+C)
A(B+C)
Simplify the following Boolean expression to a minimum number of literals:
xyz+ xz.
ABC+AB+ABC.
Construct OR gate using only NAND gates
What are the advantages of CMOS?
Define fan-out.
Define noise margin.
What are the important CMOS characteristics?
Draw the CMOS logic circuit for Inverter.
Draw the logic circuit for CMOS NAND gate.
Define propagation delay.

PART B
Simplify the following using K-map and realize the reduced function using NAND gates
only. m(0,1,3,5,6,8,9,14,26,28,31)+(16) .d(4,1
Simplify the following using K map and realize the reduced function using NAND gates only.
m(1,2,4,5,7,9,12,13)+ .d(3,8)(16).

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EE6301 DIGITAL LOGIC CIRCUITS

3.
A digital system has 3 bits A,B and C as input. The output Y is 1 when two adjacent bits or
three equal to 1.
a.
Draw the K-map for Y & minimize.
b.
Realize the function using NAND gates.
(16)
4.
(ABCD.1234)16= (?)8 = (?)10 = (?)2 = (?)BCD = (?)5
(16)
5.
Perform the following conversion:
a.
(10110001 101011.111 1000000110)2 =(?)8
(4)
b.
(0.513)10 =(?)8
(4)
c.
(0.6875)10 = (?)2
(4)
d.
(10110001101011.11110010)2 =(?)16
(4)
6.
Reduce the following using K-Map method. F =m(2,3,4,6,7,9,11,(16)
Convert the following numbers:
(A3B)16 = (? )10
(444.456)10 = ( ? )8
(59.57)8 = (?)2
d. (4097.188)10 = (?)2
(16)
8. Obtain the canonical SOP & POS of the following expression A+AB+BC .
(8)

9.

a. Explain weighted and non weighted binary codes with examples.

(6)
b. Simplify the following Boolean expression to a minimum number of literals
i.
((ABC+AB) + BC)
ii.
((AB)+A+AB)
(10)
10.
Simplify the function F in SOP & POS(16) m(3,4,
11. Given X= 1010100 & Y= 1000011. Find X-Y & Y-X using complement1s&.
(8)2
12.
Explain NOR and OR gate construction using ECL.Also give the characteristics of ECL
family.
(16)
13.

a. Explain the formation inverter using CMOS and its operation.

(8)
b. Discuss the characteristics of ECL circuit.
(8)
14.

a. Explain the working of two inputs CMOS NAND gate.

(8)
b. Compare the performance of various logic families.
(8)
15.

a. Write notes on the digital logic families comparing the characteristics.

(8)
b. Explain the working of two inputs TTL NAND gate.
(8)

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EE6301 DIGITAL LOGIC CIRCUITS

UNIT II COMBINATIONAL CIRCUITS
PART A
Realize the logic expression Y= (AB) +A+ (B
Give an application each for a MUX and a De-MUX.
Give an application for X-OR function.
Which code is used for error detection?
Obtain the truth table of the function.
F=xy+xy+yz.
Give the differences between DMUX & MUX.
What is the function of a multiplexers select inputs?
Give the truth table for half subtractor.
9. Express the function onlyAB+BC. using NAND gate
Define half adder and full adder.
Which gates are called universal gates? Why ?
Define Combinational logic.
What are logic gates? List the basic gates.
What do you mean by multiplex?
What is the design procedure of combinational circuit?
Give the truth table of full adder.
What are select lines in MUX?
18. Reduce the function F(x,y,z)= (0,3,4,6,7)
What are code converters?
State De-Morgans theorem.
PART B
1.

a. Design and construct a full adder circuit using two half adders and a OR gate.
(8)
b. Draw the logic diagram of 1 to 4 line DMUX.
(8)
2.
Design a full adder circuit using only NOR gates.
(8)
3.

a. Design a code converter that converts a BCD to Excess- 3 code.

(10)
4.
Design a combinational circuit that will converts a decimal digits from BCD to Excess-3code.
(12)
Implement the following function. using(8) multi
Implement the following function using multi
(16)
7.
Design the circuit for full adder.
(8)
8.
Implement the given function using(8) multi
b. Implement full subtractor using demultiplexer.
(8)
9.
Design the circuit of full adder. Also design it using only NAND and NOR gates
(16)
10.
Simplify the following Boolean Expression by using K-map in POS and SOP form
(16)
F(W,X,Y,Z)= (1,3,4,6,9,11,12,14)

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EE6301 DIGITAL LOGIC CIRCUITS

UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS

PART A
What is the other name for flip flop?
What is the drawback of SR flip flop?
Draw the diagram of 4 bit ripple counter.
What is a ring counter?
State the problem normally encountered in SR flip flop.
How many flip flops are needed o realize the mod-16 counter?
Draw the logic diagram for D latch.
Show that the characteristics equation for the complement output of JK flip flop is
Q(t+1)=JQ+KQ.
Show how a RS FF can be built using NAND gates.
What is a ripple counter?
Draw the block diagram to realize JK flip flop using SR flip flop.
What is the problem normally encountered in JK flip flop?
Give the excitation table for T flip flop.
What is a master-slave FF?
What are the different types of FF?
Define setup time.
What is meant by edge and level triggering?
Define propagation delay.
What are shift registers?
State the difference between Mealy and Moore mode.
PART B
1.

a. Draw the logic diagram of JK flip flop and give its characteristics table.
(8)
b. Design a 3 bit counter using T flip flop.

(8)
2.
Design a decade counter using T flip flop.
(16)
3.
Design a synchronous MOD-10 down counter using JK flip flop.
(16)
a.
Describe the PISO shift register with a neat logic diagram.
(8)
b. Explain the function of JK flip flop using a suitable diagram and discuss how it differs
from SR flip flop.
(8)
Design a sequential circuit with 4 FF ABCD. The next states of B,C,D are equal to the present
states of A,B,C .The next states of A is equal to the ex-OR of the present states of C
and D.
(16)
5.
Design a counter with the sequence 0,1,3,7,6,4,0.
(16)
6.
Design SISO, SIPO shift register using D flips flop.
(8)
7.
Design a MOD-5 synchronous counter.
(8)
8.
Convert a SR flip flop to JK flip flop.
(8)
9.
Design a MOD-7 counter.
(8)

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EE6301 DIGITAL LOGIC CIRCUITS

10.
Explain the working of Master slave JK flip flop.
(8)
11.
Illustrate the analysis with JK flip flop with state table & state diagram.
(16)
UNIT IV- ASYNCHRONOUS SEQUENCTIAL CIRCUITS
PART A
What is an asynchronous sequential circuit?
Define the purpose of flow table.
What do you mean by Race conditions in asynchronous sequential circuit?
Differentiate: Synchronous and Asynchronous sequential circuits.
What is a ripple counter?. State the drawbacks of ripple counter.
Define races in asynchronous sequential circuits.
Differentiate stable and unstable states.
Define asynchronous sequential circuits.
What is flow table?
Mention the applications of PLA.
What is PLA?
What is race condition? How can it be eliminated?
What is essential hazard? Give an example.
Compare volatile data storage with non volatile data storage
What is a DRAM? How is it refreshed
Name the types of ROM.
State the hazards in asynchronous sequential circuits.
Give the comparision between PROM and PLA.
Define address and word.
Define primitive flow table?

PART B
1.
What are hazards? Explain the occurrence of hazards in combination circuits with an
example. Explain the types of hazards and how they are avoided.
(16)
2.
Explain in detail the design procedure for asynchronous sequential circuit.
(16)
3.

a. Discuss the procedural steps for the implication table and merging of the flow table.
(12)
b. Briefly comment on Races and their implication.
(4)
4.
Design an asynchronous circuit that has two inputs x1 and x2 and one single o/p z. the circuit
is required to give an o/p whenever the i/p sequence 00,10,11 and 01 are received but only in
that order.
(16)
5.

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EE6301 DIGITAL LOGIC CIRCUITS

a.

How do you identify and eliminate static and dynamic hazards from an asynchronous

sequential circuit? Explain in detail about that.

(10)
Find whether static O hazard does not ex Y= x1 x3+ x1. If existx2 thenx3find the+x2x3statichazards present.
(6)
Construct the Melay state diagram that will detect a serial input sequence of 10110. The detection of the
required bit pattern can occur in a longer data string and the correct pattern can overlap with another pattern.
When the i/p pattern has been detected , and cause an o/p
Z to be asserted high.
(16)
7.

a. What are hazards?. How they can be detected and rectified?

(8)
b. Design asynchronous decade counter.
(8)
8.
Explain the procedure for designing synchronous sequential circuit.
(8)
9.
Illustrate analysis procedure for asynchronous sequential circuit with maps, transition table &
flow table?
(16)
10.
Write notes on

a.
PLA

b.
FPGA
(16)
11.
Write notes on FPGA & PLD.
(8)
12.

(i)A combinational logic circuit is defined by the following function

f1(a,b,c) = (O, 1, 6, 7),(2, f2(a,3,57)b,

e)Implement=
the
having three inputs, product terms and two outputs.
(10)
(ii) Describe the concept and working of FPGA.
(6)

UNIT V-VHDL
PART A
Write HDL bahavioural model of D flip flop
What is the need for VHDL?
Write HDL for half adder
What are the various modeling techniques in HDL?
Write the VHDL code for AND gate.
List the operators available in VHDL.
What is the meaning of the following RTL statement?

T1: ACC

ACC and MDR

What are the different types of modelling the VHDL?

Write HDL bahavioural model of JKflip flop
What are packages and what is their use?
What is variable class, give example for variable?

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EE6301 DIGITAL LOGIC CIRCUITS

Write the VHDL coding for D FF.
What are test bench?
Write the test bench for AND gate.
What is Moore FSM?
What are the different kinds of test bench?
Write the test bench for and gate entity.
Write HDL bahavioural model of T flip flop.
Differentiate a signal and variable.
What is subprogram overloading?
PART B
1.
Write HDL for four bit binary counter and explain
(16)
2.

a. Write HDL code for two to one line multiplexer with data flow description and
behavioural description.
(8)
b. Write HDL for four bit adder.
(8)
3.
Write HDL code for mod 6 counter.
(16)
4.
Explain RTL design using VHDL with the help of an example
(16)
5.
Construct a VHDL module listing for a 16:1 mux that is based on assignment statement.
Use a 4-bit select word s3 s2 s1 s0 to map the
6.
Explain the design procedure of RTL using VHDL
(10)
7.

Write an HDL behavioral description of JK FF using if-else statement based on the value
of present state
(16)
8.
Write the VHDL code for mod 6 counter
(16)
9.
Describe RTL in VHDL
(16)
10.

a. Construct a VHDL module for a JK flipflop

(8)
b. Express how arithmetic and logic operations are expressed using RTL
(8)
11.
Write notes on test bench and its types.
(8)

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