An-8201 FCM8201 Three-Phase Sine-Wave BLDC Motor Controller
An-8201 FCM8201 Three-Phase Sine-Wave BLDC Motor Controller
An-8201 FCM8201 Three-Phase Sine-Wave BLDC Motor Controller
com
AN-8201
FCM8201 Three-Phase Sine-Wave BLDC Motor Controller
Introduction
FCM8201 is a BLDC motor controller with a three-phase
sine-wave / square-wave drive; the detection position is at
120 rotor magnetic pole. With just a small number of
peripheral components, it can control BLDC motors on a
stand-alone basis. In coordination with microcontroller, it
can also be used for complicated motor control applications.
It is suitable for motor control for various products, such as
fans, water / oil pumps, tooling machines, etc.
PWM-PWM commutation mode greatly facilitates use of MOSFET; between two-step continuous PWM output,
high-side driver IC in combination with driver circuit whose negative current may return to the power source side when
high and low sides both use N-channel MOSFET or IGBT as the low sides of the other two phases exchange conduction,
the driver circuit for the motor. This is because the high side as shown in Figure 5. Such negative current is one of the
does not keep being conducted during any commutating major noise sources for square-wave drive.
period and, when the high side closes, its low side with the
When U-phase outputs PWM, at the instant low-side
same phase is conducted and, as a result, synchronous
conduction of W-phase switches to low-side conduction of V-
rectifying is enabled to improve efficiency. At this moment,
phase; when both the low side of MOSFET and PWM of U-
the bootstrap circuit of the high-side driver IC has the chance
phase close, polarities of inductance of U-phase and W-phase
to charge, supplementing energy for the driving MOSFET.
are reverse. Thus the energy having been stored in inductance
Although PWM output using these commutation features a becomes negative current IW-U and returns to the power
somewhat simple driver circuit that doesnt require concern supply side via the built-in diode of high-side MOSFET of
about turn-on failure or partial conduction of the high-side W-phase. In this way, negative current is generated.
2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.3 4/8/14 3
AN-8201 APPLICATION NOTE
HA
IDC
IU-Phase
HA
IDC
IU-Phase
No negative current
generated!
U pin of FCM8201
Revolution of 2
ARNG[1:0] Hall Freq.
Poles Motor
0, 0 0.8 ~ 80 Hz 48 ~ 4800 rpm
0, 1 0.4 ~ 40 Hz 24 ~ 2400 rpm
1, x 3.2 ~ 320 Hz 192 ~ 19200 rpm
AS Voltage
4.5V
0.5V
0.3V Sine-wave Inactive
0 58 Phase Angle
Circuit Design for AS Function and Current Step 2: Identify Position for Installing Hall
Angle Correction Method Components of Motor
Step 1: Design AS Application Circuit
Step 4: Adjust, Measure, and Record Phase rising rates are consistent but the voltage levels slightly
Current Angle deviate, fine-tune the resistance value of the current-sensing
After the measuring environment is ready, the adjustment resistor (RISENSE in Figure 16) to change the level of I_FB
procedure can start. voltage to bring the voltage of I_FB and AS into
consistency.
1. Adjust the input voltage of the AS pin to 0.5 V (PWM
output advance angle: 0).
2. Use an oscilloscope to observe HA, U-phase PWM
output, and U-phase current waveform. It should be
possible to see that the center of U-phase PWM output
waveform is aligned with HA falling edge. However, the
upper half cycle center of U-phase current waveform
lags behind HA falling edge.
60
Application of Close-Loop Speed Control RPM
HPERH / L _ REG Poles (5)
Although FCM8201 comes with open-loop control design, it 6
can also realize close-loop speed control by using FO pin or CLK HPER 2
reading / writing SPI register.
where poles is the number of motor poles.
Use SPI Interface to Realize Application of
Close-Loop Speed Control CLKHPER =
IP 0.5 ~ 4.5V
+
PWM Duty
Control IN
OPO R2
I_FB
Current Feedback Amplifier
(Gain x 8) R1
M
3-Phase
Short-Circuit Current Protection Inverter
I BIAS_I_IN IS
I_IN
Cycle-by-Cycle Current VS
Protection
RBIAS
CLPF RS
Figure 22 shows the internal current feedback block The application circuit lies between the I_IN pin and RBIAS;
diagram and external application circuit. The current somewhere near I_IN pin there should be a filter capacitor
feedback block includes the current feedback amplifier, CLPF for grounding. High-frequency noise above PWM
torque error amplifier, and over-current protections. frequency is filtered to prevent noise from triggering
abnormal operation of current protection. When PWM
After the current feedback signal (I_IN) passes through a
frequency falls between 15 and 30 kHz and RBIAS is 10 k,
low-pass filter to screen out high-frequency noise, the
the capacitance should fall between about 220 pF and
current feedback amplifier amplifies the current eightfold
470 pF. Otherwise, excessive capacitance leads to
before the current is output via the I_FB pin. This is the
inaccuracy of protection function while insufficient
main function of the current feedback amplifier. An external
capacitance causes failure to filter all noise, likely to trigger
application circuit is provided for applications such as
abnormal operation of current protection.
torque-loop control or automatic adjustment of current
leading phase. The relationship between the current feedback input signal
and the output (I_IN vs. I_FB) can be expressed by:
I_IN pin outputs 50 A bias current (IBIAS_I_IN) and then, by
means of the additional 10 k bias resistor (RBIAS), the
benchmark level of load current is raised to 0.5 V. VI _ FB (VS 8) ( I BIAS _ I _ IN RBIAS ) (7)
Application of Torque Feedback Control error amplifier. The circuit connection method can take the
IP pin as the limit setting for maximum PWM duty; the
Although FCM8201 comes with open-loop speed control maximum PWM duty is determined by the external divided
design; if the combination of I_FB pin and torque error resistance of IP pin.
amplifier is used, it is also possible to realize application of
torque feedback control.
In the application circuit with torque feedback control, the
IP pin can serve as the input signal for torque control. When
the current feedback signal I_IN has been amplified by I_FB
in the torque error amplifier, it is compared with torque
control feedback signal IP. Once I_FB is greater than the
setting for IP, duty width of PWM starts to decrease to
reduce the torque output of motor. If I_FB is lower than the
setting for IP, the duty of PWM is determined by the speed
loops DUTY pin or DUTY_REG. Figure 23. Application without Torque -Loop Control
If the application circuit does not need torque feedback
control, Figure 23 should be followed for connecting torque
Short Circuit
Overload Cycle-by-Cycle
V OCP_SH
V OCP_CYC
V OCP_OL
VI_IN
Charging
V TMR_LTH COC_TMR!
PWM
Overload Current Protection motor driver. The first three protection functions avoid
motor drive failure resulting from abnormal system voltage.
The time setting of the over-current timer (OC timer) for
The last protects the driver circuit and power transistor from
overload protection can be determined by a capacitor on the
being burnt down by the excessive back-EMF voltage
OC_TMR pin or the OC_TMR[2:0] register.
generated during motor running.
The default OC timer is the OC_TMR pin and an externally
connected capacitor. Once the voltage of I_IN goes above OV and UV Protection for System
VOCP_OL, the OC_TMR pin provides a current at 40 A If the working voltage exceeds 18 V, FCM8201 enables OV
(ITMR_CHG) to charge the capacitor. When the voltage of I_IN protection status and closes all motor drive output signals
has dropped back to somewhere below VOCP_OL, the (U, V, W, X, Y and Z); the motor is set to free running. If
OC_TMR pin provides a current at 10 A (ITMR_DIS) to the working voltage goes below 8 V, UV protection is
discharge the capacitor. If the voltage of I_IN keeps enabled and closes all motor drive outputs and reset itself.
exceeding VOCP_OL, the OC_TMR keeps charging the
capacitor. Once the voltage on the capacitor has been When the output of the 5 V voltage regulator goes below
charged to 2.5 V (typical), FCM8201 immediately turns off 4 V, FCM8201 closes all motor drive output signals and the
all motor drive output signals (U, V, W, X, Y, and Z). motor is set to free running.
Moreover, it latches the close status until the FREE/nST pin OV Protection of Motor Driver
transitions to a high level (free) and then goes back to the
low-level status (start). Only then does FCM8201 disable Braking and instantaneous speed / load change during
the latch and restore output. operation of BLDC motors may generate back-EMF voltage
and feed it back to input voltage of motor drive, bringing
This protection function allows sufficient torque for the about a sharp rise in input voltage. If the sharp voltage rise
motor. Within the safe time set by the OC timer, the motor is not appropriately checked, it may burn down the power
can run with a load higher than the rated load without transistors and the whole driver circuit.
damaging power transistor of the driver circuit. In the
application field of electric vehicle and electric machine
tool, such protection function is necessary.
If the application circuit does not need this protection,
ground OC_TMR pin to disable this function.
Detailed descriptions are provided in the SPI Operation
Mode section below to address use of the OC_TMR[2:0]
register as time setting for OC timer.
Cycle-by-Cycle Current Protection Figure 25. Application Circuit of Motor Drive OVP
As long as the voltage of the I_IN pin exceeds the threshold Basic application circuit of motor drive OV protection is
voltage VOCP_CYC of the cycle-by-cycle current protection, shown in Figure 25. With the divider resistor, FCM8201 can
FCM8201 immediately reduces the normal PWM duty to use the VSENSE pin to detect the voltage of motor drive
the minimum duty output. input voltage. Once the voltage of the VSENSE pin exceeds
The purpose of this protection function is to protect the 4.5 V, the OV protection function of motor drive triggers.
power transistor of the driver circuit from damage resulting At this moment, FCM8201 immediately turns off all drive
from excessive peak current generated on PWM output as a output signals and keeps the back-EMF from rising.
result of instantaneous load change during motor running. Meanwhile the HOVP pin also outputs high level to enable
conduction of power transistor of discharge circuit. In this
Short-Circuit Current Protection (SC)) way, the back-EMF fed back to input voltage is quickly
When the voltage of the I_IN pin has three to four PWM exhausted and the level of input voltage is forced to fall to a
pulses exceeding VOCP_SH, SCP is triggered. FCM8201 safe working level. Along with the disappearance of back-
immediately closes all motor drive output signals and latches EMF, the level of VSENSE pin goes below 4.0 V and all
the close status until the FREE/nST pin transits to a high level motor drive output signals are restored to a normal level.
(free) and goes back to low-level status (start). Only then does
FCM8201 disable the latch and restore output.
sbit PIN_XP_SDO = P2^6; // to declare MCU I/O Port P2.6 to be XP/SDO pin
sbit PIN_XN_SEN = P2^4; // to declare MCU I/O Port P2.4 to be XN/SEN pin
SPI interface offers the error detection function of 6-bit via SDO. Inconsistency of the two CRC contents indicates
cyclic redundancy check (CRC). By default, this function is error in communications for the present reading operation.
disabled. To enable it to prevent communication error from MCU has to re-execute the reading operation. During a
causing motor control failure, set CRC_ON bit of writing operation, FCM8201 automatically checks
WDT_REG to 1. consistency between CRC self-calculated and the CRC sent
by MCU. If consistent, upon the time at the final bit, SDO is
Whether CRC function is enabled or not, each reading /
changed to low-level status (i.e. ACK bit) to indicate no
writing operation digit has a length of 24 bits. The very first
error in communications. If MCU does not detect any ACK
6 bits stand for the address of the register to be read /
bit on the SCK rising edge of the final bit, that indicates
written; the following 2 bits, the control command to be
there is an error in the writing operation just performed and
executed for reading or writing (Read = 1,0; Write = 0,1);
the MCU must repeat execution.
the next 8 bits, data to be read / written from / to the
register; the preceding 6 bits of the last 8 bits, CRC CRC formula:
calculation value; and the lattermost two bits, invalid bits.
Calculation scope of CRC falls between A5 to D0, 16 bits in g x x 6 x 1 (8)
all. During reading operation, the master MCU has to
calculate the CRC of these 16 bits by itself; then a check is
performed for consistency with the CRC sent by FCM8201
Data_String = (((ADDR & 0x3F) << 2 | (RW & 0x3)) << 8) | (DATA & 0xFF);
for ( i = 0; i <= 15; i++ )
{
if ( (Data_String & 0x8000) == 0x8000 )
{
CRC_Accum = Data_String & 0xFE00;
CRC_Accum = CRC_Accum ^ 0x8600;
Data_String = (Data_String & 0x01FF) | CRC_Accum;
}
if ( i == 15 )
break;
Data_String = Data_String << 1;
}
CRC_Result = ((Data_String & 0xFE00) >> 9) & 0x3F;
return CRC_Result;
}
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name TMR_CLR OC_TMR2 OC_TMR1 OC_TMR0 IP_EA DT_EA CW/CCW FREE/nST
Default 0 0 0 0 0 0 1 1
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name PMOD NA DT1 DT0 SEQ_TBL SYN_OFF EXT_SYN LPWM
Default 0 0 0 0 0 0 0 0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name ANG_SEL ARNG1 ARNG0 ANG4 ANG3 ANG2 ANG1 ANG0
Default 0 0 0 0 0 0 0 0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name SIN_MAU SIN_EA NA NA NA NA NA NA
Default 0 0 0 0 0 0 0 0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name NA NA NA NA HREG HC_INV HB_INV HA_INV
Default 0 0 0 0 0 0 0 0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name OSL_DIS OTL_EA NA CRC_ON WDT_EN CLR W_TMR1 W_TMR0
Default 0 0 0 0 0 0 0 0
OSL_DIS: For setting latch disabling for pin open/short-circuit protection. Only the R_CLK pin is provided with short
protection function; R_CLK and RT pins are provided with open-circuit protection.
0: Open/short-circuit protection does not provide latch function; so long as open/short status ends,
FCM8201 immediately restores PWM output.
1: After triggering of open/short-circuit protection, all PWM outputs are immediately turned off and latched
until the next time FREE/nST pin re-transitions to LOW level or until FREE/nST bit of CNTL_REG is set
to 1 and then set to 0.
OTL_EA: For enabling of over-temperature protection latch.
0: Over-temperature protection does not provide latch function; so long as over-temperature status ends,
FCM8201 immediately restores PWM output.
1: After triggering of over-temperature protection, all PWM outputs are immediately turned off and latched
until the next time FREE/nST pin re-transitions to LOW level or until FREE/nST bit of CNTL_REG is set
to 1 and then set to 0.
CRC_ON: For enabling of SPI CRC function.
0: SPI CRC is disabled.
1: SPI CRC is enabled.
WDT_EN: For enabling of watch dog timer (WDT).
0: WDT is disabled.
1: WDT is enabled.
W_TMR[1:0]: For setting time for watch dog timer.
0,0: When fSYS = 1.28 MHz, timing duration is 0.25 s.
0,1: When fSYS = 1.28 MHz, timing duration is 0.5 s.
1,0: When fSYS = 1.28 MHz, timing duration is 1 s.
1,1: When fSYS = 1.28 MHz, timing duration is 2 s.
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name DUTY7 DUTY6 DUTY5 DUTY4 DUTY3 DUTY2 DUTY1 DUTY0
Default 0 0 0 0 0 0 0 0
DUTY[7:0]: For setting duty width of PWM. When the DT_EA bit of CNTL_REG is set to 1, DUTY[7:0] takes the
place of the DUTY pin to control duty width of PWM.
A set value between 0 and 255 is equivalent to DUTY pin voltage 0.5 V ~ 4.5 V. (0 = Zero Duty,
255 = Full Duty).
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
Default 0 0 0 0 0 0 0 0
IP[7:0]: For setting internal voltage level for IP pin for error amplifier. When IP_EA bit of CNTL_REG is set to 1,
the written value of IP[7:0] substitutes an external IP to become the IP pin voltage level of error amplifier.
A set value between 0 and 255 is equivalent to IP pin voltage 0.5 V ~ 4.5 V.
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name NA NA NA AS4 AS3 AS2 AS1 AS0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name NA NA NA VS4 VS3 VS2 VS1 VS0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name NA NA NA IFB4 IFB3 IFB2 IFB1 IFB0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name NA NA NA RT4 RT3 RT2 RT1 RT0
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name HP15 HP14 HP13 HP12 HP11 HP10 HP9 HP8
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0
HP[15:0]: Time length counting value for each configuration change of Hall signal HA/B/C.
HP[15 : 0]
t (13)
CLK HPER
Notes:
5. If ARNG[1:0]=0,0, then, CLKHPER = fSYS 4.
6. If ARNG[1:0]=0,1, then, CLKHPER = fSYS 8.
7. If ARNG[1:0]=1,x, then, CLKHPER = fSYS.
Bit b7 b6 b5 b4 b3 b2 b1 b0
Name OT OC OS OV H_ERR DIR WDT SHORT
OT: Read value 1 indicates over-temperature protection has been triggered (RT pin voltage less than 1.0 V).
OC: Read value 1 indicates overload over-current protection has been triggered.
OS: Read value 1 indicates R_CLK and RT pins open/short-circuit protection has been triggered.
OV: Read value 1 indicates over-voltage protection has been triggered (VSENSE pin voltage higher than 4.5 V).
H_ERR: Read value 1 indicates error in Hall input signals (HA/B/C has such signal configuration as 0/0/0 or 1/1/1).
DIR: Read value 1 indicates the direction and order of Hall signals are not consistent with direction of internal
PWM sequencer.
WDT: Read value 1 indicates timing of watch dog timer is timeout.
SHORT: Read value 1 indicates short-circuit over-current protection has been triggered (I_IN pin voltage higher than 2.5 V).
Related Datasheets
FCM8201 3-Phase Sinusoidal Brushless DC Motor Controller
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