ALC5610 Datasheet 1.2

ALC5610-GR
ALC5610-GRT
AC97 AUDIO CODEC + TOUCH PANEL

CONTROLLER + VOICE PCM INTERFACE
DATASHEET
Rev. 1.2
11 January 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC5610
Datasheet
COPYRIGHT
2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document as is, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT

This document is intended for the hardware and software engineers general information on the Realtek
ALC5610 Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2007/06/07 First release
1.1 2007/08/15 Revised Table 85, page 68.
Added section 9.1.2 Recommended Operating Conditions, page 68.
1.2 2008/01/11 Revised section 1 General Description, page 1.
Revised Figure 1, page 4.
Revised Figure 2, page 5.
Added note in Table 4, page 9.
Revised Figure 7 to Figure 14, page 15 to 17.
Revised section 7.8.1 Speaker Output, page 24.
Revised section 7.9 Touch Panel Control, page 26.
Revised Table 21, page 36.
Revised section 10 Application Circuits, page 76.
Revised section 13 Ordering Information, page 81.
AC97 Audio Codec + Touch Panel Controller + ii Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................2
3. SYSTEM APPLICATIONS ...............................................................................................................................................3
4. FUNCTION BLOCK DIAGRAM.....................................................................................................................................4

4.1. FUNCTION BLOCK ........................................................................................................................................................4
4.2. AUDIO MIXER PATH .....................................................................................................................................................5
5. PIN ASSIGNMENTS..........................................................................................................................................................6
5.1. GREEN PACKAGE AND VERSION IDENTIFICATION .........................................................................................................6
6. PIN DESCRIPTIONS.........................................................................................................................................................7
6.1. AC97 DIGITAL I/O PINS ..............................................................................................................................................7
6.2. ANALOG I/O PINS ........................................................................................................................................................8
6.3. FILTER/REFERENCE ......................................................................................................................................................8
6.4. POWER/GROUND ..........................................................................................................................................................9
7. FUNCTIONAL DESCRIPTION .....................................................................................................................................10
7.1. POWER .......................................................................................................................................................................10
7.2. RESET ........................................................................................................................................................................10
7.2.1. Power-On Reset (POR) ........................................................................................................................................10
7.3. CLOCKING ..................................................................................................................................................................11
7.3.1. Phase-Locked Loop .............................................................................................................................................. 11
7.3.2. AC97 Mode .........................................................................................................................................................12
7.3.3. Voice_I2S/PCM Interface......................................................................................................................................12
7.3.4. Voice ADC ............................................................................................................................................................12
7.4. DIGITAL DATA INTERFACE ..........................................................................................................................................13
7.4.1. AC-Link ................................................................................................................................................................13
7.4.2. Voice I2S/PCM Interface.......................................................................................................................................15
7.5. AUDIO DATA PATH......................................................................................................................................................19
7.5.1. Stereo ADC and Voice ADC..................................................................................................................................19
7.5.2. Stereo DAC ...........................................................................................................................................................19
7.5.3. Voice to Stereo Digital Path..................................................................................................................................19
7.5.4. Voice DAC ............................................................................................................................................................20
7.6. MIXERS ......................................................................................................................................................................20
7.6.1. Headphone Mixer .................................................................................................................................................20
7.6.2. MONO Mixer........................................................................................................................................................21
7.6.3. Speaker Mixer.......................................................................................................................................................21
7.6.4. ADC Record Mixer ...............................................................................................................................................22
7.7. ANALOG AUDIO INPUT PATH ......................................................................................................................................22
7.7.1. Line Input .............................................................................................................................................................22
7.7.2. Phone Input ..........................................................................................................................................................23
7.7.3. Microphone Input .................................................................................................................................................23
7.7.4. MIC1N/AUX3 and MICBIAS2/AUX4 Pin Sharing...............................................................................................23
7.8. ANALOG AUDIO OUTPUT DATA PATH .........................................................................................................................24
7.8.1. Speaker Output .....................................................................................................................................................24
7.8.2. Headphone Output................................................................................................................................................25
7.8.3. MONO Output ......................................................................................................................................................25
7.9. TOUCH PANEL CONTROL ............................................................................................................................................26
AC97 Audio Codec + Touch Panel Controller + iii Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
7.10. AVC CONTROL ..........................................................................................................................................................27
7.11. HARDWARE SOUND EFFECTS .....................................................................................................................................28
7.11.1. Equalizer Block................................................................................................................................................28
7.11.2. Pseudo Stereo and Spatial 3D Sound...............................................................................................................28
7.12. ODD-ADDRESSED REGISTER ACCESS .........................................................................................................................28
7.13. POWER MANAGEMENT ...............................................................................................................................................29
7.13.1. Sleep Mode ......................................................................................................................................................29
7.14. GPIO AND INTERRUPT ...............................................................................................................................................30
8. MIXER REGISTERS LIST.............................................................................................................................................31
8.1. REG-00H: RESET ........................................................................................................................................................31
8.2. REG-02H: SPEAKER OUTPUT VOLUME .......................................................................................................................31
8.3. REG-04H: HEADPHONE OUTPUT VOLUME..................................................................................................................32
8.4. REG-08H: PHONE INPUT/MONO OUTPUT VOLUME ...................................................................................................32
8.5. REG-0AH: LINE_IN VOLUME ...................................................................................................................................33
8.6. REG-0CH: STEREO DAC VOLUME...........................................................................................................................33
8.7. REG-0EH: MIC VOLUME ...........................................................................................................................................34
8.8. REG-10H: MIC ROUTING CONTROL ...........................................................................................................................34
8.9. REG-12H: ADC RECORD GAIN...................................................................................................................................35
8.10. REG-14H: ADC RECORD MIXER CONTROL ................................................................................................................35
8.11. REG-18H: VOICE DAC OUTPUT VOLUME ..................................................................................................................36
8.12. REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................36
8.13. REG-22H: MICROPHONE CONTROL ............................................................................................................................37
8.14. REG-26H: POWER DOWN CONTROL/STATUS ..............................................................................................................37
8.15. REG-2AH: TONE CONTROL ........................................................................................................................................39
8.16. REG-2CH: AC97 STEREO DAC RATE/DPE RATE .....................................................................................................39
8.17. REG-32H: AC97 STEREO ADC RATE ........................................................................................................................40
8.18. REG-36H: EXTEND SERIAL DATA PORT CONTROL (VODAC_I2S/PCM) ....................................................................40
8.19. REG-3AH: POWER MANAGEMENT ADDITION 1 ..........................................................................................................41
8.20. REG-3CH: POWER MANAGEMENT ADDITION 2 ..........................................................................................................42
8.21. REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................43
8.22. REG-40H: GENERAL PURPOSE CONTROL REGISTER 1 ................................................................................................44
8.23. REG-42H: GENERAL PURPOSE CONTROL REGISTER 2 ................................................................................................45
8.24. REG-44H: PLL CONTROL ...........................................................................................................................................45
8.24.1. AC-Link PLL Clock Setting Table (Unit: MHz) ...............................................................................................46
8.25. REG-4CH: GPIO PIN CONFIGURATION .......................................................................................................................46
8.26. REG-4EH: GPIO PIN POLARITY .................................................................................................................................47
8.27. REG-50H: GPIO PIN STICKY ......................................................................................................................................47
8.28. REG-52H: GPIO PIN WAKE-UP ..................................................................................................................................48
8.29. REG-54H: GPIO PIN STATUS ......................................................................................................................................49
8.30. REG-56H: PIN SHARING .............................................................................................................................................49
8.31. REG-58H: OVER-TEMP/CURRENT STATUS ..................................................................................................................51
8.32. REG-5CH: GPIO_OUTPUT PIN CONTROL ...................................................................................................................52
8.33. REG-5EH: MISC CONTROL ........................................................................................................................................52
8.34. REG-64H: VODAC_PCM CLOCK CONTROL_1 ..........................................................................................................54
8.35. REG-66H: VODAC_PCM CLOCK CONTROL_2 ..........................................................................................................55
8.36. REG-68H: PSEUDO STEREO AND SPATIAL EFFECT BLOCK CONTROL ..........................................................................56
8.37. REG-6AH: INDEX ADDRESS........................................................................................................................................57
8.38. REG-6CH: INDEX DATA ..............................................................................................................................................57
8.39. REG-6EH: EQ STATUS ................................................................................................................................................57
8.40. INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1) ......................................................................................................58
8.41. INDEX-01H: EQ BAND-0 GAIN (LP0: HO)..................................................................................................................58
8.42. INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1) ......................................................................................................58
8.44. INDEX-04H: EQ BAND-1 GAIN (BP1: HO) .................................................................................................................59
AC97 Audio Codec + Touch Panel Controller + iv Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
8.47. INDEX-07H: EQ BAND-2 GAIN (BP2: HO) .................................................................................................................59
8.50. INDEX-0AH: EQ BAND-3 GAIN (BP3: HO).................................................................................................................60
8.51. INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1) .....................................................................................................60
8.52. INDEX-0CH: EQ BAND-4 GAIN (HPF: HO) ................................................................................................................60
8.53. INDEX-10H: EQ CONTROL AND STATUS REGISTER .....................................................................................................61
8.54. INDEX-11H: EQ INPUT VOLUME CONTROL ................................................................................................................61
8.55. INDEX-12H: EQ OUTPUT VOLUME CONTROL .............................................................................................................61
8.56. INDEX-20H: AUTO VOLUME CONTROL REGISTER 0 ...................................................................................................62
8.62. INDEX-39H: DIGITAL INTERNAL REGISTER.................................................................................................................63
8.63. INDEX-4AH: CLASS D TEMPERATURE SENSOR ...........................................................................................................64
8.64. INDEX-54H: AD_DA_MIXER_INTERNAL REGISTER ..................................................................................................64
8.65. REG-74H: TOUCH PANEL CONTROL BYTE 1 ...............................................................................................................65
8.66. REG-76H: TOUCH PANEL CONTROL BYTE 2 ...............................................................................................................66
8.67. REG-78H: TOUCH PANEL INDICATION.........................................................................................................................67
8.68. REG-7CH: VENDOR ID 1 .........................................................................................................................................67
8.69. REG-7EH: VENDOR ID 2..........................................................................................................................................67
9. ELECTRICAL CHARACTERISTICS...........................................................................................................................68
9.1. DC CHARACTERISTICS ...............................................................................................................................................68
9.1.1. Absolute Maximum Ratings ..................................................................................................................................68
9.1.2. Recommended Operating Conditions ...................................................................................................................68
9.1.3. Static Characteristics ...........................................................................................................................................68
9.2. ANALOG PERFORMANCE CHARACTERISTICS ..............................................................................................................69
9.3. SIGNAL TIMING ..........................................................................................................................................................72
9.3.1. Cold Reset.............................................................................................................................................................72
9.3.2. Warm Reset...........................................................................................................................................................72
9.3.3. AC-Link Clock Parameters...................................................................................................................................73
9.3.4. AC-Link Data Output and Input Timing ...............................................................................................................73
9.3.5. AC-Link Signal Rise and Fall Timing...................................................................................................................74
9.3.6. AC-Link Low Power Mode Timing .......................................................................................................................75
9.3.7. AC-Link IO Pin Capacitance and Loading ..........................................................................................................75
10. APPLICATION CIRCUITS .......................................................................................................................................76
11. MECHANICAL DIMENSIONS .................................................................................................................................77
12. APPENDIX A: VOICE PCM INTERFACE..............................................................................................................78

12.1. MASTER MODE: (VOICE_PORT_SEL=0) ......................................................................................................................78
12.2. SLAVE MODE: (VOICE_PORT_SEL=1) .........................................................................................................................80
13. ORDERING INFORMATION ...................................................................................................................................81
AC97 Audio Codec + Touch Panel Controller + v Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
List of Tables
TABLE 1. AC97 DIGITAL I/O PINS ..............................................................................................................................................7
TABLE 2. ANALOG I/O PINS.........................................................................................................................................................8
TABLE 3. FILTER/REFERENCE ......................................................................................................................................................8
TABLE 4. POWER/GROUND ..........................................................................................................................................................9
TABLE 5. POWER SETTING FOR BEST PERFORMANCE ................................................................................................................10
TABLE 6. RESET OPERATION......................................................................................................................................................10
TABLE 7. POWER-ON RESET VOLTAGE ......................................................................................................................................10
TABLE 8. AC-LINK CLOCK SETTING TABLE (UNIT: MHZ) ........................................................................................................11
TABLE 9. I2S SIGNAL LINK MASTER MODE CLOCK TABLE ........................................................................................................18
TABLE 10. PIN SHARING CONFIGURATION TABLE .......................................................................................................................23
TABLE 11. REG-00H: RESET ........................................................................................................................................................31
TABLE 12. REG-02H: SPEAKER OUTPUT VOLUME .......................................................................................................................31
TABLE 13. REG-04H: HEADPHONE OUTPUT VOLUME .................................................................................................................32
TABLE 14. REG-08H: PHONE INPUT/MONO OUTPUT VOLUME...................................................................................................32
TABLE 15. REG-0AH: LINE_IN VOLUME ...................................................................................................................................33
TABLE 16. REG-0CH: STEREO DAC VOLUME ..........................................................................................................................33
TABLE 17. REG-0EH: MIC VOLUME ...........................................................................................................................................34
TABLE 18. REG-10H: MIC ROUTING CONTROL...........................................................................................................................34
TABLE 19. REG-12H: ADC RECORD GAIN ..................................................................................................................................35
TABLE 20. REG-14H: ADC RECORD MIXER CONTROL................................................................................................................35
TABLE 21. REG-18H: VOICE DAC OUTPUT VOLUME ..................................................................................................................36
TABLE 22. REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................36
TABLE 23. REG-22H: MICROPHONE CONTROL ............................................................................................................................37
TABLE 24. REG-26H: POWER DOWN CONTROL/STATUS ..............................................................................................................37
TABLE 25. TRUTH TABLE FOR POWER DOWN MODE (PD=POWER DOWN) .................................................................................38
TABLE 26. REG-2AH: TONE CONTROL ........................................................................................................................................39
TABLE 27. REG-2CH: AC97 STEREO DAC RATE/DPE RATE .....................................................................................................39
TABLE 28. PC99/PC2001 DESIGN GUIDE SAMPLING RATES .......................................................................................................39
TABLE 29. REG-32H: AC97 STEREO ADC RATE ........................................................................................................................40
TABLE 30. PC99/PC2001 DESIGN GUIDE SAMPLING RATES .......................................................................................................40
TABLE 31. REG-36H: EXTEND SERIAL DATA PORT CONTROL (VODAC_I2S/PCM)....................................................................40
TABLE 32. REG-3AH: POWER MANAGEMENT ADDITION 1..........................................................................................................41
TABLE 33. REG-3CH: POWER MANAGEMENT ADDITION 2 ..........................................................................................................42
TABLE 34. REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................43
TABLE 35. REG-40H: GENERAL PURPOSE CONTROL REGISTER 1 ................................................................................................44
TABLE 36. REG-42H: GENERAL PURPOSE CONTROL REGISTER 2 ................................................................................................45
TABLE 37. REG-44H: PLL CONTROL ...........................................................................................................................................45
TABLE 38. AC-LINK PLL CLOCK SETTING TABLE (UNIT: MHZ) ................................................................................................46
TABLE 39. REG-4CH: GPIO PIN CONFIGURATION .......................................................................................................................46
TABLE 40. REG-4EH: GPIO PIN POLARITY .................................................................................................................................47
TABLE 41. REG-50H: GPIO PIN STICKY ......................................................................................................................................47
TABLE 42. REG-52H: GPIO PIN WAKE-UP ..................................................................................................................................48
TABLE 43. REG-54H: GPIO PIN STATUS ......................................................................................................................................49
TABLE 44. REG-56H: PIN SHARING .............................................................................................................................................49
TABLE 45. GPIO AND IRQ LOGIC ...............................................................................................................................................50
TABLE 46. REG-58H: OVER-TEMP/CURRENT STATUS .................................................................................................................51
TABLE 47. REG-5CH: GPIO_OUTPUT PIN CONTROL ..................................................................................................................52
TABLE 48. REG-5EH: MISC CONTROL .......................................................................................................................................52
TABLE 49. REG-64H: VODAC_PCM CLOCK CONTROL_1..........................................................................................................54
TABLE 50. REG-66H: VODAC_PCM CLOCK CONTROL_2..........................................................................................................55
TABLE 51. REG-68H: PSEUDO STEREO AND SPATIAL EFFECT BLOCK CONTROL ..........................................................................56
AC97 Audio Codec + Touch Panel Controller + vi Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
TABLE 52. REG-6AH: INDEX ADDRESS .......................................................................................................................................57
TABLE 53. REG-6CH: INDEX DATA..............................................................................................................................................57
TABLE 54. REG-6EH: EQ STATUS ................................................................................................................................................57
TABLE 55. INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1) ......................................................................................................58
TABLE 56. INDEX-01H: EQ BAND-0 GAIN (LP0: HO) .................................................................................................................58
TABLE 57. INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1) ......................................................................................................58
TABLE 59. INDEX-04H: EQ BAND-1 GAIN (BP1: HO) .................................................................................................................59
TABLE 62. INDEX-07H: EQ BAND-2 GAIN (BP2: HO) .................................................................................................................59
TABLE 65. INDEX-0AH: EQ BAND-3 GAIN (BP3: HO) ................................................................................................................60
TABLE 66. INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1).....................................................................................................60
TABLE 67. INDEX-0CH: EQ BAND-4 GAIN (HPF: HO) ................................................................................................................60
TABLE 68. INDEX-10H: EQ CONTROL AND STATUS REGISTER.....................................................................................................61
TABLE 69. INDEX-11H: EQ INPUT VOLUME CONTROL ................................................................................................................61
TABLE 70. INDEX-12H: EQ OUTPUT VOLUME CONTROL ............................................................................................................61
TABLE 71. INDEX-20H: AUTO VOLUME CONTROL REGISTER 0 ...................................................................................................62
TABLE 77. INDEX-39H: DIGITAL INTERNAL REGISTER ................................................................................................................63
TABLE 78. INDEX-4AH: CLASS D TEMPERATURE SENSOR ..........................................................................................................64
TABLE 79. INDEX-54H: AD_DA_MIXER_INTERNAL REGISTER ..................................................................................................64
TABLE 80. REG-74H: TOUCH PANEL CONTROL BYTE 1 ...............................................................................................................65
TABLE 81. REG-76H: TOUCH PANEL CONTROL BYTE 2 ...............................................................................................................66
TABLE 82. REG-78H: TOUCH PANEL INDICATION ........................................................................................................................67
TABLE 83. REG-7CH: VENDOR ID 1 .........................................................................................................................................67
TABLE 84. REG-7EH: VENDOR ID 2 .........................................................................................................................................67
TABLE 85. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................68
TABLE 86. RECOMMENDED OPERATING CONDITIONS .................................................................................................................68
TABLE 87. STATIC CHARACTERISTICS .........................................................................................................................................68
TABLE 88. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................69
TABLE 89. COLD RESET TIMING PARAMETERS ............................................................................................................................72
TABLE 90. WARM RESET TIMING PARAMETERS ..........................................................................................................................72
TABLE 91. AC-LINK CLOCK PARAMETERS .................................................................................................................................73
TABLE 92. AC-LINK DATA TIMING PARAMETERS .......................................................................................................................73
TABLE 93. AC-LINK SIGNAL RISE AND FALL TIMING PARAMETERS ............................................................................................74
TABLE 94. AC-LINK LOW POWER MODE TIMING PARAMETERS .................................................................................................75
TABLE 95. AC-LINK IO PIN CAPACITANCE PARAMETERS ...........................................................................................................75
TABLE 96. ORDERING INFORMATION ..........................................................................................................................................81
AC97 Audio Codec + Touch Panel Controller + vii Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4
FIGURE 2. AUDIO MIXER PATH ....................................................................................................................................................5
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................6
FIGURE 4. AC-LINK WAKE UP TIMING ......................................................................................................................................13
FIGURE 5. DEFAULT ALC5610 SLOT ARRANGEMENT CODEC ID ALWAYS 00 .......................................................................14
FIGURE 6. CONTROLLER AND CODEC CONNECTION ..................................................................................................................14
FIGURE 7. PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=0).....................................................................................15
FIGURE 8. PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=1).....................................................................................15
FIGURE 9. PCM MONO DATA MODE B FORMAT (BCLK_POLARITY=0) ....................................................................................16
FIGURE 10. PCM STEREO DATA MODE A FORMAT (BCLK_POLARITY=0)....................................................................................16
FIGURE 11. PCM STEREO DATA MODE B FORMAT (BCLK_POLARITY=0)....................................................................................16
FIGURE 12. I2S DATA FORMAT (BCLK_POLARITY=0)...................................................................................................................17
FIGURE 13. LEFT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0)...............................................................................................17
FIGURE 14. RIGHT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0).............................................................................................17
FIGURE 15. I2S SIGNAL LINK SLAVE MODE DIAGRAM (ALC5610 IS SLAVE) ..............................................................................18
FIGURE 16. I2S SIGNAL LINK MASTER MODE DIAGRAM (ALC5610 IS MASTER) .......................................................................18
FIGURE 17. 4-WIRE RESISTIVE TOUCH PANEL CIRCUIT ..............................................................................................................26
FIGURE 18. AUTO VOLUME CONTROL BLOCK DIAGRAM ............................................................................................................27
FIGURE 19. EXAMPLE OF ALC5610 POWER-DOWN/POWER-UP FLOW .......................................................................................29
FIGURE 20. GPIO IMPLEMENTATION ...........................................................................................................................................30
FIGURE 21. POWER CONTROL TO MIC INPUT .............................................................................................................................44
FIGURE 22. GPIO AND IRQ LOGIC .............................................................................................................................................50
FIGURE 23. JACK-INSERT-DETECT PULL-UP RESISTOR IMPLEMENTED VIA AN EXTERNAL CIRCUIT ............................................53
FIGURE 24. COLD RESET TIMING ................................................................................................................................................72
FIGURE 25. WARM RESET TIMING ...............................................................................................................................................72
FIGURE 26. DATA OUTPUT AND INPUT TIMING ............................................................................................................................73
FIGURE 27. SIGNAL RISE AND FALL TIMING ................................................................................................................................74
FIGURE 28. AC-LINK LOW POWER MODE TIMING......................................................................................................................75
AC97 Audio Codec + Touch Panel Controller + viii Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
1. General Description
The ALC5610 is a highly-integrated dual AC'97/PCM interface audio codec with multiple input/output
ports and a 4-wire touch panel controller. The ALC5610 is designed for mobile computing and
communications.
Stereo audio is supported via the AC97 interface, and voice functions via a PCM/I2S interface. To reduce
component count, the device can connect directly to:
A 4-wire touch panel
MONO or stereo differential analog inputs
Stereo headphone
Single-end or BTL MONO output
MONO or Stereo Bridge-Tied Load (BTL) speaker
Multiple analog input and output pins are provided for seamless integration with analog connected
wireless communication devices. Differential input/output connections efficiently reduce noise
interference, providing better sound quality. Class-AB or Class-D amplifiers are easily swapped via
simple register configuration, and the 1 Watt speaker removes the need for an additional amplifier, further
cutting both cost and required board area. Additionally, a flexible hardware 5-band equalizer with
configurable gain, bandwidth, and center frequency, and enriches the sound experience.
ALC5610 Digital power operates at supply voltages from 1.8V to 3.6V. Analog power operates from
2.3V to 3.6V, and Speaker power operates from 2.3V to 5V. To extend battery life, each section of the
device can be powered down individually under software control. Leakage current in maximum power
saving state is less than 10A.
The ALC5610 is available in a 7x7mm Green QFN package, making it ideal for use in handheld
portable systems.
AC97 Audio Codec + Touch Panel Controller + 1 Track ID: JATR-1076-21 Rev. 1.2
Voice PCM Interface
ALC5610
Datasheet
2. Features
Single-chip AC97 Rev 2.2 compatible codec
16-bit stereo DAC SNR 90dB, THD+N -85dB
16-bit stereo ADC SNR 85dB, THD+N -80dB
Supports PCM/I2S input and output interface
Supports all WinCE variable rates (8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,
48kHz)
One analog stereo input (LINE-IN)
One analog MONO single-ended or differential input (PHONE and PHONEN input)
Stereo, single-ended MONO, or differential analog microphone inputs, with boost pre-amplifiers
(+20/+30/+40dB)
BTL (Bridge-Tied Load) Max. output with on-chip 1W speaker driver (SPKVDD=5V, 8 load)
Stereo headphone output with on-chip 45mW headphone driver (HPVDD=3.3V, 16 load)
25mW SE or 75mW BTL MONO output support (AVDD=3.3V, 32 load)
Microphone switch detection
Integrated 16-bit I2S/PCM interface voice DAC for blue-tooth and other external devices
Power management and enhanced power saving
Supports digital 5 band equalizer (EQ)
Supports digital spatial sound and pseudo stereo effect
Supports pop noise suppression
Internal PLL can receive wide range of clock input (Digital IO power > 1.8V)
Digital power supplies from 1.8V to 3.6V, speaker amplifier power supplies from 2.3V to 5V
Analog power, headphone power, and touch panel power supplies from 2.3V to 3.6V
Voice PCM Interface
ALC5610
Datasheet
Resistive touch panel interface

Supports 4-wire panel
X, Y axis and pressure measurement
12-bit resolution AUX_ADC for battery measurement, DNL<1 LSB, INL<2 LSBs
Supports pen-down detection in power down mode
48-pin QFN package
3. System Applications
Tablet PC system/Ultra-Mobile PC (UMPC)
GPS/Personal Navigation Device (PND) or Multi-Media phone
PDA Phone/Smartphone
Personal Media Player (PMP)
Voice PCM Interface
ALC5610
Datasheet
4. Function Block Diagram

4.1. Function Block
ALC5610
MONO+ MONO_OUT
MONO- MONO_OUTN
LINE_IN_L DACL
LINE_IN_R ADCL
Input
PHONE DACR
Mixer ADCR SRC
PHONEN
VoiceDAC
AVC 45mW
HP_OUT_L
HPL
Output Mixer
45mW
MIC1 HP_OUT_R
MIC HPR
MIC1N
MIC2 Boost
MIC2N 700mW BTL SPK_OUT_L
SPKL+ /
SPKL- SPK_OUT_LN
MICBIAS EQ /
MICBIAS
MICBIAS2 3D
Control 700mW BTL SPK_OUT_R
VSDAC
SPKR+ /
VSADC GPIO / IIS SPKR- SPK_OUT_RN
VBCLK
VSLRCK
VREFOUT
X+
Clock 12 bits X-
AC-Link Interface Touch Panel
(PLL) ADC Y+
Y-
SDATA_OUT
RESET#
SDATA_IN
MCLK
SYNC
BIT_CLK
EXTCLK
IRQOUT
AUX4
AUX3
Figure 1. Block Diagram
Voice PCM Interface
R eg 14[ 12 ][ 4] 2
V o i c e_ I S/ P C M
M
R eg 14[ 11] [ 3]
L/ R
M
R eg 14[ 14] [ 6] L /L
R e g0 12[ 11: 7 ] R eg 3 6 [ 8]
M L /L
[ 4: 0]
Voice PCM Interface

R e g 14[ 13] [ 5] A D C- R
L/ L
G ai n
M A D C -L
R e g 012 [15 : 14] L /R
R eg 14[ 10] [ 2]
M
L/L A DC r ec or d
R eg 0 A [1 2:8] [ 4: 0 ] M
R e g0 A[ 15 ] L /L AV C
L I N E - I N _L / R M ixe r
R e g 1 4[8 ][ 0]
V ol M
P HO NE P R e g8[ 13 ] R eg 08[ 1 2:8 ] R eg 08[ 15]
M
A C
9 7/ S lo t 3 / 4
L/ R R e g 1 4[9 ][ 1] V o ic e to S te r e o D i g it a l p a th
V ol M L /R
PH O NE N
Reg 42 [ 15 ]
M
R eg 22[ 11: 1 0] L /L
M I C 1P R e g 1 0[ 1 2] R e g0E [1 2: 8] R e g10 [1 5]
L/ L
B oo st V ol M
M I C1 N A B/ D
4.2. Audio Mixer Path
S P K_ O UT _L/ R
M I C 2P R e g10 [4 ] R e g22 [9: 8 ] R eg 0E[ 4:0 ] R e g1 0[ 7] L/ L
Vol M
AC97 Audio Codec + Touch Panel Controller +

B o o st V ol M L/R
[ 12 : 11 ]
M I C2 N L /L R e g0 1 C [ 13] S P K _ O U T _ L N /R N
R e g- 02
Reg 1 C [ 15 : 14 ]
R e g0 C [1 2: 8] [4 : 0] R eg 0C [ 15] H P Mix er
A C9 7/ S lo t 3 /4
E Q /3 D D A Cs V ol M
Figure 2.
2 R e g18 [1 2: 8] R e g 18[ 15]
V oi c e _ I S / P C M
V o ic e D A C V ol M
R e g 012 [13 : 12]
5
V oi c e t o St e r eo D i gi t a l pa t h M
R e g0 A[ 13]
M
L +R L+R
AB
R e g 1 0[ 1 3]
H P_ O UT _ L/R
M Vol M
R e g10 [5 ]
Reg 1 C [ 9 : 8 ]
R e g- 04
M L +R
Audio Mixer Path

R eg 0C [ 13] M O N O Mix er
M
R e g 18[ 13]
m on o a n a lo g
s te r e o a na l o g R e g0 A[ 14]
M L+ R AB M O NO _ OU T
m o no d i gi tal R e g 0 8[ 1 4]
V ol M
s t e re o d i g i t al
M
Reg 1 C [ 7 : 6 ]
MO N O_ O UTN
R e g 1 0[ 1 4] R e g- 08 [ 7: 0 ]
S p ea ke r M ix e r
M
L +R
R e g10 [6 ]
M
R eg 0C [ 14]
Track ID: JATR-1076-21

M
A L C 5610 A u dio M ixer P ath R e g 18[ 14]
Rev. 1.2
Datasheet
ALC5610
ALC5610
Datasheet
5. Pin Assignments
G PI O3/ V SL R CK
G PI O2/I R Q O U T
G PI O 4 / V S DA C
G PI O 5/ V S A D C
G PI O1/ V B CLK
S P K_ O U T_ R N
H P_ O U T_ R
H P_ O U T_L
S PKV D D
HP GND
AGND 2
HPVDD
41
40
39
38
37
48
47
46
45
44
43
42
DVDD 1 1 36 SPK_ OUT_R
MCLK 2 35 SPK_ OUT_L
EXTCLK 3 34 SPKGND
DGND 1 4 33 SPK _OUT_ LN
SDATA _OUT 5 32 MONO_OUTN
BIT_ CLK 6 31 MONO_OUT
DGND 2 7 30 MIC2N
SDATA _IN 8 29 MIC2P
DVDD 2 9 28 MICBIAS
SYNC 10 27 VREF
RESET# / PENDOWN 11 26 AGND 1
AUX4 /MICBIAS2 12 25 AVDD 1

13
15
16
17
18
19
20
21
22
23
14
24
LI N E_I N_L
LI N E_I N_ R
TPVDD
TPGND
X+
Y+
X-
Y-
PH ONEP
PH ONEN
MI C1 P
MI C1 N /A U X3
Figure 3. Pin Assignments
5.1. Green Package and Version Identification

Green package is indicated by a G in the location marked T in Figure 3. The version number is shown
in the location marked V.
Voice PCM Interface
ALC5610
Datasheet
6. Pin Descriptions
6.1. AC97 Digital I/O Pins
Table 1. AC97 Digital I/O Pins
Name Type Pin Description Characteristic Definition
MCLK I 2 Master Clock Input Schmitt trigger
EXTCLK IO 3 External Reference Clock Output: VOL=0.1*DVDD, VOH =0.9*DVDD
Input/Output Input: Schmitt trigger
SDATA_OUT I 5 Serial TDM Data Input Schmitt trigger
BIT_CLK O 6 Bit Clock Output VOL=0.1*DVDD, VOH =0.9*DVDD
SDATA_IN O 8 Serial TDM Data Output VOL=0.1*DVDD, VOH =0.9*DVDD
SYNC I 10 48kHz Synchronous Input Signal Schmitt trigger
RESET#/ I/ 11 H/W Reset Input Schmitt trigger
PENDOWN O Pen-Down Output
GPIO1/VBCLK IO 44 General Purpose Input and Output 1 / GPIO: Input/Output
I2S interface Clock VBCLK: Slave input/Master output
GPIO2/IRQOUT IO 45 General Purpose Input and Output 2 / GPIO: Input/Output
Interrupt Output IRQOUT: Output
GPIO3/VSLRCK IO 46 General Purpose Input and Output 3 / GPIO: Input/Output
I2S Interface Frame Signal VSLRCK: Slave input/Master output
GPIO4/VSDAC IO 47 General Purpose Input and Output 4 / GPIO: Input/Output
I2S Interface Serial Data Input VSDAC: Schmitt trigger input
GPIO5/VSADC IO 48 General Purpose Input and Output 5 / GPIO: Input/Output
I2S Interface Serial Data Output VSADC: Voice data output
Total: 12 Pins
Voice PCM Interface
ALC5610
Datasheet
6.2. Analog I/O Pins

Table 2. Analog I/O Pins
AUX4/MICBIAS2 IO 12 Auxiliary Input 4/ Analog input (1Vrms) / Programmable
MIC BIAS Voltage Output 2 Analog DC Output with 3mA drive
X+ IO 14 Touch Panel Connect Input/Output X+ for 4-wire panel
Y+ IO 15 Touch Panel Connect Input/Output Y+ for 4-wire panel
X- IO 16 Touch Panel Connect Input/Output X- for 4-wire panel
Y- IO 17 Touch Panel Connect Input/Output Y- for 4-wire panel
PHONEP I 19 Phone Positive Input Analog Input (1Vrms)
PHONEN I 20 Phone Negative Input Analog Input (1Vrms)
MIC1P I 21 First Mic Positive Input Analog Input (1Vrms)
MIC1N/AUX3 I 22 First Mic Negative Input / Auxiliary Analog Input (1Vrms)
Input 3
MIC2P I 29 Second Mic Positive Input Analog Input (1Vrms)
MIC2N I 30 Second Mic Negative Input Analog Input (1Vrms)
LINE_IN_L I 23 Line Input Left Channel Analog Input (1Vrms)
LINE_IN_R I 24 Line Input Right Channel Analog Input (1Vrms)
MONO_OUT O 31 Positive MONO Output Analog Output (1vrms)
MONO_OUTN O 32 Negative MONO Output Analog Output (1vrms)
HP_OUT_L O 39 Headphone Output Left Channel Analog Output (1Vrms)
HP_OUT_R O 41 Headphone Output Right Channel Analog Output (1Vrms)
SPK_OUT_L O 35 Speaker Output Left Channel Analog Output (1.3Vrms, SPKVDD = 4.2V)
SPK_OUT_LN O 33 Negative Speaker Output Left Channel Analog Output (1.3Vrms, SPKVDD = 4.2V)
SPK_OUT_R O 36 Speaker Output Right Channel Analog Output (1.3Vrms, SPKVDD = 4.2V)
SPK_OUT_RN O 37 Negative Speaker Output Right Channel Analog Output (1.3Vrms, SPKVDD = 4.2V)
Total: 21 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
MICBIAS O 28 MIC BIAS Voltage Output Programmable Analog DC Output with 3mA drive
VREF O 27 Internal Reference Voltage 1f capacitor to analog ground
Total: 2 Pins
Voice PCM Interface
ALC5610
Datasheet
6.4. Power/Ground
Table 4. Power/Ground
DVDD1 P 1 Digital VDD 1.8V~3.6V (IO)
DGND1 P 4 Digital GND -
DGND2 P 7 Digital GND -
DVDD2 P 9 Digital VDD 1.8V~3.6V (Core)
TPVDD P 13 Analog VDD for Touch Panel 2.3V~3.6V
TPGND P 18 Analog GND for Touch Panel -
AVDD1 P 25 Analog VDD 2.3V~3.6V
AGND1 P 26 Analog GND -
SPKGND P 34 Analog GND for Speaker Amps -
SPKVDD P 38 Analog VDD for Speaker Amps 3.0V~5V (for Ohm loading)
2.3V~5V (for kOhm loading)
HPGND P 40 Analog GND for Headphone Amps -
AGND2 P 42 Analog GND -
HPVDD P 43 Analog VDD for Headphone Amps 2.3V~3.6V
LFGND P 49 Thermal Pad, Connect to SPKGND -
Total: 14 Pins
Note: DVDD1 DVDD2, SPKVDD AVDD1, HPVDD AVDD1 DVDD2, TPVDD DVDD2.
Note: SPDVDD connect 10F Capacitor to SPKVDD is required.
Voice PCM Interface
ALC5610
Datasheet
7. Functional Description
7.1. Power
The ALC5610 has many power blocks. SPKVDD operates between 2.3V and 5V. HPVDD, TPVDD and
AVDD1 operate between 2.3V and 3.6V. DVDD1 and DVDD2 operate between 1.8V and 3.6V. The
power supplier limit conditions are DVDD1DVDD2, SPKVDDAVDD1, HPVDDAVDD1DVDD2,
TPVDDDVDD2, and AVDD1=TPVDD
Table 5. Power Setting for Best Performance

Power DVDD1 DVDD2 HPVDD TPVDD AVDD1 SPKVDD
Setting 3.3V 1.8V 3.3V 3.3V 3.3V 4.2V
7.2. Reset
There are 4 types of reset operation: Power-On Reset (POR), Cold, Warm, and Register reset.
Table 6. Reset Operation

Reset Type Trigger Condition CODEC Response
POR Power-On Reset. Monitor digital power Resets all hardware logic and all registers to default values.
supply voltage reaches VPOR
Cold Reset Asserts RESET# for a specified period Resets all hardware logic and all registers to default values
except some PLL related control registers and logic.
Register Reset Write Reg-00h Resets all registers to default values except some PLL
related control registers and logic.
Warm Reset Drives SYNC high for specified period Reactivates AC-Link. No change to register values.
without BIT_CLK
7.2.1. Power-On Reset (POR)

When powered on, DVDD2 passes through the VPOR band of the ALC5610 (VPOR_ON ~VPOR_OFF). A
Power-On Reset (POR) will generate an internal reset signal (POR reset LOW) to reset the whole chip.
Table 7. Power-On Reset Voltage

Symbol Min Typical Max Unit
VPOR_ON 1.0 - 1.6 V
VPOR_OFF - 1.3 - V
Note: VPOR_OFF must be below VPOR_ON.
Voice PCM Interface
ALC5610
Datasheet
7.3. Clocking
The Stereo_SYSCLK can be selected from MCLK or PLL. This means MCLK is always provided
externally, and the driver should arrange the clock of each block and setup each divider.
The voice codec clock can be selected from MCLK (Master mode), PLL (Master mode), EXTCLK (Slave
mode) or VBCLK (Slave mode). The driver should arrange the clock of each block and setup each
divider.
In master mode of voice I2S/PCM, EXTCLK can be output by setting Extclk_dir=1. The output frequency
will be determined by MCLK and the setting of Extclk_out_sel.
7.3.1. Phase-Locked Loop

A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. Typical
choices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to MCLK or MCLK/2
by setting PLL_pre_div.
The ALC5610 SYSCLK frequency is 24.576MHz. If the system cannot provide 24.576MHz to the
ALC5610, the PLL of the ALC5610 can be used to generate a frequency near 24.576MHz. As the PLL
parameter is configured through the AC link, the input clock to the MCLK pin must be between
2.048MHz and 80MHz. After the AC link is connected, the driver must configure the PLL in order to
output a frequency close to the SYSCLK (24.576MHz). The accuracy of audio output frequency will
depend on the accuracy of PLL output.
The PLL transmit formula is:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 8. AC-Link Clock Setting Table (Unit: MHz)

MCLK N M FVCO K FOUT
13 66 7 98.222 2 24.555
3.6864 78 1 98.304 2 24.576
2.048 94 0 98.304 2 24.576
4.096 70 1 98.304 2 24.576
After a Cold Reset, PLL related Registers are reset to default values, however, they are not reset to
default values after a soft-reset (write Reg00). Firmware should not power down the PLL when the PLL
output is used as Stereo_SYSCLK.
Note: The ALC5610 will only be enabled after an AC-Link Warm Reset.
Voice PCM Interface
ALC5610
Datasheet
7.3.2. AC97 Mode

For the AC-Link controller, the BIT_CLK driven by PLL will only be enabled after a warm reset.
The sampling rate of the stereo ADC and stereo DAC can be configured separately and is controlled by
Reg2C (stereo DAC) and Reg32 (stereo ADC).
7.3.3. Voice_I2S/PCM Interface

The ALC5610 supports an independent digital interface for Voice Audio. The voice audio digital
interface is used to input digital data to the voice DAC, or output digital data from the voice ADC. The
Voice Audio Digital Interface can be configured to Master mode or Slave mode. Whether in Master mode
or Slave mode, the sample rate of the Voice ADC and Voice DAC is set via Reg64 and Reg66.
In Master mode, the main clock of the Voice_I2S/PCM interface can be input selected from MCLK (with
or without a PLL) or EXTCLK. VBCLK and VSLRCK will be configured as output. DRIVER has to set
each divider (Reg64 & Reg66) to arrange the clock distribution. See section 12 Appendix A: Voice PCM
Interface, page 78 for details.
In Slave mode, the main clock of the Voice_I2S/PCM can be input from MCLK or EXTCLK. VBCLK is
synchronized externally. VBCLK and VSLRCK will be configured as input. The driver has to set each
divider (Reg64 and Reg66) to arrange the clock distribution (see section 12.2 Slave Mode:
(voice_port_sel=1), page 80, for more information.
If VBCLK provides 64Fs, 128Fs, or 256Fs externally, the ACL5610 can use VBCLK input as the main
clock of the Voice_I2S/PCM. See section 12 Appendix A: Voice PCM Interface, page 78 for details.
7.3.4. Voice ADC

The ALC5610 supports Voice ADC for transmitting voice data to a Bluetooth device. The Voice ADC is
implemented by sharing from the Right Channel of the Stereo ADC (by setting voice_adc_enable).
When voice_adc_enable=0, the L/R channel stereo ADC sample rate is set according to the stereo sample
rate (ADC_SAMPLE_RATE) and output to slots 3 & 4 of the AC97 interface.
When voice_adc_enable=1, the sample rate of the Left channel is set by the stereo sample rate
(ADC_SAMPLE_RATE). The sample rate of the Right channel is set by the voice sample rate (Reg64 &
Reg66). The Left channel ADC data is output to the Left (slot 3) and duplicated to the Right (slot 4) of
the AC97 interface. The Right channel of the Stereo ADC data is then used as a Voice ADC and output
to voice_I2S/PCM.
Voice PCM Interface
ALC5610
Datasheet
7.4. Digital Data Interface

7.4.1. AC-Link
When the ALC5610 takes serial data from the AC97 controller, it samples SDATA_OUT on the falling
edge of BIT_CLK. When the ALC5610 sends serial data to the AC97 controller, it starts to drive
SDATA_IN on the rising edge of BIT_CLK.
The ALC5610 will return any uninstalled bit or register read operations with 0. The ALC5610 also stuffs
an unimplemented slot or bit with 0 in SDATA-IN. Note that AC-Link is MSB-justified.
See the Audio CODEC 97 Component Specification Revision 2.2 for detailed information.
Figure 4. AC-Link Wake Up Timing
Voice PCM Interface
ALC5610
Datasheet
If wakeup control (Reg52 & Reg5E[1]) is enabled during Sleep state, the ALC5610 will assert
SDATA_IN and IRQOUT when interrupted.
SLOT# 0 1 2 3 4 5 6 7 8 9 10 11 12
SYNC
SDATA-OUT TAG CMD DATA PCML PCMR
TAG ADDR DATA PCML PCMR AUX Status
SDATA-IN OR
TAG ADDR DATA PCML PCMR Pipeline Status
Figure 5. Default ALC5610 Slot Arrangement CODEC ID Always 00
Application
Processor
AC97 Controller AC97

Primary
AC97_RESET_n nRESET
AC97_SDATA_OUT SDATA_OUT Codec
AC97_SYNC (48 kHz) SYNC
AC97_SDATA_IN_0 SDATA_IN
AC97_SDATA_IN_1
AC97_BITCLK (12.288 MHz) BIT_CLOCK
AC97_SYSCLK (Optional)
(24.5 MHz)
Figure 6. Controller and Codec Connection
Voice PCM Interface
ALC5610
Datasheet
7.4.2. Voice I2S/PCM Interface

The voice interface can be configured as Master mode or Slave mode. Four audio data formats are
supported:
PCM mode
Left justified mode
Right justified mode
I2S mode
Figure 7. PCM MONO Data Mode A Format (bclk_polarity=0)
Figure 8. PCM MONO Data Mode A Format (bclk_polarity=1)
Voice PCM Interface
ALC5610
Datasheet
Figure 9. PCM MONO Data Mode B Format (bclk_polarity=0)
Figure 10. PCM Stereo Data Mode A Format (bclk_polarity=0)
Figure 11. PCM Stereo Data Mode B Format (bclk_polarity=0)

Voice PCM Interface
ALC5610
Datasheet
Figure 12. I2S Data Format (bclk_polarity=0)
Figure 13. Left-Justified Data Format (bclk_polarity=0)
Figure 14. Right-Justified Data Format (bclk_polarity=0)
Voice PCM Interface
ALC5610
Datasheet
Figure 15. I2S Signal Link Slave Mode Diagram (ALC5610 is Slave)
Figure 16. I2S Signal Link Master Mode Diagram (ALC5610 is Master)
Table 9. I2S Signal Link Master Mode Clock Table

SYSCLK BITCLK SYNC
12.235MHz 3.058MHz 47.794K (closest std = 48kHz)
11.346MHz 2.836MHz 44.318K (closest std = 44.1kHz)
2.811MHz 702.75kHz 10.980K (closest std = 11.025kHz)
2.053MHz 513.25kHz 8.0194K (closest std = 8.00kHz)
Voice PCM Interface
ALC5610
Datasheet
7.5. Audio Data Path

7.5.1. Stereo ADC and Voice ADC
The stereo ADC is used for recording stereo sound or, by setting voice_adc_enable, can be configured to
MONO PCM ADC (Left channel of stereo ADC) + voice ADC (Right channel of stereo ADC) when
using bluetooth and recording at the same time.
When voice_adc_enabl=0, the sample rate of the stereo ADC can be configured via setting Reg32.
When voice_adc_enabl=1, the sample rate of the voice ADC is set by Reg66, and the sample rate of
the MONO PCM ADC is set by Reg32.
The sample rate of the stereo ADC is independent of the stereo DAC sample rate.
In order to save power, the left and right ADC can be powered down separately by setting Reg3C [6], [7].
PR0=1 will disable both channels of the ADC.
The volume control of the stereo ADC is set via Reg12[11:7][4:0].
7.5.2. Stereo DAC

The sample rate of the stereo DAC is controlled by Reg2C.
Reg0C[12:8][4:0] can be used to control the volume of DAC output.
7.5.3. Voice to Stereo Digital Path

The ALC5610 supports a voice to digital stereo path for voice command through Bluetooth by setting
Reg42[15]=1. The Voice data will be transferred from the voice I2S/PCM to the AC97 directly. This
function is only supported when the Voice and Stereo I2S/PCM are in Master Mode. The driver should set
the same sample rate between the Voice DAC and the stereo ADC.
When a voice to stereo digital path is enabled, the signal from Voice_I2S/PCM is direct output to Left
(slot 3) and is duplicated to Right (slot 4) of the AC97 interface.
The Voice to Stereo Digital Path and Voice ADC functions can exist at the same time.
Voice PCM Interface
ALC5610
Datasheet
7.5.4. Voice DAC

The Voice DAC is dedicated to playback of received voice signals from the voice_I2S/PCM interface.
Typically, it is used at an 8kHz sample rate.
In Voice I2S/PCM Master mode, the sample rate is set by the VoDAC clock Divider (Reg64). In addition,
Reg66[7:4][2:0] is used to set the over-sample rate clock divider of the Voice ADC/DAC filter to 64Fs or
128Fs. Reg66[13] must be set according to the over-sample rate clock.
Performance at 128Fs is better than 64Fs, but with higher power consumption. For best performance, the
frequency of the Voice DAC Sigma Delta clock must be equal to, or higher than, the Voice DA filter
over-sampling rate. The volume control of the Voice DAC is set via Reg18[12:8].
7.6. Mixers
The ALC5610 supports four mixers for all audio function requirements:
Headphone mixer for 2 channels
MONO mixer
Speaker mixer
ADC record mixer
7.6.1. Headphone Mixer

The headphone mixer is used to drive stereo output, including HP_OUT_L/R, SPK_OUT_L/R
(SPK_OUT_LN/RN) and MONO_OUT (MONO_OUTN). The output of the headphone mixer can be
input to the ADC record mixer.
The following signals can be mixed into the headphone mixer:

LINE-IN_L/R (Controlled by Reg0A)
PHONEP/N (Controlled by Reg08)
MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
Stereo DAC output (Controlled by Reg0C)
Voice DAC output (Controlled by Reg18)
ADC record mixer output (Controlled by Reg12 & Reg14).
Note: The headphone mixer can be powered down by setting Reg3C[5][4].
Voice PCM Interface
ALC5610
Datasheet
7.6.2. MONO Mixer

The MONO mixer is used to drive MONO_OUT (MONO_OUTN) and SPK_OUT_L/R
(SPK_OUT_LN/RN). The output of the MONO mixer can be input to the ADC record mixer. The output
of the MONO mixer is two channels with the same signal.
The following signals can be mixed into the MONO mixer:

ADC record mixer output (Controlled by Reg12 & Reg14).
Note: The MONO mixer can be powered down by setting Reg3C[2].
7.6.3. Speaker Mixer

The speaker mixer is the same as the MONO mixer and is used to drive MONO_OUT (MONO_OUTN)
and SPK_OUT_L/R (SPK_OUT_LN/RN). The output of the speaker mixer can be input to the ADC
record mixer. The output of the speaker mixer is two channels with the same signal.
The following signals can be mixed into the speaker mixer:

Note: The speaker mixer can be powered down by setting Reg3C[3].
Voice PCM Interface
ALC5610
Datasheet
7.6.4. ADC Record Mixer

The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording. Output of
the ADC record mixer can be input to the headphone mixer, MONO mixer, and speaker mixer.
The following signals can be mixed into the ADC record mixer:
Headphone mixer output
MONO mixer output
Speaker mixer output
Note: The ADC record mixer can be powered down by setting Reg3C[1][0].
7.7. Analog Audio Input Path

The ALC5610 supports four Analog Audio Input paths:
Line_IN_L/R
PHONEP/N
MIC1
MIC2
7.7.1. Line Input

Line_In_L and Line_In_R provide 2-channel stereo single-ended input that can be mixed into the MONO
mixer, Headphone mixer, Speaker mixer, or the ADC record mixer.
The Line_In_L/R volume and mute are controlled by Reg0A. Reg3E[7:6] can be used to power down
Line_In volume control.
Voice PCM Interface
ALC5610
Datasheet
7.7.2. Phone Input

PHONEP/N provides one-channel MONO differential or single-ended input configured by Reg08[13]
that can be mixed into the ADC record mixer, or any analog output mixer except for the MONO mixer.
PHONEP is main input when differential mode is disabled.
The PHONEP/N volume and mute are controlled by Reg08. Reg3E[5:4] can be used to power down the
PHONEP/N volume control and mixer.
7.7.3. Microphone Input

MIC1P/N and MIC2P/N provide two-channel stereo differential or single-ended input via Reg10[12], [4],
that can be mixed into the ADC record mixer, or any analog output mixer. MIC1P and MIC2P are main
inputs when differential mode is disabled. MIC1N is pin-shared to AUX3 input.
The ALC5610 Microphone input boost provides 20/30/40dB boost, set by Reg22[11:10] (for MIC1), and
by Reg22[9:8] (for MIC2). The MIC1/2 volume and mute are controlled by Reg0E.
For detailed power management of MIC1/2, Reg3E[3][2] can be used to power down the MIC1/2 volume
control. Reg3E[1][0] can be used to power down MIC1/2 and mixer.
7.7.4. MIC1N/AUX3 and MICBIAS2/AUX4 Pin Sharing

MIC1N is pin-shared with AUX3 input of AUX_ADC. MICBIAS2 is pin-shared with AUX4 input of
AUX_ADC. The driver must set the related register as shown in Table 10.
Table 10. Pin Sharing Configuration Table

AUX3_micin_ AUX4_micbias2_ Reg76[0]: Reg76[7]: Reg10[12]: Reg3A[2]:
sharing sharing Aux_measure_sel AUX_measure_en micl_diff_ctrl pow_mic2_bias
MIC1N AUX4 AUX4 (0b) - - Disable (0b)
MIC1N MICBIAS2 - 0b - -
AUX3/AUX4
AUX3 AUX4 - Disable (0b) Disable (0b)
(1b/0b)
AUX3 MICBIAS2 AUX3 (1b) - Disable (0b) -
Voice PCM Interface
ALC5610
Datasheet
7.8. Analog Audio Output Data Path

The ALC5610 supports three Analog Audio output paths:
SPK_OUT_L/R
HP_OUT_L/R
MONO_OUT
7.8.1. Speaker Output

SPK_OUT_L/R provides two-channel differential output.
The SPK_OUT_L source is set in Reg1C[15:14]. Sources are shown below:

Vmid
Headphone left mixer
Speaker mixer
MONO mixer
The SPK_OUT_R source is set in Reg1C[12:11]. Sources are shown below:

Vmid
Headphone right mixer
Speaker mixer
MONO mixer
The ALC5610 speaker supports Class AB and Class D type amplifiers (set in Reg1C[13]:spk_out_sel).
As the voltage of SPKVDD is usually higher than AVDD, the driver should set the Class AB Vmid ratio
in Reg40[5:3], and the Class D Vmid ratio in Reg40[7:6] in order to extend the output level.
In class AB mode, for L+R MONO speaker solutions, SPK_OUT_R can select a different signal source
(SPKR Volume output or SPKL Volume output by Reg1C[14]) but SPK_OUT_RN only outputs SPKR
Volume Negative Output.
The SPK_OUT_L/R volume and mute are controlled by Reg02.

Reg3E[13:12] and Reg3E[9:8] can be used to power down SPK output.
Reg3C[14]: pow_clsab is used to power down Class AB output.
SPK_OUT_L/R supports the zero-cross detect function (enabled at Reg02[6][14]: sp_l_dezero/

sp_r_dezero).
Voice PCM Interface
ALC5610
Datasheet
7.8.2. Headphone Output

HP_OUT_L/R provides two-channel single-ended output. The HP_OUT_L/R source is set in
Reg1C[9][8]. Sources are shown below:
Vmid
Headphone mixer
The HP_OUT_L/R volume and mute are controlled by Reg04.
Reg3E[11]: pow_hp_l_vol and Reg3E[10]: pow_hp_r_vol can be used to power down the volume of HP
output.
HP_OUT supports the zero-cross detect function (enabled at Reg04[14][6]:hp_l_dezero/ hp_r_dezero).
7.8.3. MONO Output

MONO_OUT provide one-channel differential or single-ended output configured by Reg08[15]. The
MONO_OUT source is set in Reg1C[7:6]. Sources are shown below:
Vmid
Headphone mixer (L+R)
Speaker mixer
MONO mixer
The MONO_OUT volume and mute are controlled by Reg08.
Reg3E[14]: pow_MONO_out_vol can be used to power down the volume of MONO_OUT.
MONO_OUT supports the zero-cross detect function (enabled at Reg08[6]:MONO_dezero).
Voice PCM Interface
ALC5610
Datasheet
7.9. Touch Panel Control

The ALC5610 provides 4-wire resistive touch panel control. X-position, Y-position, Pen-down detection,
touch pressure, and AUX measurement are supported by using AUX_ADC.
There are 2 modes within the touch panel measurement: Continuous mode (Reg76[14]=1), and polling
mode (Reg76[14]=0).
Figure 17. 4-Wire Resistive Touch Panel Circuit
Continuous Mode
The ALC5610 automatically initializes the measurement at the rate set in Reg74[1:0], and sends the
measured data back to the AC97 Controller. It is strongly recommended that the total measure time of
one measure cycle (Delay time + measure time) not be longer than the measurement frame period
(1/measurement rate).
Polling Mode
In polling mode the AC97 Controller starts each measurement by setting the measure item and writing
Reg76[15] =1. The ALC5610 will clear the Reg76[15] after measurement is complete.
Voice PCM Interface
ALC5610
Datasheet
7.10. AVC Control

The Automatic Volume Control (AVC) function dynamically adjusts the input signal quantized by the
ADC to an expected sound level by setting THmax and THmin.
When the average level of input signal is higher than THmax, the AVC will decrease the selected analog
gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower amplitude than THmax.
When the average level of input signal is lower than THmin, the AVC will increase the selected analog
gain to amplify the input signal. The quantized Pulse Code Modulation (PCM) signal is then set higher
than THmin. The quantized PCM has an average level between THmin and THmax.
The AVC reference source channel and target channel can be individually set by Index20[0] and
Reg5E[13:12].
The AVC architecture is shown in Figure 18 below:
Figure 18. Auto Volume Control Block Diagram
Voice PCM Interface
ALC5610
Datasheet
7.11. Hardware Sound Effects

The Sound Effect block is composed of Pseudo Stereo, Spatial 3D and Equalizer blocks. The Pseudo
Stereo block is used to convert a MONO source into virtualized stereo output. The Spatial 3D block is a
surround sound generator with adjustable amplitude (Gain) and surround depth (Ratio). The Equalizer
block can be used to compensate for speaker response, or to make environment sound effects, e.g., Pub,
Live, Rock, etc..
7.11.1. Equalizer Block

The Equalizer block cascades 5 bands of equalizer to compensate for speaker response and to emulate
environment sound. One high-pass filter cascaded in the front end is used to drop low frequency tone,
which has a larger amplitude and may damage a mini speaker.
The high-pass filter can also be used to adjust Treble strength with gain control. A low-pass filter with
gain control can adjust the Bass strength. Three bands of bi-quad bandpass filters are used to emulate
environment sounds.
To avoid PCM sample saturation, the digital volume control has up to 18dB of attenuation before the
equalizer. A 0~+18dB digital gain after the equalizer is used to correct PCM output to a suitable level.
7.11.2. Pseudo Stereo and Spatial 3D Sound

There are two spatial effects in post-processing; the Pseudo-Stereo Effect + Spatial Effect, and the Stereo
Expansion Effect. The Pseudo-Stereo Effect + Spatial Effect converts a MONO signal to a stereo signal
by changing the phase and amplitude of the original signal followed by enhancing the spatial effect. The
Stereo Expansion Effect enhances the spatial effect when the input signal is Stereo.
7.12. Odd-Addressed Register Access

The ALC5610 will return 0000h when odd-addressed and unimplemented registers are read.
Voice PCM Interface
ALC5610
Datasheet
7.13. Power Management

The ALC5610 supports a standard power down control register as defined in AC97 (Reg26). More
detailed Power Management control is supported in Reg 3C & 3E. Each particular block will only be
active when both Reg26 and Reg3C/3E are set to Enable.
7.13.1. Sleep Mode

When PR4 (Reg26) is set, the ALC5610 will enter Sleep Mode. Before entering sleep mode, the driver
can set other control bits to save power according to system requirements.
The following functions should be kept operating during sleep mode:

Pen-down Detection
GPIO and Interrupts
Analog to analog path when control registers Reg 3C & 3E are enabled
There are two methods to wake the ALC5610 from Sleep mode
Warm Reset and Cold Reset from AC Link
Wake-up from GPIO (configured as Input) and Internal event signal (pen-down, over-temperature)
when the wake-up bit is set at Reg52.
Figure 19. Example of ALC5610 Power-Down/Power-Up Flow
Voice PCM Interface
ALC5610
Datasheet
7.14. GPIO and Interrupt

The ALC5610 supports up to five GPIOs. Each GPIO can be configured as Input/Output by Reg4C.
When GPIOs are configured as Input, the status will be indicated in Reg54 and Slot 12. When GPIOs are
configured as Output, Reg5C is used to drive GPIOs to High (1b) or Low (0b). The status can be read in
Reg54.
Interrupt request (IRQ) function can be configured as:

Sticky by setting Reg50
Changed polarity by setting Reg4E
Wake-up by setting Reg52
The wake-up function will drive SDATA_In high when the AC-Link is in sleep mode, and set
GPIO_INT (Slot12 bit0) when the AC-Link is awake. The wake up function can only be enabled when
Wake-up control (Reg5E[1])=1. The driver can write each bit of Reg54=1 to clear each IRQ status flag.
When VoPCM_En (Reg36[15])=1, GPIOs 1, 3, 4, and 5 will be dedicated as VoDAC_I2S/PCM interface,

regardless of GPIO Pin Configure (Reg4C[5:3,1)). These pin cannot be used as GPIOs in this case.
GPIO pin2 can be configured and pin-shared with IRQ_Output by setting Reg56.
Figure 20. GPIO Implementation
There are some internal events (pen-down, over-temperature, MICBIAS short detect) where GPIOs can
be an interrupt source. GPIO Internal event application is located in Reg4C, Reg4E, Reg50, Reg52, and
Reg54.
Voice PCM Interface
ALC5610
Datasheet
8. Mixer Registers List

Accessing odd numbered registers, or reading unimplemented registers, will return a 0.
8.1. Reg-00h: Reset

Default: 59B4h
Table 11. Reg-00h: Reset

Name Bits Read/Write Reset State Description
Reserved 15 R 0h Reserved. Read as 0
REG-00_b14_b10 14:10 R 16h SE[4:0]=10110b
REG-00_b9 9 R 0h No Support for 20-Bit ADC
REG-00_b8 8 R 1h Supports 16-Bit ADC
REG-00_b7 7 R 1h Supports 16-Bit DAC
REG-00_b6 6 R 0h No Support for 18-Bit DAC
REG-00_b5 5 R 1h Support for Loudness
REG-00_b4 4 R 1h Headphone Output Support
Reserved 3 R 0h Reserved
REG-00_b2 2 R 1h Supports EQ Control
REG-00_b0 0 R 0h Dedicated MIC PCM input is not supported. Can be for
touch panel ADC use
Note: Writes to this register will reset all registers to their default values except PLL related Register. The written data
will be ignored
8.2. Reg-02h: Speaker Output Volume

Default: 8080h
Table 12. Reg-02h: Speaker Output Volume

sp_l_mute 15 RW 1h Mute Left Control
0: On 1: Mute Left Channel (-dB)
sp_l_dezero 14 RW 0h Left Zero-Cross Detector Control
0: Disable 1: Enable
sp_l_vol 12:8 RW 0h Speaker Output Left Volume (SPKL[4:0]) in 1.5dB Steps
sp_r_mute 7 RW 1h Mute Right Control
0: On 1: Mute Right Channel (-dB)
sp_r_dezero 6 RW 0h Right Zero-Cross Detector Control
sp_r_vol 4:0 RW 0h Speaker Output Right Volume (SPKR[4:0]) in 1.5dB Steps
Note: For SPKR/SPKL, 00h: 0dB attenuation 1Fh: 46.5dB attenuation
Voice PCM Interface
ALC5610
Datasheet
8.3. Reg-04h: Headphone Output Volume

Default: 8080h
Table 13. Reg-04h: Headphone Output Volume

hp_l_mute 15 RW 1h Mute Left Control
0: On 1: Mute Left Channel (-dB)
hp_l_dezero 14 RW 0h Left Zero-Cross Detector Control
hp_l_vol 12:8 RW 0h Headphone Output Left Volume (HPL[4:0]) in 1.5dB Steps
hp_r_mute 7 RW 1h Mute Right Control
0: On 1: Mute Right Channel (-dB)
hp_r_dezero 6 RW 0h Right Zero-Cross Detector Control
hp_r_vol 4:0 RW 0h Headphone Output Right Volume (HPR[4:0]) in 1.5dB Steps
Note: For HPR/HPL, 00h: 0dB attenuation 1Fh: 46.5dB attenuation
8.4. Reg-08h: Phone Input/MONO Output Volume

Default: C880h
Table 14. Reg-08h: Phone Input/MONO Output Volume

phone2hp_mute 15 RW 1h Mute Phone Input to Headphone Mixer Control
0: On 1: Mute (-dB)
phone2spk_mute 14 RW 1h Mute Phone Input to Speaker Mixer Control
0: On 1: Mute (-dB)
phone_diff_ctrl 13 RW 0h Phone Differential Input Control
phone_vol 12:8 RW 8h Phone Input Volume (PV[4:0]) in 1.5dB Steps (not to ADC)
MONO_mute 7 RW 1h Mute MONO Output Control
0: On 1: Mute (-dB)
MONO_dezero 6 RW 0h Zero-Cross Detector Control
MONO_diff_ctrl 5 RW 0h MONO Output Differential Control
0: Disable (SE) 1: Enable (BTL)
MONO_vol 4:0 RW 0h MONO Output Master Volume (MOV[4:0]) in 1.5dB Steps
Note: For MOV, 00h: 0dB attenuation 1Fh: 46.5dB attenuation
For PV, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation
Voice PCM Interface
ALC5610
Datasheet
8.5. Reg-0Ah: LINE_IN Volume

Default: E808h
Table 15. Reg-0Ah: LINE_IN Volume

li2hp_mute 15 RW 1h Mute Volume Output to Headphone Mixer Control
0: On
1: Mute
li2spk_mute 14 RW 1h Mute Volume Output to Speaker Mixer Control
0: On
1: Mute
li2MONO_mute 13 RW 1h Mute Volume Output to MONO Mixer Control
0: On
1: Mute
li_l_vol 12:8 RW 08h LINE_IN Left Volume (NLV[4:0]) in 1.5dB Steps
Reserved 7:5 R 0h Reserved
li_r_vol 4:0 RW 8h LINE_IN Right Volume (NRV[4:0]) in 1.5dB Steps
Note: For NRV/NLV, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation
8.6. Reg-0Ch: STEREO DAC Volume

Default: E808h
Table 16. Reg-0Ch: STEREO DAC Volume

dac2hp_mute 15 RW 1h Mute Volume Output to Headphone Mixer Control
0: On
1: Mute (-dB)
dac2spk_mute 14 RW 1h Mute Volume Output to Speaker Mixer Control
0: On
1: Mute (-dB)
dac2MONO_mute 13 RW 1h Mute Volume Output to MONO Mixer Control
0: On
1: Mute (-dB)
dac_l_vol 12:8 RW 08h PCM Left DAC Volume (PLV[4:0]) in 1.5dB Steps
dac_r_vol 4:0 RW 8h PCM Right DAC Volume (PRV[4:0]) in 1.5dB Steps
Note: For PRV/PLV,: 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation
Voice PCM Interface
ALC5610
Datasheet
8.7. Reg-0Eh: MIC Volume

Default: 0808h
Table 17. Reg-0Eh: MIC Volume

mic1_vol 12:8 RW 08h MIC1 Volume (M1V[4:0]) in 1.5dB Steps
mic2_vol 4:0 RW 8h MIC2 Volume (M2V[4:0]) in 1.5dB Steps
For M2V/M1V, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation
8.8. Reg-10h: MIC Routing Control

Default: E0E0h
Table 18. Reg-10h: MIC Routing Control

mic12hp_mute 15 RW 1h Mute MIC1 Volume Output to Headphone Mixer
0: On 1: Mute
mic12spk_mute 14 RW 1h Mute MIC1 Volume Output to Speaker Mixer
0: On 1: Mute
mic12MONO_mute 13 RW 1h Mute MIC1 Volume Output to MONO Mixer
0: On 1: Mute
mic1_diff_ctrl 12 RW 0h MIC1 Differential Input Control
mic22hp_mute 7 RW 1h Mute MIC2 Volume Output to Headphone Mixer
0: On 1: Mute
mic22spk_mute 6 RW 1h Mute MIC2 Volume Output to Speaker Mixer
0: On 1: Mute
mic22MONO_mute 5 RW 1h Mute MIC2 Volume Output to MONO Mixer
0: On 1: Mute
mic2_diff_ctrl 4 RW 0h MIC2 Differential Input Control
Voice PCM Interface
ALC5610
Datasheet
8.9. Reg-12h: ADC Record Gain

Default: F58Bh
Table 19. Reg-12h: ADC Record Gain

adc2hp_l_mute 15 RW 1h Mute Left Gain Output to Headphone Mixer Control
0: On 1: Mute (-dB)
adc2hp_r_mute 14 RW 1h Mute Right Gain Output to Headphone Mixer Control
0: On 1: Mute (-dB)
adc2MONO_l_mute 13 RW 1h Mute Left Gain Output to MONO Mixer Control
0: On 1: Mute (-dB)
adc2MONO_r_mute 12 RW 1h Mute Right Gain Output to MONO Mixer Control
0: On 1: Mute (-dB)
adc_l_vol 11:7 RW 0Bh ADC Record Gain Left Channel (LRG[4:0]) in 1.5dB Steps
00h: -16.5dB attenuation 0Bh: 0dB gain
1Fh: 30dB gain
adc_l_dezero 6 RW 0h ADC_L Zero-Cross Detector Control
adc_r_dezero 5 RW 0h ADC_R Zero-Cross Detector Control
adc_r_vol 4:0 RW 0Bh ADC Record Gain Right Channel (RRG[4:0]) in 1.5dB
Steps
00h: -16.5dB attenuation 0Bh: 0dB gain
1Fh: 30dB gain
8.10. Reg-14h: ADC Record Mixer Control

Default: 7F7Fh
Table 20. Reg-14h: ADC Record Mixer Control

adcrec_l_mute 14:8 RW 7Fh Left Mixer Mute Control
0: On 1: Mute (-dB)
Bit 14: MIC1 Bit 13: MIC2
Bit 12: LINE_IN_L Bit 11: PHONE
Bit 10: Headphone Mixer Left Channel
Bit 9: Speaker mixer Bit 8: MONO Mixer
adcrec_r_mute 6:0 RW 7Fh Right Mixer Mute Control
0: On 1: Mute (-dB)
Bit 6: MIC1 Bit 5: MIC2
Bit 4: LINE_IN_R Bit 3: PHONE
Bit 2: Headphone Mixer Right Channel
Bit 1: Speaker mixer Bit 0: MONO Mixer
Voice PCM Interface
ALC5610
Datasheet
8.11. Reg-18h: Voice DAC Output Volume

Default: E800h
Table 21. Reg-18h: Voice DAC Output Volume

voice2hp_mute 15 RW 1h Mute VoDAC Output to Headphone Mixer Control
0: On 1: Mute (-dB)
voice2spk_mute 14 RW 1h Mute VoDAC Output to Speaker Mixer Control
0: On 1: Mute (-dB)
voice2MONO_mute 13 RW 1h Mute VoDAC Output to MONO Mixer Control
0: On 1: Mute (-dB)
voice_vol 12:8 RW 8h VoDAC Output Volume (VV[4:0]) in 1.5dB Steps
Note: For VV, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation
8.12. Reg-1Ch: Output Mixer Control

Default: 0000h
Table 22. Reg-1Ch: Output Mixer Control

spk_l_vol_in_sel 15:14 RW 0h SPKL Volume Input Select
00: VMID (No input) 01: HP Left Mixer
10: Speaker Mixer 11: MONO
spk_l_out_sel 13 RW 0h SPKL and SPKR Output Select
0: Class AB 1: Class D
spk_r_vol_in_sel 12:11 RW 0h SPKR Volume Input Select
00: VMID (No input) 01: HP Right Mixer
10: Speaker Mixer 11: MONO
hp_l_in_sel 9 RW 0h HPL Volume Input Select
0: VMID (No input) 1: HP Left Mixer
hp_r_in_sel 8 RW 0h HPR Volume Input Select
0: VMID (No input) 1: HP Right Mixer
MONO_in_sel 7:6 RW 0h MONO Volume Input Select
00: VMID (No input) 01: HP Left + Right Mixer
10: Speaker Mixer 11: MONO Mixer
clab_amp_source_sel 4 RW 0h In Class AB Mode
SPK_OUT_R Output Amplifier Source Select
0: SPKR Volume Output
1: SPKL Volume Output
Note: SPK_OUT_RN: SPKR Volume Negative Output
Voice PCM Interface
ALC5610
Datasheet
8.13. Reg-22h: Microphone Control

Default: 0000h
Table 23. Reg-22h: Microphone Control

mic1_boost_ctrl 11:10 RW 0h MIC1 Boost Control
00: Bypass 01: +20dB
10: +30dB 11: +40dB
mic2_boost_ctrl 9:8 RW 0h MIC2 Boost Control
00: Bypass 01: +20dB
10: +30dB 11: +40dB
Reserved 7:6 R 0h Reserved. Read as 0
mic1_bias_voltage_ctrl 5 RW 0h MICBIAS1 Output Voltage Control
0: 0.9 * AVDD 1: 0.75 * AVDD
mic2_bias_voltage_ctrl 4 RW 0h MICBIAS2 Output Voltage Control
0: 0.9 * AVDD 1: 0.75 * AVDD
mic_bias_threshold 1:0 RW 0h MICBIAS1/2 Short Current Detector Threshold
00: 600A 01: 1200A
1x: 1800A
8.14. Reg-26h: Power Down Control/Status

Default: EF00h
Table 24. Reg-26h: Power Down Control/Status

ac_pr7 15 RW 1h PR7
0: Normal
1: Power down Speaker Amplifier
ac_pr6 14 RW 1h PR6
0: Normal
1: Power down Headphone Out and MONO Out
ac_pr5 13 RW 1h PR5
0: Normal
1: Disable internal clock of AC97 (Without PLL)
ac_pr4 12 RW 0h PR4
0: Normal
1: Power down AC-Link
Note: Though this bit is read as 1, write 1 to power down
the AC-Link
Voice PCM Interface
ALC5610
Datasheet
ac_pr3 11 RW 1h PR3
0: Normal
1: Power down Mixer (Vref/Vrefout off)
ac_pr2 10 RW 1h PR2
0: Normal
1: Power down Mixer (Vref/Vrefout are still on)
ac_pr1 9 RW 1h PR1
0: Normal
1: Power down STEREO DAC
ac_pr0 8 RW 1h PR0
0: Normal
1: Power down STEREO ADC, and input MUX
vref_status 3 R 0h Vref Status
1: Vref is up to normal level
0: Not yet up to normal level
analog_mixer_status 2 R 0h Analog Mixer Status
1: Ready
0: Not yet ready
dac_status 1 R 0h DAC Status
1: Ready
0: Not yet ready (Inverse of PR1)
adc_status 0 R 0h ADC Status
1: Ready
0: Not yet ready (Inverse of PR0)
Table 25. Truth Table for Power Down Mode (PD=Power Down)
ADC DAC Mixer Vref ACLINK Int CLK HP-OUT MONO-OUT SPK-OUT
PR0=1 PD - - - - - - - -
PR1=1 - PD - - - - - - -
PR2=1 - - PD - - - PD - -
PR3=1 PD PD PD PD - - PD - -
PR4=1 PD PD - - PD - - - -
PR5=1 PD PD - - PD PD - - -
PR6=1 - - - - - - PD PD -
PR7=1 - - - - - - - - PD
Voice PCM Interface
ALC5610
Datasheet
8.15. Reg-2Ah: Tone Control

Default: 0000h
Table 26. Reg-2Ah: Tone Control

ac_src_en 0 RW 0h Enable Variable Rate Audio Control
0: Off
1: On
8.16. Reg-2Ch: AC97 Stereo DAC Rate/DPE Rate

Default: BB80h
Table 27. Reg-2Ch: AC97 Stereo DAC Rate/DPE Rate

dac_sample_rate 15:0 RW BB80h FOSR[15:0] Output Sampling Rate
The ALC5610 supports the following PC99/PC2001 design guide sampling rates.
Table 28. PC99/PC2001 Design Guide Sampling Rates

Sampling Rate FOSR[15:0]
8000 1F40h
11025 2B11h
12000 2EE0
16000 3E80h
22050 5622h
24000 5DC0
32000 7D00h
44100 AC44h
48000 BB80h
When ac_src_en=0 (VRA is disabled), any non-zero value in this register will be forced to BB80h.
Voice PCM Interface
ALC5610
Datasheet
8.17. Reg-32h: AC97 Stereo ADC Rate

Default: BB80h
Table 29. Reg-32h: AC97 Stereo ADC Rate

adc_sample_rate 15:0 RW BB80h IISR[15:0] Output Sampling Rate.
The ALC5610 supports the following PC99/PC2001 design guide sampling rates.
Table 30. PC99/PC2001 Design Guide Sampling Rates

Sampling Rate IISR[15:0]
8000 1F40h
11025 2B11h
12000 2EE0
16000 3E80h
22050 5622h
24000 5DC0
32000 7D00h
44100 AC44h
48000 BB80h
8.18. Reg-36h: Extend Serial Data Port Control

(VoDAC_I2S/PCM)
Default: 0000h
Table 31. Reg-36h: Extend Serial Data Port Control (VoDAC_I2S/PCM)
VoPCM_En 15 RW 0b Enable PCM Interface on GPIO1, 3, 4, 5
0: GPIO function 1: VoPCM interface
voice_port_sel 14 RW 0h Extend Serial Data Port Mode Selection
0: Master 1: Slave
voice_adc_enable 8 RW 0b Voice ADC Enable
0b: Disable (ADC_L=ADC_R=Stereo)
1b: Enable (ADC_L=Stereo, ADC_R=Voice)
voice_vbclk_polarity_ctrl 7 RW 0h Voice I2S VBCLK Polarity Control
0: Normal 1: Invert
Voice PCM Interface
ALC5610
Datasheet
voice_pcm_mode_sel 6 RW 0h PCM Mode Select
0: Mode A 1: Mode B
Non PCM Mode Control
0: Normal VSLRCK 1: Invert VSLRCK
voice_data_len_sel 3:2 RW 0h Data Length Selection
00: 16 bits 01: 20 bits
10: 24 bits 11: 32 bits
voice_data_format_sel 1:0 RW 0h Voice Data Format Selection
00: I2S format 01: Right justified
10: Left justified 11: PCM format
8.19. Reg-3Ah: Power Management Addition 1

Default: 0000h
Table 32. Reg-3Ah: Power Management Addition 1

depop_MONOoutb 15 RW 0h Depop of MONO Out
0: Enable (De-pop Enable)
1: Disable (De-pop Disable)
depop_hp_outb 14 RW 0h Depop of HP Out
0: Enable (De-pop Enable)
1: Disable (De-pop Disable)
pow_zcd 13 RW 0h All Zero-Cross Detect Power down
ip_en 12 RW 0h Pressure Measurement Source Current Enable
Pow_zcd_timo_out_en 11 RW 0h Zero Cross Time Out Enable
Reserved 10:6 RW 0h Reserved
pow_mic1_bias_det_ctrl 5 RW 0h MICBIAS1 Short Current Detector Control
pow_mic2_bias_det_ctrl 4 RW 0h MICBIAS2 Short Current Detector Control
pow_mic1_bias 3 RW 0h 0: Disable
1: Enable microphone1 bias
pow_mic2_bias 2 RW 0h 0: Disable
1: Enable microphone2 bias
pow_main_bias 1 RW 0h 0: Disable
1: Enable Main bias of the ALC5610
pow_dac_ref 0 RW 0h 0: Disable
1: Enable ALL DAC reference of the ALC5610
Voice PCM Interface
ALC5610
Datasheet
8.20. Reg-3Ch: Power Management Addition 2

Default: 0000h
Table 33. Reg-3Ch: Power Management Addition 2

pow_thermal 15 RW 0h Thermal Detect (Temp Sensor)
pow_clsab 14 RW 0h Class_AB Power (All)
pow_vref 13 RW 0h VREF of All Analog Circuits
pow_pll 12 RW 0h PLL
0: Disable 1: Enable PLL
pow_tp_adc 11 RW 0h Touch Panel and AUX_ADC
pow_voice_dac 10 RW 0h VoDAC Clock
Note: Disabled includes Voice_I2S interface.
pow_dac_l 9 RW 0h Left Stereo DAC Filter Clock
pow_dac_r 8 RW 0h Right Stereo DAC Filter Clock
pow_adc_l 7 RW 0h Left Stereo ADC Filter Clock and Input Gain
pow_adc_r 6 RW 0h Right Stereo ADC Filter Clock and Input Gain
pow_hp_l 5 RW 0h Left Headphone Mixer
pow_hp_r 4 RW 0h Right Headphone Mixer
pow_spk_mixer 3 RW 0h Speaker Mixer
pow_MONO_mixer 2 RW 0h MONO Mixer
pow_adc_rec_l_mixer 1 RW 0h Left ADC Record Mixer
pow_adc_rec_r_mixer 0 RW 0h Right ADC Record Mixer
Voice PCM Interface
ALC5610
Datasheet
8.21. Reg-3Eh: Power Management Addition 3

Default: 0000h
Table 34. Reg-3Eh: Power Management Addition 3

pow_MONO_out_vol 14 RW 0h MONO_OUT Volume Control (Amp)
pow_spk_outln 13 RW 0h SPK_OUTLN Output (Enable Class AB & Class D)
pow_spk_outrn 12 RW 0h SPK_OUTRN Output (Enable Class AB & Class D)
pow_hp_l_vol 11 RW 0h HP_OUT_L Volume Control (Amp)
pow_hp_r_vol 10 RW 0h HP_OUT_R Volume Control (Amp)
pow_spk_l 9 RW 0h SPK_OUT_L Output (Enable Class AB & Class D)
pow_spk_r 8 RW 0h SPK_OUT_R Output (Enable Class AB & Class D)
pow_li_l_vol 7 RW 0h LINE_IN Left Volume Control
pow_li_r_vol 6 RW 0h LINE_IN Right Volume Control
pow_phone_vol 5 RW 0h PHONE Volume Control
pow_phone_admixer 4 RW 0h PHONE AD Mixer
pow_mic1_vol 3 RW 0h MIC1 Volume Control
pow_mic2_vol 2 RW 0h MIC2 Volume Control
pow_mic1_admixer 1 RW 0h MIC1 AD Mixer and Boost
pow_mic2_admixer 0 RW 0h MIC2 AD Mixer and Boost
Voice PCM Interface
ALC5610
Datasheet
Figure 21. Power Control to MIC Input
8.22. Reg-40h: General Purpose Control Register 1

Default: 0428h
Table 35. Reg-40h: General Purpose Control Register 1

Name Bits Read/ Reset Description
Write State
sel_sysclk 15 RW 0h Clock Source MUX Control
0: MCLK 1: PLL Output
Extclk_dir 14 RW 0h EXTCLK Direction Control
0: Input 1: Output
hp_amp_ctrl 9:8 RW 0h Headphone Amplifier VMID Ratio Control (Output Gain Control)
00: 1 01: 1.25 1x: 1.5
spk_ampD_ctrl 7:6 RW 0h Speaker Class D Amplifier VMID Ratio Control (Output Gain Control)
00: 1.75 Vdd 01: 1.5 Vdd
10: 1.25 Vdd 11: 1.0 Vdd
spk_ampAB_ctrl 5:3 RW 5h Speaker Class AB Amplifier VMID Ratio Control (Output Gain Control)
000: 2.25 Vdd 001: 2.00 Vdd
010: 1.75 Vdd 011: 1.5 Vdd
100: 1.25 Vdd 101: 1 Vdd
Others: Not allowed
Voice PCM Interface
ALC5610
Datasheet
8.23. Reg-42h: General Purpose Control Register 2

Default: 0000h
Table 36. Reg-42h: General Purpose Control Register 2

voice_stereo_ 15 RW 0b Voice to Stereo Digital Path Enable
digitalpath_en 0b: Disable
1b: Enable
Reserved 14 RW 0h Reserved
se_btl_clsab 13 RW 0b Single End & BTL of SPK_Class AB Selection
0: Differential Mode
1: Single-End Mode
pll_pre_div 0 RW 0b PLL Pre-Divider
0b: 1
1b: 2
8.24. Reg-44h: PLL Control

Default: 0000h
Table 37. Reg-44h: PLL Control

pll_n_code 15:8 RW 00h N[7:0] Code for Analog PLL
00000000: Div 2
00000001: Div 3
..
11111111: Div 257
pll_m_bypass 7 RW 0h Bypass PLL M
0b: No bypass
1b: Bypass
pll_k_code 6:4 RW 0h K[2:0] Code for Analog PLL
000: Div 2
001: Div 3

111: Div 9
pll_m_code 3:0 RW 0h M[3:0] Code for Analog PLL
0000: Div 2
0001: Div 3

1111: Div 17
Note: The PLL transmit formula is FOUT = (MCLK * (N+2))/((M+2) * (K+2)) {Typical K=2}
Voice PCM Interface
ALC5610
Datasheet
8.24.1. AC-Link PLL Clock Setting Table (Unit: MHz)

Table 38. AC-Link PLL Clock Setting Table (Unit: MHz)
MCLK N M FVCO K FOUT
13 66 7 98.222 2 24.555
3.6864 78 1 98.304 2 24.576
2.048 94 0 98.304 2 24.576
4.096 70 1 98.304 2 24.576
Note: PLL will only be enabled after a warm reset of the AC-Link
8.25. Reg-4Ch: GPIO Pin Configuration

Default: 2E3Eh
Table 39. Reg-4Ch: GPIO Pin Configuration

Reserved 15:14 R 00b Reserved
pendown_conf 13 RW 1h Pen-down Detect Status Source Configuration
0: Bypass 1: Normal
Reserved 12 R 0b Reserved
over_temp_conf 11 RW 1h Over-temperature Status Source Configuration
0: Bypass 1: Normal
mic1_short_det_conf 10 RW 1h MICBIAS1 Short Current Status Source Configuration
0: Bypass 1: Normal
mic2_short_det_conf 9 RW 1h MICBIAS2 Short Current Status Source Configuration
0: Bypass 1: Normal
gpio5_conf 5 RW 1h GPIO5 Pin Configuration
0: Output 1: Input
0: Output 1: Input
0: Output 1: Input
0: Output 1: Input
0: Output 1: Input
Voice PCM Interface
ALC5610
Datasheet
8.26. Reg-4Eh: GPIO Pin Polarity

Default: 2E3Eh
Table 40. Reg-4Eh: GPIO Pin Polarity

pendown_polarity 13 RW 1h Pen-down Detect Polarity
0: Low Active 1: High Active
over_temp_polarity 11 RW 1h Over-temperature Polarity
mic1_short_det_polarity 10 RW 1h MICBIAS1 Short Current Detect Polarity
mic2_short_det_polarity 9 RW 1h MICBIAS2 Short Current Detect Polarity
gpio5_polarity 5 RW 1h GPIO Pin Polarity
gpio2_polarity 2 R/W 1h GPIO Pin Polarity
gpio1_polarity 1 R/W 1h GPIO Pin Polarity
8.27. Reg-50h: GPIO Pin Sticky

Default: 0000h
Table 41. Reg-50h: GPIO Pin Sticky

pendown_sticky_En 13 RW 0h Pen-down Detect Sticky Enable
0: Not sticky 1: Sticky
over_temp_sticky_En 11 RW 0h Over-temperature Sticky Enable
mic1_short_det_sticky_En 10 RW 0h MICBIAS1 Short Current Detect Sticky Enable
Voice PCM Interface
ALC5610
Datasheet
mic2_short_det_sticky_En 9 RW 0h MICBIAS2 Short Current Detect Sticky Enable
gpio5_sticky_En 5 RW 0h GPIO5 Pin Sticky Enable
8.28. Reg-52h: GPIO Pin Wake-Up

Default: 0000h
Table 42. Reg-52h: GPIO Pin Wake-Up

pendown_wakeup_en 13 RW 0h Pen-Down Detect Wake-Up Enable
0: No wake-up 1: Wake Up
over_temp_wakeup_en 11 RW 0h Over-Temperature Wake-Up Enable
mic1_short_det_ 10 RW 0h MICBIAS1 Short Current Detect Wake-Up Enable
wakeup_en 0: No wake-up 1: Wake Up
mic2_short_det_ 9 RW 0h MICBIAS2 Short Current Detect Wake-Up Enable
wakeup_en 0: No wake-up 1: Wake Up
gpio5_wakeup_en 5 RW 0h GPIO5 Pin Wake-Up Enable
Voice PCM Interface
ALC5610
Datasheet
8.29. Reg-54h: GPIO Pin Status

Default: 003Ah
Table 43. Reg-54h: GPIO Pin Status

pendown_status 13 R 0h Pen-down Detect Status
Read: Return status
Write: Writing 0 clears the sticky bit
over_temp_status 11 R 0h Over-temperature Status
Read: Return status
mic1_short_det_status 10 R 0h MICBIAS1 Short Current Detect Status
Read: Return status
mic2_short_det_status 9 R 0h MICBIAS2 Short Current Detect Status
Read: Return status
gpio5_status 5 R 1h GPIO5 Pin Status
Read: Return status of each GPIO pin
8.30. Reg-56h: Pin Sharing

Default: 0000h
Table 44. Reg-56h: Pin Sharing

gpio2_pin_sharing 2 RW 0h GPIO2 Pin Sharing
0: IRQ_Out 1: GPIO enable
Voice PCM Interface
ALC5610
Datasheet
Figure 22. GPIO and IRQ Logic
Table 45. GPIO and IRQ Logic

GPIO Bit Reg54[15:1] SLOT 12 Bit Source Description
1 5 GPIO Pin GPIO1 Input Status
2 6 GPIO Pin GPIO2
3 7 GPIO Pin GPIO3
4 8 GPIO Pin GPIO4
5 9 GPIO Pin GPIO5
6 10 - Unused
7 11 - Unused
8 12 - Unused
9 13 VGPIO MICBIAS2 Short Current Detect
10 14 VGPIO MICBIAS1 Short Current Detect
11 15 VGPIO Over-Temperature
12 16 - Unused
13 17 VGPIO Pen-Down Detect
14 18 - Unused
15 19 - Unused
Voice PCM Interface
ALC5610
Datasheet
8.31. Reg-58h: Over-Temp/Current Status

Default: 0CFFh
Table 46. Reg-58h: Over-Temp/Current Status

ovt_hp_status 11 R 1h Headphone Amp Over-Temperature
0: Normal
1: Over-temperature
ovt_MONO_status 10 R 1h MONO Amp Over-Temperature
0: Normal
1: Over-temperature
ovc_micbias1_status 9 R 0h MICBIAS1 Over-Current
0: Normal
1: Over current
ovc_micbias2_status 8 R 0h MICBIAS2 Over-Current
0: Normal
1: Over-current
rp_depop_status 7 R 1h RP Channel Depop Status
0: Depop ready
1: Depop finished
rn_depop_status 6 R 1h RN Channel Depop Status
0: Depop ready
1: Depop finished
lp_depop_status 5 R 1h LP Channel Depop Status
0: Depop ready
1: Depop finished
ln_depop_status 4 R 1h LN Channel Depop Status
0: Depop ready
1: Depop finished
ovt_rp_status 3 R 1h RP Channel Temperature Sensor Status
0: Normal
1: Over-temperature
ovt_rn_status 2 R 1h RN Channel Temperature Sensor Status
0: Normal
1: Over-temperature
ovt_lp_status 1 R 1h LP Channel Temperature Sensor Status
0: Normal
1: Over-temperature
ovt_ln_status 0 R 1h LN Channel Temperature Sensor Status
0: Normal
1: Over-temperature
Voice PCM Interface
ALC5610
Datasheet
8.32. Reg-5Ch: GPIO_Output Pin Control

Default: 0000h
Table 47. Reg-5Ch: GPIO_Output Pin Control

gpio5_out_status 5 RW 0h GPIO5 Output Pin Control
0b: Drive Low
1b: Drive High
0b: Drive Low
1b: Drive High
0b: Drive Low
1b: Drive High
0b: Drive Low
1b: Drive High
0b: Drive Low
1b: Drive High
8.33. Reg-5Eh: MISC Control

Default: 0000h
Table 48. Reg-5Eh: MISC Control

en_vref_fast 15 RW 0b Enable Fast Vref
0: Enable fast Vref 1: Disable fast Vref
Note: To improve PSRR, en_vref_fast should be
disabled before playback/record.
clsab_amp_sel 14 RW 0b Class AB Output Amplifier Select
0: Strong Amp 1: Weak Amp
Note: Strong Amp, SPKVDD: 3.0V~5V and Set
index44[8:6]=100b
Weak Amp, SPKVDD: 2.3V~5V and
Setindex44[8:6]=000b
AVC_target_sel 13:12 RW 0b AVC Target Select
00: Reserved (No AVC) 01: R Channel
10: L Channel 11: Both channel
thermal_shutdown_en 11 RW 0b Thermal Shutdown Enable
Voice PCM Interface
ALC5610
Datasheet
reset_pendown_sel 10 RW 0b Reset/Pen-Down Selection
0: Reset Input 1: Pen-down Output
Note: Output Reg78[15] status as pen-down signal
when Reset_Pendown_sel=1
Sequence:
1. Set the GPIO of the controller as output and set the
ALC5610 as Reset_Input
2. After Reset, Set the GPIO of the controller as Input
and set the ALC5610 as Pendown_Output
3. Enable the GPIO of the controller to receive INT
4. After the controller Received INT, the controller
disables INT and starts to check AUXADC
5. Pen-up will be reported by Reg78[15]
main_dac_l_mute 6 RW 0h Mute Main DAC Left Input
0: On 1: Mute (-dB)
main_dac_r_mute 5 RW 0h Mute Main DAC Right Input
0: On 1: Mute (-dB)
voice_dac_mute 4 RW 0h Mute Voice DAC Input
0: On 1: Mute (-dB)
gpio_wakeup_ctrl 1 RW 0h GPIO wakeup Control
irqout_inv_ctrl 0 RW 0h IRQOUT Inverter Control
0: Normal 1: Invert
The Jack-insert-detect pull-up resistor is implemented via an external circuit (see Figure 23).
Figure 23. Jack-Insert-Detect Pull-Up Resistor Implemented via an External Circuit
Voice PCM Interface
ALC5610
Datasheet
8.34. Reg-64h: VoDAC_PCM Clock Control_1

Default: 2130h
Table 49. Reg-64h: VoDAC_PCM Clock Control_1

voice_mclk_sel 15 RW 0h Voice Master-Clock Select
0b: MCLK input
1b: PLL output
voice_sysclk_sel 14 RW 0h Voice System-Clock Select
0b: MCLK
1b: EXTCLK
I2s_wclk voice_master_sel 13 RW 1h I2S Word-Clock Voice Master Select
0b: 32
1b: 64
extclk_out_sel 10:8 RW 1h External Clock-Out Select
000b: 1
001b: 2
010b: 4
011b: 8
100b: 16
Others: Reserved
I2s_sclk_voice_master_sel_1 7:4 RW 3h I2S Bit-Clock Voice Master Select 1
0000b: 1
0001b: 2
0010b: 3

1101b: 14
1110b: 15
1111b: 16
I2s_sclk_voice_master_sel_2 2:0 RW 0h I2S Bit-Clock Voice Master Select 2
000b: 2
001b: 4
010b: 8
011b: 16
100b: 32
Others: Reserved
Note: The driver must determine the Voice AD/DA filter clock, and select the filter by setting Voice_64osr (see Table 50).
Voice PCM Interface
ALC5610
Datasheet
8.35. Reg-66h: VoDAC_PCM Clock Control_2

Default: 0010h
Table 50. Reg-66h: VoDAC_PCM Clock Control_2

sel_clk_filter_slave 15 RW 0h Select Voice Clock Filter Slave
0b: 1
1b: 2
sel_clk_filter 14 RW 0h Select Voice Clock Filter Source
0b: From MCLK/EXTCLK
1b: From VBCLK
voice_64osr 13 RW 0h Voice DA/AD Filter Select
0b: 128x
1b: 64x
clk_filter_master_sel_1 7:4 RW 1h Clock Filter Master Select 1
000b: 1
001b: 2
010b: 3

1101b: 14
1110b: 15
1111b: 16
clk_filter_master_sel_2 2:0 RW 0h Clock Filter Master Select 2
000b: 2
001b: 4
010b: 8
011b: 16
100b: 32
Others: Reserved
Voice PCM Interface
ALC5610
Datasheet
8.36. Reg-68h: Pseudo Stereo and Spatial Effect Block Control

Default: 0053h
Table 51. Reg-68h: Pseudo Stereo and Spatial Effect Block Control
spatial_ctrl_enable 15 RW 0b Spatial Enable
0b: Disable (Clear internal state)
1b: Enable
apf_en 14 RW 0h Enable All Pass Filter APF(z) (EN-APF)
0: Disable (Bypass) and reset.
1: Enable all pass filters. The coefficient a1 is loaded from
apf_parm_a1[7:0]
pseudo_stereo_en 13 RW 0h Enable Pseudo Stereo Block (EN-PSB)
0: Disabled
1: Enabled
en_3d 12 RW 0h Enable Stereo Expension Block (EN-SEB)
0: Disable
1: Enabled. Load 3D Ratio from ratio_parm_3d and 3D
Gain from gain_parm_3d
Reserved 11:8 - 0h Reserved
gain_parm_3d 7:6 RW 1h 3D Gain Parameter (SEGn)
00: Gain=1.0
01: Gain=1.5
10: Gain=2.0
11: Reserved
ratio_parm_3d 5:4 RW 1h 3D Ratio Parameter (DPn)
00: Ratio=0.0
01: Ratio=0.66
10: Ratio=1.0
11: Reserved
Reserved 3:2 - 0h Reserved
apf_parm_a1 1:0 RW 3h All Pass Filter Parameter
00: Disable
01: Enable for 32kHz sample rate or lower
10: Enable for 44.1kHz sample rate
11: Enable for 48kHz sample rate
Note: Writes to SEGn and DPn will be ignored when the Spatial effect control bit is enabled. This means individual
Spatial coefficients cannot be modified when Spatial is enabled.
Voice PCM Interface
ALC5610
Datasheet
8.37. Reg-6Ah: Index Address

Default: 0000h
Table 52. Reg-6Ah: Index Address

index_addr 6:0 RW 0h Index Address
8.38. Reg-6Ch: Index Data

Default: 0000h
Table 53. Reg-6Ch: Index Data

index_data 15:0 RW 0h Index Data
8.39. Reg-6Eh: EQ Status

Default: 0000h
Table 54. Reg-6Eh: EQ Status

eq_hpf_status 4 R 0h EQ High-Pass Filter (HPF) Status
0: Normal 1: Overflow.
This bit is set if overflow has occurred. Write 1 to clear.
eq_bpf3_status 3 R 0h EQ Band-3 (BP3) Status
eq_lpf_status 0 R 0h EQ Low-Pass Filter (LPF) Status
Voice PCM Interface
ALC5610
Datasheet
8.40. Index-00h: EQ Band-0 Coefficient (LP0: a1)

Default: 0000h
Table 55. Index-00h: EQ Band-0 Coefficient (LP0: a1)

Bit Type Function
15:0 RW 2s complement in 3.13 formats (The range is from 4~3.99, the a1 should be in -2 ~ 1.99)
Note: For low pass filter for Bass control LP0 has filter coefficient a1 and gain Ho must be set (see Table 56).
8.41. Index-01h: EQ Band-0 Gain (LP0: Ho)

Default: 0000h
Table 56. Index-01h: EQ Band-0 Gain (LP0: Ho)

Bit Type Function
15:0 RW 2s complement in 3.13 format (The range is from 4~3.99, the Ho should be in -4 ~ 3.99)
8.42. Index-02h: EQ Band-1 Coefficient (BP1: a1)

Default: 0000h
Table 57. Index-02h: EQ Band-1 Coefficient (BP1: a1)

Bit Type Function
15:0 RW 2s complement in 3.13 format (The range is from 4~3.99, the a1 should be in -2 ~ 1.99)

Default: 0000h

Bit Type Function
Voice PCM Interface
ALC5610
Datasheet
8.44. Index-04h: EQ Band-1 Gain (BP1: Ho)

Default: 0000h
Table 59. Index-04h: EQ Band-1 Gain (BP1: Ho)

Bit Type Function

Default: 0000h

Bit Type Function

Default: 0000h

Bit Type Function
8.47. Index-07h: EQ Band-2 Gain (BP2: Ho)

Default: 0000h
Table 62. Index-07h: EQ Band-2 Gain (BP2: Ho)

Bit Type Function
Voice PCM Interface
ALC5610
Datasheet

Default: 0000h

Bit Type Function

Default: 0000h

Bit Type Function
8.50. Index-0Ah: EQ Band-3 Gain (BP3: Ho)

Default: 0000h
Table 65. Index-0Ah: EQ Band-3 Gain (BP3: Ho)

Bit Type Function
8.51. Index-0Bh: EQ Band-4 Coefficient (HPF: a1)

Default: 0000h
Table 66. Index-0Bh: EQ Band-4 Coefficient (HPF: a1)

Bit Type Function
8.52. Index-0Ch: EQ Band-4 Gain (HPF: Ho)

Default: 0000h
Table 67. Index-0Ch: EQ Band-4 Gain (HPF: Ho)

Bit Type Function
Voice PCM Interface
ALC5610
Datasheet
8.53. Index-10h: EQ Control and Status Register

Default: 0000h
Table 68. Index-10h: EQ Control and Status Register

Bit Type Function
15 RW EQ Block Control
0b: Disable 1b: Enable
14:5 - Reserved
4 RW EQ High-Pass Filter (HPF) Control
0: Disabled (bypass) and reset 1: Enabled
3 RW EQ Band-3 (BP3) Control
0: Disabled and reset 1: Enabled
0 RW EQ Low-Pass Filter (LPF) Control
Note: Individual EQ coefficients cannot be modified when EQ is enabled.
8.54. Index-11h: EQ Input Volume Control

Default: 0000h
Table 69. Index-11h: EQ Input Volume Control

Bit Type Function
15:2 - Reserved
1:0 RW 7-Bit Volume Unsigned Ratio EQIn-VOL-LR
00b: 0dB 01b: -6dB 10b: -12dB 11b: -18dB
8.55. Index-12h: EQ Output Volume Control

Default: 0001h
Table 70. Index-12h: EQ Output Volume Control

Bit Type Function
15:3 - Reserved
2:0 RW 7-Bit Volume Unsigned Ratio EQOut-VOL-LR
000b: -3dB 001b: 0dB 010b: 3dB 011b: 6dB
100b: 9dB 101b: 12dB 110b: 15dB 111b: 18dB
Voice PCM Interface
ALC5610
Datasheet
8.56. Index-20h: Auto Volume Control Register 0

Default: 0050h
Table 71. Index-20h: Auto Volume Control Register 0

Bit Type Function
15 RW Select the Controlled Gain Block for AVC (Default: 00b)
0: Disable AVC
1: Enable AVC to control ADC gain
14:8 - Reserved
7:3 RW Monitor Window Control (Unit: 2^(n+1) samples) (Default: 01010b)
00000b: 2^(1) sample
00001b: 2^(2) samples
00010b: 2^(3) samples

10000b: 2^(17) samples
Others: Reserved.
Maximum n=16
Note: The Monitor Window can only be changed after soft-reset when AVC is enabled
2:1 - Reserved
0 RW AVC Reference Channel Selection (Default: 0b)
0: Left Channel
1: Right Channel

Default: 2710h

Bit Type Function
15 - Reserved
14:0 RW The Maximum PCM absolute level after AVC, Thmax (=0 ~ 2^15-1)

Default: 0BB8h

Bit Type Function
15 - Reserved
14:0 RW The Minimum PCM absolute level after AVC, Thmin (=0 ~ 2^15-1)
Voice PCM Interface
ALC5610
Datasheet

Default: 01F4h

Bit Type Function
15 - Reserved
14:0 RW The Non-active PCM absolute level AVC will keep analog unit gain, Thnonact (=0 ~ 2^15-1)
Note: Initial Index23=0001h

Default: 0190h

Bit Type Function
15:0 RW The CNTMAXTH1 to control the sensitivity to increase Gain (Unit:2^1)
This value should be less than CNTMAXTH2 (Max:2^17)

Default: 0200h

Bit Type Function
15:0 RW The CNTMAXTH2 to control the sensitivity to decrease Gain (Unit:2^1)
This value should be less than Monitor Window. (Optimized: 1/2 Monitor Window)
(Max:2^17)
Note: CNTMAXTH1 < CNTMAXTH2
8.62. Index-39h: Digital Internal Register

Default: 9000h
Table 77. Index-39h: Digital Internal Register

Bit Type Function
15 RW Pad Drive Capability
0b: Weak drive
1b: Strong drive
14:0 RW Reserved
Voice PCM Interface
ALC5610
Datasheet
8.63. Index-4Ah: Class D Temperature Sensor

Default: 4444h
Table 78. Index-4Ah: Class D Temperature Sensor

Bit Type Function
15 RW Reserved
14:12 RW RP Channel Temp. Sensor Threshold Setting
001: 35C 011: 65C
101: 95C 111: 125C
11 RW Reserved
10:8 RW RN Channel Temp. Sensor Threshold Setting
001: 35C 011: 65C
101: 95C 111: 125C
7 RW Reserved
6:4 RW LP Channel Temp. Sensor Threshold Setting
001: 35C 011: 65C
101: 95C 111: 125C
3 RW Reserved
2:0 RW LN Channel Temp. Sensor Threshold Setting
001: 35C 011: 65C
101: 95C 111: 125C
Note: Tolerance: 15C
8.64. Index-54h: AD_DA_Mixer_Internal Register

Default: 8184h
Table 79. Index-54h: AD_DA_Mixer_Internal Register

Bit Type Function
15 RW Reserved
14:13 RW DAC Reference Source
01: Internal DAC reference (AVDD1 & DAC reference cannot be bonded together)
11: External DAC reference (AVDD/AGND as DAC reference)
Others: Forbidden
12:3 RW Reserved
2:0 RW Temp. Sensor for Threshold Setting
001: 35C 011: 65C
101: 95C 111: 125C
Note: Tolerance: 15C
Note: To reduce DAC power consumption, we suggest that Index54=E184h be initialized.
Voice PCM Interface
ALC5610
Datasheet
8.65. Reg-74h: Touch Panel Control Byte 1

Default: 008Ch
Table 80. Reg-74h: Touch Panel Control Byte 1

pow_tp_ctrl 15:14 RW 0h Touch Panel Power Control
00: All OFF
01: AUX_ADC is OFF, pen-down is ON, and AUX_ADC
will be turned ON once pen-down is detected.
10: AUX_ADC is OFF, pen-down is ON, but AUX_ADC
will not be turned ON even if pen-down is detected.
11: AUX_ADC ON
pressure_source_ 13:10 RW 0h Pressure Measurement Source Current
current 0000b: OFF
0001b: 25A
0010b: 50A

1111b: 375A
Reserved 9 RW 0h Reserved
tp_adc_delay_sel 8:7 RW 1h Touch Panel ADC Measure Delay After Switch Matrix
Setting Change (1 Frame =20.8s)
00: 4 frame
01: 8 frame (Default)
10: 16 frame
11: 32 frame
slot_readback_En 6 RW 0b Slot Readback Enable
(Control for continuous and polling mode)
0b: Disable
1b: Enable
tp_slot_sel 5 RW 0h AC97 Slot Select
0: Slot 5
1: Slot 6
tp_clk_div 4:2 RW 3h AUX ADC Clock Divider
000~010: Reserved
011: 64 (Default)
100: 80
101: 96
110: 112
111: 128
conversion_rate_sel 1:0 RW 0h Conversion Rate Select for No Delay Setting
00: 93.75Hz (512 frames)
01: 124.67Hz (384 frames)
10: 187.5Hz (256 frames)
11: 374Hz (128 frames)
Voice PCM Interface
ALC5610
Datasheet
8.66. Reg-76h: Touch Panel Control Byte 2

Default: 3F00h
Table 81. Reg-76h: Touch Panel Control Byte 2

polling_trig 15 RW 0h Writing 1 initiates a measurement in polling mode. This
bit will self-clear when measured data is received
tp_adc_mode_sel 14 RW 0h Touch Panel ADC Data Mode Select During Position
Measurement
0: Polling mode
1: Continuous mode
pd_pullup_resistor_sel 13:8 RW 3Fh Programmable Internal Pull-up Resistor For Pen-down
Detection
000000: 1K Ohm
000001: 2K Ohm
000010: 3K Ohm

111111: 64Kohm
AUX_measure_en 7 RW 0h AUX Measurement
0: Disable
1: Enable
pressure_measure_en 3 RW 0h Pressure Measurement
0: Disable
1: Enable
y_measure_en 2 RW 0h Y Co-Ordinate Measurement
0: Disable
1: Enable
x_measure_en 1 RW 0h X Co-Ordinate Measurement
0: Disable
1: Enable
AUX_measure_sel 0 RW 0h AUX3/AUX4 Measure Selection
0:AUX4
1:AUX3
Voice PCM Interface
ALC5610
Datasheet
8.67. Reg-78h: Touch Panel Indication

Default: 0000h
Table 82. Reg-78h: Touch Panel Indication

pen_status 15 R 0h Indicates Pen Status after AUX_ADC Measured
0: Pen-up
1: Pen-down
pipe_adc_source 14:12 R 0h AUX ADC Source
000: No Data (AUX_ADC Busy)
001: X co-ordinate measurement
010: Y co-ordinate measurement
011: Pressure measurement
100: Reserved
101: Reserved
110: Reserved
111: AUX
pipe_adc_rpt 11:0 R 0h AUX ADC Data Report
8.68. Reg-7Ch: VENDOR ID 1

Default: 10ECh
Table 83. Reg-7Ch: VENDOR ID 1

vender_id1 15:0 R 10ECh Vendor ID=10EC
8.69. Reg-7Eh: VENDOR ID 2

Default: 1003h
Table 84. Reg-7Eh: VENDOR ID 2

vender_id 15:8 R 10h Device ID=10
device_id2 7:0 R 03h Version ID=03
Voice PCM Interface
ALC5610
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 85. Absolute Maximum Ratings
Parameter Symbol Min Typ Max Units
Power Supplies
Digital IO Buffer DVDD1 -0.3 - 3.63 V
Digital Core DVDD2 -0.3 - 3.63 V
Analog AVDD -0.3 - 3.63 V
Touch Panel TPVDD -0.3 - 3.63 V
Headphone HPVDD -0.3 - 3.63 V
Speaker SPKVDD -0.3 - 71 V
o
Operating Ambient Temperature Ta -25 - +85 C
o
Storage Temperature Ts -55 - +125 C
Note 1: SPKVDD=5V with 3.5% duty cycle Power bouncing up to SPKVDD=8V is acceptable.
9.1.2. Recommended Operating Conditions

Table 86. Recommended Operating Conditions
Digital IO Buffer DVDD1 1.8 3.3 3.6 V
Digital Core DVDD2 1.8 3.3 3.6 V
Analog AVDD 2.3 3.3 3.6 V
Touch Panel TPVDD 2.3 3.3 3.6 V
Headphone HPVDD 2.3 3.3 3.6 V
Speaker SPKVDD1 2.3 3.3 5 V
Note 1: A 10F Capacitor must be connected from SPKVDD to AGND, and should be placed as close as possible to the
SPKVDD pin of the ALC5610.
9.1.3. Static Characteristics

Table 87. Static Characteristics
Low Level Input Voltage VIL - - 0.35DVDD V
High Level Input Voltage VIH 0.65DVDD - - V
High Level Output Voltage VOH 0.9DVDD - - V
Low Level Output Voltage VOL - - 0.1DVDD V
Input Leakage Current - -1 - 1 A
Output Leakage Current (Hi-Z) - -1 - 1 A
Output Buffer High Drive Current - - 22 - mA
Output Buffer Low Drive Current - - 10 - mA
VMID Internal Serial Resistor - 25 50 75 K
VMID Internal Serial Resistor Ratio - 95 100 105 %
Note: DVDD=3.3V, Tambient=25C, with 50pF external load.
Voice PCM Interface
ALC5610
Datasheet
9.2. Analog Performance Characteristics

Table 88. Analog Performance Characteristics
Parameter Min Typ Max Units
Full Scale Input Voltage
Line Inputs - 1.0 - Vrms
MIC Inputs (Non-Boost) - 1.0 - Vrms
MIC Inputs (Boost 20dB) - 0.1 - Vrms
ADC - 0.7 - Vrms
Full Scale Output Voltage
MONO Outputs - 1.0 - Vrms
Headphone Amplifiers Outputs - 1.0 - Vrms
Speaker Amplifiers Outputs - 1.3 - Vrms
S/N Ratio
(A-weighted, HPL/R or MONO with 10K/50pF load)
STEREO DAC - 90 - dB
STEREO ADC - 85 - dB
Voice DAC - 70 - dB
Total Harmonic Distortion + Noise
(A-weighted, HPL/R or MONO with 10K/50pF load)
STEREO DAC - -85 - dB
STEREO ADC - -80 - dB
Voice DAC - -60 - dB
MIC Boost Amplifier
Gain=20dB 18 20 22 dB
Gain=30dB - 30 - dB
Gain=40dB - 40 - dB
Input Impedance (Gain=0dB, ADC Mixer=On/Off)
PHONEN (Differential Mode) - 16 - K
MIC1N, MIC2N (Differential Mode) - 16 - K
MIC1P, MIC2P - 16 - K
PHONEP - 16 - K
Input Impedance (Gain=0dB, ADC Mixer=On)
LINE_IN 12.8 16 19.2 K
Input Impedance (Gain=0dB, ADC Mixer=Off)
LINE_IN 25.6 32 38.4 K
Output Impedance
MONO_OUT - 2 -
HP_OUT - 2 -
SPK_OUT (Class AB) - 1 -
SPK_OUT (Class D) - 0.3 0.4
MONO_OUT Amplifier Output Power (32 Load)
Single End Mode 25 - - mW
BTL Mode 75 - - mW
Voice PCM Interface
ALC5610
Datasheet
MONO_OUT Amplifier Quiescent Current (32 Load)/CH - 700 - A
MONO_OUT Amplifier Efficiency (fIN=1kHz, 32 Load)
Single End Mode (Output Power=25mW) 50 - - %
BTL Mode (Output Power=75mW) 50 - - %
MONO_OUT Amplifier THD+N
Single End Mode (10K Load)
Output Power=0.1mW - 0.01 - %
BTL Mode (10K Load)
Output Power=0.1mW - 0.01 - %
MONO_OUT Amplifier PSRR - 50 - dB
Headphone Amplifier Output Power (32 Load) - - 31.25 mW
Headphone Amplifier Quiescent Current (32 Load) - 700 - A
Headphone Amplifier Efficiency 50 - - %
(fIN=1kHz, 32 Load, Output Power=25mW)
Headphone Amplifier THD+N (32 Load)
Output Power=20mW - 70 - dB
Headphone Amplifier PSRR - 50 - dB
BTL Speaker Amplifier Output Power - 1 - W
(SPKVDD=5V with 8 Load)
BTL Speaker Amplifier Quiescent Current
Class AB_Strong (8 Load) - - 11 mA
Class D - - 4 mA
BTL Speaker Amplifier Efficiency
(fIN=1kHz, 8 Load, Output Power=700 mW)
Class AB 50 - - %
Class D - 82 - %
BTL Speaker Amplifier THD + N (8 Load)
Class AB_Strong (8 Load)
Class D
BTL Speaker Amplifier THD + N
Class AB_Weak (10K/50pF Load) - -85 - dB
BTL Speaker Amplifier SNR
Class AB_Weak (10K/50pF Load) - -90 - dB
BTL Speaker Amplifier PSRR - 50 - dB
Power Supply Current
IDDA (Analog Block) - - 15 mA
IDDD (Digital Block) - - 20 mA
Voice PCM Interface
ALC5610
Datasheet
Power Down Current
IDDA (Analog Block) - - 10 A
IDDD (Digital Block) - - 1 A
MICBIAS1 Output Voltage
0.75*Avdd Setting - 2.475 - V
MICBIAS1 and MICBIAS2 Drive Current - 16 - mA
MICBIAS2 Output Voltage
Vref Pull Up Resistor - 50 - K
Note: Standard test conditions
Tambient = 25C, DVDD = AVDD = HPVDD=3.3V, SPKVDD = 4.2V
1kHz input sine wave; PCM Sampling frequency = 48kHz; 0dB = 1Vrms, Test bench Characterization BW: 10Hz~22kHz,
0dB attenuation; EQ and 3D disabled
Voice PCM Interface
ALC5610
Datasheet
9.3. Signal Timing

9.3.1. Cold Reset
Figure 24. Cold Reset Timing
Table 89. Cold Reset Timing Parameters

RESET# Active Low Pulse Width Trst_low 1.0 - - s
RESET# Inactive to SDATA-IN or BITCLK Active Delay Ttri2actv - - 25 ns
RESET# Inactive to BIT_CLK Startup Delay Trst2clk 162.8 - - ns
9.3.2. Warm Reset

Tsync_high Tsync2clk
SYNC
BIT_CLK
Figure 25. Warm Reset Timing
Table 90. Warm Reset Timing Parameters

Parameter Symbol Min Typ (Design) Max Units
SYNC Active High Pulse Width Tsync_high 1.0 1.3 (16 BCLK) - s
SYNC Inactive to BIT_CLK Startup Delay Tsync2clk 0.1628 - 400 s
Voice PCM Interface
ALC5610
Datasheet
9.3.3. AC-Link Clock Parameters

Table 91. AC-Link Clock Parameters
BIT_CLK Frequency - - 12.288 - MHz
BIT_CLK Period Tclk_period - 81.4 - ns
BIT_CLK Output Jitter - - - 750 ps
BIT_CLK High Pulse Width (Note 2) Tclk_high 36 40.7 45 ns
BIT_CLK Low Pulse Width (Note 2) Tclk_low 36 40.7 45 ns
SYNC Frequency - - 48.0 - kHz
SYNC Period Tsync_period - 20.8 - s
SYNC High Pulse Width Tsync_high - 1.3 - s
SYNC Low Pulse Width Tsync_low - 19.5 - s
Note: Worse case duty cycle restricted to 45/55.
9.3.4. AC-Link Data Output and Input Timing
Figure 26. Data Output and Input Timing
Table 92. AC-Link Data Timing Parameters

Output Valid Delay from Rising Edge of BIT_CLK tco - - 15 ns
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Note 2: 50pF external load
Input Setup to Falling Edge of BIT_CLK tsetup 10 - - ns
Input Hold from Falling Edge of BIT_CLK thold 10 - - ns
Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
BIT_CLK Combined Rise or Fall Plus Flight Time - - - 7 ns
SDATA Combined Rise or Fall Plus Flight Time - - - 7 ns
Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
Voice PCM Interface
ALC5610
Datasheet
9.3.5. AC-Link Signal Rise and Fall Timing
Figure 27. Signal Rise and Fall Timing
Table 93. AC-Link Signal Rise and Fall Timing Parameters

BIT_CLK Rise Time Triseclk - - 6 ns
BIT_CLK Fall Time Tfallclk - - 6 ns
SYNC Rise Time Trisesync - - 6 ns
SYNC Fall Time Tfallsync - - 6 ns
SDATA_IN Rise Time Trisedin - - 6 ns
SDATA_IN Fall Time Tfalldin - - 6 ns
SDATA_OUT Rise Time Trisedout - - 6 ns
SDATA_OUT Fall Time Tfalldout - - 6 ns
Note 1: 55pF external load (50 pF in AC97 rev2.1), only for PC system verify case
Note 2: Rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: Fall is from 90% to 10% of Vdd (Voh to Vol)
Voice PCM Interface
ALC5610
Datasheet
9.3.6. AC-Link Low Power Mode Timing
Figure 28. AC-Link Low Power Mode Timing
Table 94. AC-Link Low Power Mode Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN Low Ts2_pdown - - 1.0 s
9.3.7. AC-Link IO Pin Capacitance and Loading

Table 95. AC-Link IO Pin Capacitance Parameters
Output Pin For PC For PDA Units
RESET#, SYNC & SDATA_OUT 47.5 25 pF
BIT_CLK 47.5 25 pF
SDATA_IN 47.5 25 pF
Voice PCM Interface
ALC5610
Datasheet
10. Application Circuits

AVDD AVDD SPKVDD AVDD DVDD DVDD
TPVDD1 HPVDD1 SPKVDD1 AVDD1 DVDD2 DVDD1
AVDD
C48
10u
C3
0.1u
C8
0.1u
C9
10u
C14
0.1u
C15
10u
C1
10u
C2
0.1u
C6
10u
C7
0.1u
C12
10u
C13
0.1u
BTL Output
DVDD AVDD
J1
DVDD AVDD FB1
DVDD
AC97_MONO_OUT MONO_DIFF_OUT
FB3 SPKVDD BEAD
HPVDD1
TPVDD1
*NOTE: For SPKVDD by pass cap , C15>= 10u is necessary FB2
SPKVDD1
DVDD1
DVDD2
AVDD1
BEAD C11
AC97_MONO_OUTN MONON_DIFF_OUT
+C10 BEAD
0.1u MONO_CON
10u
D1
25
13
43
38
1
9
U1 C4 C5
SPKVDD
1 4 U2-1
AVDD1
DVDD1
DVDD2
TPVDD
HPVDD
100P 100P PESD5V0S2BT
2 3 R1 0 2 31
MCLK MONO_OUT AC97_MONO_OUT
OSC 24.576MHz 3 32 FB4 SPK_OUT_L
AC97_EXTCLK EXTCLK MONO_OUTN AC97_MONO_OUTN J2
AC97_SPK_OUT_LN BEAD
R2 0 BITCLK 6 39
AC97_BITCLK BIT_CLK HP_OUT_L AC97_HP_OUT_L FB5
8 41
AC97_SDIN SDATA_IN HP_OUT_R AC97_HP_OUT_R AC97_SPK_OUT_L BEAD SPKL_CON
5
AC97_SDOUT SDATA_OUT
R3 0 SYNC 10 C16 C17
AC97_SYNC SYNC 35
R4 0 RESET 11 SPK_OUT_L AC97_SPK_OUT_L 100P 100P
AC97_RESET RESET_ 33
SPK_OUT_LN AC97_SPK_OUT_LN
36
R5 0 SPK_OUT_R AC97_SPK_OUT_R
AC97_AUX3 37 FB6
SPK_OUT_RN AC97_SPK_OUT_RN SPK_OUT_R
J3
21 AC97_SPK_OUT_RN BEAD
AC97_MIC1P MIC1P ALC5610
22
AC97_MIC1N MIC1N FB7
29
AC97_MIC2P MIC2P AC97_SPK_OUT_R BEAD SPKR_CON
30 28
AC97_MIC2N MIC2N MICBIAS AC97_MIC_BIAS1
27 C18 C19
VREF
100P 100P
19 C21 C22
AC97_PHONEP PHONEP
20 0.1u 4.7u
AC97_PHONEN PHONEN
23
AC97_LINEL LINE_IN_L
24 45
AC97_LINER LINE_IN_R GPIO2BARIRQOUT AC97_GPIO2
AC97_XP
AC97_YP
14
15
XPLUS
YPLUS
GPIO1BARVBCLK
GPIO3BARVSLRCK
44
46
AC97_VBCLK
AC97_VSLRCK
Single_End Output
16 47
AC97_XN XMINUS GPIO4BARVSDAC AC97_VSDAC AVDD
17 48
AC97_YN YMINUS GPIO5BARVSADC AC97_VSADC
R6
C25 C26 C27 C28 100k
12
0.01u 0.01u 0.01u 0.01u AUX4
SPKGND
HPGND
DGND1
DGND2
TPGND
AGND1
AGND2
C23 FB8 HP_OUT1

RGND1 NC 1
AC97_HP_OUT_R 220u BEAD 2
R10 RGND2 C24 FB9 3
26
42
18
40
34
4
4
AC97_AUX4 BEAD AC97_HP_OUT_L BEAD 5

0 220u
D2 Front
AC97_MIC_BIAS2 R7 R8 R9
DGND AGND AC97_VSADC
4.7k 4.7k C29 C30 10K
Tied at one point only under the PESD5V0S2BT
100P 100P C49
codec or near the codec 0.1u
C34
BITCLK
22p
C35 POR1
DVDD RESET1 RESET2
SYNC RESET
22p
10k/NC 300/NC
C36
Single_End Input
C37
RESET 0.1u R13 R11
AC97_MIC_BIAS2
22p 5.6k C31 680
4.7u
BTL Input C32 FB10

J5
R14 R12 AC97_MIC2P BEAD

1u
AC97_MIC_BIAS1
5.6k 680 D3
C20 MIC2_CON
C33
4.7u MIC_SIG_IN
100P
J4 J6 PESD5V0S1BA
FB13 C42 FB14
AC97_PHONEP PHONEP_DIFF_IN AC97_MIC1P
BEAD BEAD
LINE_IN1
FB15 1u FB16 C38 FB11
C43 1
AC97_PHONEN BEAD PHONEN_DIFF_IN AC97_MIC1N BEAD AC97_LINER 1u BEAD 2
PHONE_CON 1u MIC1_CON C39 FB12 3
4
D5 D6 MIC_DIFF_IN AC97_LINEL BEAD 5
R15 1u C40 C41
C44 C45 C46 C47 D4
680 100P 100P
100P 100P PESD5V0S2BT 100P 100P PESD5V0S2BT
PESD5V0S2BT
Voice PCM Interface
ALC5610
Datasheet
11. Mechanical Dimensions
Voice PCM Interface
ALC5610
Datasheet
12. Appendix A: Voice PCM Interface

12.1. Master Mode: (voice_port_sel=0)
Voice PCM Interface
ALC5610
Datasheet
Voice PCM Interface
ALC5610
Datasheet
12.2. Slave Mode: (voice_port_sel=1)
X ==> Dont Care
==> forbidden
Voice PCM Interface
ALC5610
Datasheet
13. Ordering Information

Table 96. Ordering Information
Part Number Package Status
ALC5610-GR QFN-48 in Green Package (Tray) MP
ALC5610-GRT QFN-48 in Green Package (Tape & Reel) MP
Note 1: See page 6 for Green package and version identification.
Note 2: Above parts are tested under AVDD=3.3V.
Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
Voice PCM Interface

ALC5610 Datasheet 1.2

Uploaded by

Copyright:

Available Formats

ALC5610 Datasheet 1.2

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ALC5610 Datasheet 1.2

Uploaded by

Copyright:

Available Formats

ALC5610-GR

AC97 AUDIO CODEC + TOUCH PANEL

Realtek Semiconductor Corp.

USING THIS DOCUMENT

3. SYSTEM APPLICATIONS ...............................................................................................................................................3

4. FUNCTION BLOCK DIAGRAM.....................................................................................................................................4

11. MECHANICAL DIMENSIONS .................................................................................................................................77

12. APPENDIX A: VOICE PCM INTERFACE..............................................................................................................78

One analog stereo input (LINE-IN)

25mW SE or 75mW BTL MONO output support (AVDD=3.3V, 32 load)

Microphone switch detection

Power management and enhanced power saving

Supports digital 5 band equalizer (EQ)

Supports digital spatial sound and pseudo stereo effect

Supports pop noise suppression

Resistive touch panel interface

48-pin QFN package

GPS/Personal Navigation Device (PND) or Multi-Media phone

Personal Media Player (PMP)

4. Function Block Diagram

Figure 1. Block Diagram

Voice PCM Interface

AC97 Audio Codec + Touch Panel Controller +

Audio Mixer Path

Track ID: JATR-1076-21

MCLK 2 35 SPK_ OUT_L

DGND 1 4 33 SPK _OUT_ LN

SDATA _OUT 5 32 MONO_OUTN

BIT_ CLK 6 31 MONO_OUT

SDATA _IN 8 29 MIC2P

AUX4 /MICBIAS2 12 25 AVDD 1

Figure 3. Pin Assignments

5.1. Green Package and Version Identification

6.2. Analog I/O Pins

Table 5. Power Setting for Best Performance

Table 6. Reset Operation

7.2.1. Power-On Reset (POR)

Table 7. Power-On Reset Voltage

7.3.1. Phase-Locked Loop

The PLL transmit formula is:

FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}

Table 8. AC-Link Clock Setting Table (Unit: MHz)

7.3.2. AC97 Mode

7.3.3. Voice_I2S/PCM Interface

7.3.4. Voice ADC

7.4. Digital Data Interface

Figure 4. AC-Link Wake Up Timing

SDATA-OUT TAG CMD DATA PCML PCMR

TAG ADDR DATA PCML PCMR AUX Status

Figure 5. Default ALC5610 Slot Arrangement CODEC ID Always 00

AC97 Controller AC97

7.4.2. Voice I2S/PCM Interface

Figure 7. PCM MONO Data Mode A Format (bclk_polarity=0)

Figure 8. PCM MONO Data Mode A Format (bclk_polarity=1)

Figure 9. PCM MONO Data Mode B Format (bclk_polarity=0)

Figure 10. PCM Stereo Data Mode A Format (bclk_polarity=0)

Figure 11. PCM Stereo Data Mode B Format (bclk_polarity=0)

Figure 12. I2S Data Format (bclk_polarity=0)

Figure 13. Left-Justified Data Format (bclk_polarity=0)

Figure 14. Right-Justified Data Format (bclk_polarity=0)