Sai Vidya Institute of Technology

Department Electronics and communication Engineering

Semester: 5TH Subject: Verilog HDL(15EC53)

Module 3
Gate-Level Modeling
Modeling using basic Verilog gate primitives, description of and/or and buf/not type
gates, rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modeling
Continuous assignments, delay specification, expressions, operators, operands,
operator types.

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 In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of
abstraction in verilog. They are:

Behavioral or algorithmic level: This is the highest level of abstraction. A

module can be implemented in terms of the design algorithm. The
designer no need to have any knowledge of hardware implementation.

Data flow level: In this level the module is designed by specifying the data
flow. Designer must how data flows between various registers of the
design.

Gate level: The module is implemented in terms of logic gates and

interconnections between these gates. Designer should know the gate-
level diagram of the design.

Switch level: This is the lowest level of abstraction. The design is

implemented using switches/transistors. Designer requires the knowledge
of switch-level implementation details.

Gate-level modeling is virtually the lowest-level of abstraction, because the switch-level abstraction is
rarely used. In general, gate-level modeling is used for implementing lowest level modules in a design like,
full-adder, multiplexers, etc. Verilog HDL has gate primitives for all basic gates.
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Gate Primitives
Gate primitives are predefined in Verilog, which are ready to use. They are instantiated like
modules. There are two classes of gate primitives: Multiple input gate primitives and Single input
gate primitives.
Multiple input gate primitives (and/or) include and, nand, or, nor, xor, and xnor.
These can have multiple inputs and a single output. They are instantiated as
follows:
// Two input AND gate. // Three input NAND gate.
and and_1 (out, in0, in1); nand nand_1 (out, in0, in1, in2);

// Two input OR gate. // Four input NOR gate.

or or_1 (out, in0, in1); nor nor_1 (out, in0, in1, in2, in3);

// Two input XNOR gate. // Five input XOR gate.

xnor and_1 (out, in0, in1); xor xor_1 (out, in0, in1, in2, in3, in4);

wire OUT, IN1, IN2;

and (OUT, IN1, IN2); // legal gate instantiation

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The truth tables of multiple input gate primitives are as follows:

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 Single input gate primitives(not/buf):

Single input gate primitives include not, buf, notif1, bufif1, notif0, and bufif0. These have a single input and
one output.
Gate primitives notif1, bufif1, notif0, and bufif0 have a control signal. The gates propagate if only control signal
is asserted, else the output will be high impedance state (z). They are instantiated as follows:
// Inverting gate.
not not_1 (out, in);

// Two output buffer gate.

buf buf_1 (out0, out1, in);

// Single output Inverting gate with active-high control signal.

notif1 notif1_1 (out, in, ctrl);

// Double output buffer gate with active-high control signal.

bufif1 bufif1_1 (out0, out1, in, ctrl);

// Single output Inverting gate with active-low control signal.

notif0 notif0_1 (out, in, ctrl);

// Single output buffer gate with active-low control signal.

bufif0 bufif1_0 (out, in, ctrl); SVIT,Dept of ECE 5
The truth tables of single input gate primitives are as follows:

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Array of Instances:

There are many situations when repetitive instances are required. These instances differ from
each other only by the index of the vector to which they are connected.

wire [3:0] out, in0, in1;

and and_array[3:0] (out, in0, in1);

The above statement is equivalent to following bunch of statements:

and and_array0 (out[0], in0[0], in1[0]);

and and_array1 (out[1], in0[1], in1[1]);
and and_array2 (out[2], in0[2], in1[2]);
and and_array3 (out[3], in0[3], in1[3]);

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Examples
Example 1: 4 to 1 Multiplexer

Logic Diagram Truth Table Circuit Diagram

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Verilog Code for 4 to 1 Multiplexer module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations
output out; //output ports.
input i0, i1, i2, i3; // Input ports.
input s1, s0; // Input ports: select lines.

// intermediate wires
wire s1n, s0n; // Inverter outputs.
wire y0, y1, y2, y3; // AND gates outputs.

// Gate instantiations

// Inverters.
not (s1n, s1);
not (s0n, s0);

// 3-input and gates

and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);

// 4-input or gate
or (out, y0, y1, y2, y3);
endmodule
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Stimulus for 4 to 1 multiplexer
// Define the stimulus module (no ports)
module stimulus;

// Declare variables to be connected to inputs

reg IN0, IN1, IN2, IN3;
reg S1, S0;

// Declare output wire

wire OUTPUT;

// Instantiate the multiplexer

mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

// Stimulate the inputs

// Define the stimulus module (no ports)
initial
Begin

// set input lines

IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
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#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);
// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

end
endmodule

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Output of the simulation :

IN0= 1, IN1= 0, IN2= 1, IN3= 0

S1 = 0, S0 = 0, OUTPUT = 1

S1 = 0, S0 = 1, OUTPUT = 0

S1 = 1, S0 = 0, OUTPUT = 1

S1 = 1, S0 = 1, OUTPUT = 0

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Example 2: 4-bit Ripple Carry Full Adder

Block Diagram :

A 4-bit ripple carry full adder can be constructed from four 1-bit full adders

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Design of 1- bit Full adder:

Mathematical Expression: sum=(ab cin)

cout=(a*b)+cin*(a b)

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// Define a 1-bit full adder

module fulladd(sum, c_out, a, b, c_in);

// I/O port declarations

output sum, c_out;

input a, b, c_in;

// Internal nets

wire s1, c1, s2;

// Instantiate logic gate primitives

xor (s1, a, b);

and (c1, a, b);
xor (sum, s1, c_in);
and (s2, s1, c_in);
xor (c_out, s2, c1);

endmodule

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Design of 4- bit Full adder:
// Define a 4-bit full adder

module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;

output c_out;
input[3:0] a, b;
input c_in;

// Internal nets

wire c1, c2, c3;

// Instantiate four 1-bit full adders.

fulladd fa0(sum[0], c1, a[0], b[0], c_in);

fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
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Stimulus for 4-bit Ripple Carry Full Adder
// Define the stimulus (top level module)

module stimulus;

// Set up variables

reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4

fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

// Set up the monitoring for the signal values

initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b, SUM= %b\n",
A, B, C_IN, C_OUT, SUM);
end
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// Stimulate inputs

initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
#5 A = 4'd2; B = 4'd5;
#5 A = 4'd9; B = 4'd9;
#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
endmodule

The output of the simulation is shown below:

0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000

5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111
10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111
15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010
20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
25 A= 1010, B=0101, C_IN= 1,, C_OUT= 1, SUM= 0000

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Create your own 2-input Verilog gates called my-or, my-and and my-not from 2-input nand gates. Check the
functionality of these gates with a stimulus module.

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module my_or(out, in1, in2); module my_and(out, in1, in2); module my_not(out,
output out; in);
output out; input in1, in2; output out;
input in1, in2; input in;
wire a, b; wire a;
nand (out, in, in);
//implementation out = (in1' . in2')' //implementation out = ((in1.in2)')'
nand (a, in1, in1); nand (a, in1, in2); endmodule
nand (b, in2, in2);
nand (out, a, a);
nand (out, a, b);
endmodule
endmodule

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module stimulus;

wire OUT_OR, OUT_AND, OUT_NOT;

reg IN1, IN2;

initial
$monitor($time, " OUT_OR = %b, OUT_AND = %b, OUT_NOT = %b, IN1 = %b, IN2 = %b",
OUT_OR, OUT_AND, OUT_NOT, IN1, IN2);

initial
begin
IN1 = 1'B1; IN2 = 1'B1;
#5 IN1 = 1'B1; IN2 = 1'B0;
#5 IN1 = 1'B0; IN2 = 1'B1;
#5 IN1 = 1'B0; IN2 = 1'B0;
end

my_or o1(OUT_OR, IN1, IN2);

my_and a1(OUT_AND, IN1, IN2);
my_not n1(OUT_NOT, IN1);

endmodule
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Gate Delays
In Verilog, a designer can specify the gate delays in a gate primitive instance. This helps the designer to get a real
time behavior of the logic circuit.

There are three types of delays from the inputs to the output of a primitive gate

Rise delay: It is equal to the time taken by a gate output transition to 1, from another value 0, x, or z.

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Fall delay: It is equal to the time taken by a gate output transition to 0, from another value 1, x, or z.

Turn-off delay: It is equal to the time taken by a gate output transition to high impedance state, from
another value 1, x, or z.

If the gate output changes to x, the minimum of the three delays is considered.

If only one delay is specified, it is used for all delays.

If two values are specified, they are considered as rise, and fall delays.

If three values are specified, they are considered as rise, fall, and turn-off delays.

The default value of all delays is zero.

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Types of Delay Specification:

and #(delay-time) a1(out, i1, i2); // Delay of delay-time for all transitions

and # (rise-val, fall-val) a2 (out, i1, i2) ; // Rise and Fall Delay Specification.

bufifO #(rise-val, fall-val, turnoff-val) b1 (out, in, control); // Rise, Fall, and Turn-off Delay Specification

Examples of delay specification

and #(5) al(out,i1,i2); //Delay of 5 for all transitions

and #(4,6) a2(out,i1,i2); // Rise = 4, Fall = 6

bufif0 # (3,4,5) b1 (out, in, control); // Rise= 3, Fall = 4, Turn-off = 5

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Min/Typ/Max Values

There is another way of specifying delay times in verilog, Min/Typ/Max values for each delay.

Min value
The min value is the minimum delay value that the designer expects the gate to have.

Typ val
The typ value is the typical delay value that the designer expects the gate to have.

Max value
The max value is the maximum delay value that the designer expects the gate to have.

This helps designer to have a much better real time experience of design simulation, as in real time logic circuits the delays
are not constant.
The user can choose one of the delay values using +maxdelays, +typdelays, and +mindelays at run time.
The typical value is the default value.

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 Examples for Min, Max and Typical Delay Values

// One delay
// if +mindelays, delay= 4
// if +typdelays, delay= 5
// if +maxdelays, delay= 6

and #(4:5:6) al(out, i1, i2);

// Two delays
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)

and #(3:4:5, 5:6:7) a2(out, i1, i2);

// Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6

and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);

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Delay Example
Let us consider a simple example of simple module called D implements the following equation:
out=(a*b)+c Verilog Definition for Module D with Delay

module D (out, a, b, c); // Define a simple combination module called D

output out; // o/p port declarations

input a,b,c; // o/p port declarations

wire e; // Internal nets

// Instantiate primitive gates to build the circuit

Module D and #(5) a1(e, a, b); //Delay of 5 on gate a1

or #(4) o1(out, e,c); //Delay of 4 on gate o1

endmodule

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Stimulus for Module D with Delay // Stimulus (top-level module)
module stimulus;

// Declare variables
reg A, B, C;
wire OUT;

// Instantiate the module D

D d1( OUT, A, B, C);

// Stimulate the inputs. Finish the simulation at 40 time units.

initial
Begin

A= 1'b0; B= 1'b0; C= 1'b0;

#10 A= 1'b1; B= 1'b1; C= 1'b1;
#10 A= 1'b1; B= 1'b0; C= 1'b0;
#20 $finish;

end
endmodule

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The waveforms illustrates the effect of specifying delays on gates.

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 Dataflow Modeling
Introduction:
Dataflow modeling is a higher level of abstraction.
The designer no need have any knowledge of logic circuit. He should be aware of data flow of the design.
The gate level modeling becomes very complex for a VLSI circuit.
Hence dataflow modeling became a very important way of implementing the design.

In dataflow modeling most of the design is implemented using continuous assignments, which are used to drive a value
onto a net. The continuous assignments are made using the keyword assign
The assign statement
The assign statement is used to make continuous assignment in the dataflow modeling. The assign statement
usage is given below:

assign out = in0 + in1; // in0 + in1 is evaluated and then assigned to out.
Syntax:
continuous_assign ::= assign [ drive_strength ] [ delay3 ] list_of_net_assignments ;
list_of_net_assignments ::= net_assignment { , net_assignment }
net_assignment ::= net_lvalue = expression

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Characteristics of continuous assignment:

The LHS of assign statement must always be a scalar or vector net or a concatenation. It cannot be a register.
Continuous statements are always active statements.
Registers or nets or function calls can come in the RHS of the assignment.
The RHS expression is evaluated whenever one of its operands changes. Then the result is assigned to the LHS.
Delays can be specified.

Examples of Continuous Assignment

assign out = i1 & i2; // Continuous assign. out is a net. i1 and i2 are nets.

// Continuous assign for vector nets. addr is a 16-bit vector net

assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0]; // addr1 and addr2 are 16-bit vector registers.

// Concatenation. Left-hand side is a concatenation of a scalar

assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in; // net and a vector net.

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Implicit Continuous Assignment

//Regular continuous assignment

wire out;
assign out = in1 & in2;
//Same effect is achieved by an implicit continuous assignment
wire out = in1 & in2;

Implicit Net Declaration

// Continuous assign. out is a net.

wire i1, i2;
assign out = i1 & i2; //Note that out was not declared as a wire but an implicit wire declaration for out is done by the simulator

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Delays:
There are three types of delays associated with dataflow modeling. They are:
Normal/regular assignment delay,
implicit continuous assignment delay and
net declaration delay.

Normal/regular assignment delay,

The first method is to assign a delay value in a continuous assignment statement. The delay value is specified
after the keyword assign.

assign #10 out = in1 & in2; // Delay in a continuous assign

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Implicit Continuous Assignment Delay:
An equivalent method is to use an implicit continuous assignment to specify both a delay and an assignment on the n

//implicit continuous assignment delay

wire #10 out = in1 & in2;

//same as
wire out;
assign #10 out = in1 & in2;
Net Declaration Delay
A delay can be specified on a net when it is declared without putting a continuous assignment on the net.

If a delay is specified on a net out, then any value change applied to the net out is delayed accordingly.
//Net Delays
wire # 10 out;
assign out = in1 & in2;

//The above statement has the same effect as the following.

wire out;
assign #10 out = in1 & in2;

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Verilog code for 4:1 mux using assign statement

module mux_4x1 (out, in0, in1, in2, in3, s0, s1);

output out;
input in0, in1, in2, in3;
input s0, s1;

assign out = (~s0 & ~s1 & in0)|(s0 & ~s1 & in1)|
(~s0 & s1 & in2)|(s0 & s1 & in3);

endmodule

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 Verilog code for 2*4 decoder using assign statement

module decoder_2x4 (out, in0, in1);

output out[3:0];
input in0, in1;
input en;
// Data flow modeling uses logic operators.
assign out[3:0] = ( ~in0 & ~in1 &en)|(in0 & ~in1 &en)|(~in0 & in1 &en )|( in0 & in1 &en );

endmodule

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 Expressions, Operators, and Operands
Dataflow modeling describes the design in terms of expressions instead of primitive gates. Expressions, operators, and
operands form the basis of dataflow modeling.
Expressions
Expressions are constructs that combine operators and operands to produce a result.
a^b
addr1[20:17] + addr2[20:17]
in1 | in2

Operands
Operands can be any one of the data types
Operands can be constants, integers, real numbers, nets, registers, times, bit-select (one bit of vector net or a
vector register), part-select (selected bits of the vector net or register vector), and memories or function calls
integer count, final_count; reg [15:0] reg1, reg2;
final_count = count + 1;//count is an integer operand reg [3:0] reg_out;
reg_out = reg1[3:0] ^ reg2[3:0];//reg1[3:0] and reg2[3:0] are
real a, b, c; //part-select register operands
c = a - b; //a and b are real operands reg ret_value;
ret_value = calculate_parity(A, B);//calculate_parity is a
//function type operand

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 Operators
Operators act on the operands to produce desired results. Verilog provides various types of operators
d1 && d2 // && is an operator on operands d1 and d2
!a[0] // ! is an operator on operand a[0]
B >> 1 // >> is an operator on operands B and 1

Operator Types
Verilog provides many different operator types.
Operators can be arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, or conditional.
Some of these operators are similar to the operators used in the C programming language.

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 Arithmetic Operators
There are two types of arithmetic operators: binary and unary.
Binary operators

Binary arithmetic operators are multiply (*), divide (/), add (+), subtract (-), power (**), and modulus (%). Binary
operators take two operands.

A = 4'b0011; B = 4'b0100; // A and B are register vectors

D = 6; E = 4; F=2// D and E are integers

A * B // Multiply A and B. Evaluates to 4'b1100

D / E // Divide D by E. Evaluates to 1. Truncates any fractional part.
A + B // Add A and B. Evaluates to 4'b0111
B - A // Subtract A from B. Evaluates to 4'b0001
F = E ** F; //E to the power F, yields 16

Note :If any operand bit has a value x, then the result of the entire expression is x.
in1 = 4'b101x;
in2 = 4'b1010;
sum = in1 + in2; // sum will be evaluated to the value 4'bx

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Modulus operators produce the remainder from the division of two numbers. They operate similarly to the modulus
operator in the C programming language.
13 % 3 // Evaluates to 1
16 % 4 // Evaluates to 0
-7 % 2 // Evaluates to -1, takes sign of the first operand
7 % -2 // Evaluates to +1, takes sign of the first operand

Unary operators
They are used to specify the positive or negative sign of the operand.
-4 // Negative 4
+5 // Positive 5
-10 / 5// Evaluates to -2

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 Logical Operators
Logical operators are logical-and (&&), logical-or (||) and logical-not (!). Operators && and || are binary operators.
Operator ! is a unary operator. Logical operators follow these conditions:

1. Logical operators always evaluate to a 1-bit value, 0 (false), 1 (true), or x (ambiguous).

2. If an operand is not equal to zero, it is equivalent to a logical 1 (true condition).

If it is 01 equal to zero, it is equivalent to a logical 0 (false condition).
If any operand bit is x or z, it is equivalent to x (ambiguous condition) and is normally treated by
simulators as a false condition.

3. Logical operators take variables or expressions as operands.

// Logical operations

A = 3; B = 0;
A && B // Evaluates to 0. Equivalent to (logical-1 && logical-0)
A || B // Evaluates to 1. Equivalent to (logical-1 || logical-0)

!A// Evaluates to 0. Equivalent to not(logical-1)

!B// Evaluates to 1. Equivalent to not(logical-0)

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 // Unknowns
A = 2'b0x; B = 2'b10;
A && B // Evaluates to x. Equivalent to (x && logical 1)
// Expressions
(a == 2) && (b == 3) // Evaluates to 1 if both a == 2 and b == 3 are true.
// Evaluates to 0 if either is false.

Relational Operators
Relational operators are greater-than (>), less-than (<), greater-than-or-equal-to (>=), and less-than-or-equal-to
(<=).

If relational operators are used in an expression, the expression returns a logical value of 1 if the expression
is true and 0 if the expression is false.

If there are any unknown or z bits in the operands, the expression takes a value x.
// A = 4, B = 3
// X = 4'b1010, Y = 4'b1101, Z = 4'b1xxx
A <= B // Evaluates to a logical 0
A > B // Evaluates to a logical 1
Y >= X // Evaluates to a logical 1
Y < Z // Evaluates to an x
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 Equality Operators
Equality operators are logical equality (==), logical inequality (!=), case equality (===), and case inequality
(!==). When used in an expression, equality operators return logical value 1 if true, 0 if false.

// A = 4, B = 3
// X = 4'b1010, Y = 4'b1101
// Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx
A == B // Results in logical 0
X != Y // Results in logical 1
X == Z // Results in x
Z === M // Results in logical 1 (all bits match, including x and z)
Z === N // Results in logical 0 (least significant bit does not match)
M !== N // Results in logical 1
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 Bitwise Operators

Bitwise operators are negation (~), and(&), or (|), xor (^), xnor (^~, ~^). Bitwise operators perform a bit-by-bit
operation on two operands.
They take each bit in one operand and perform the operation with the corresponding bit in the other operand.

Example:
// X = 4'b1010, Y = 4'b1101
// Z = 4'b10x1
~X // Negation. Result is 4'b0101
X & Y // Bitwise and. Result is 4'b1000
X | Y // Bitwise or. Result is 4'b1111
X ^ Y // Bitwise xor. Result is 4'b0111
X ^~ Y // Bitwise xnor. Result is 4'b1000
X & Z // Result is 4'b10x0

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 Reduction Operators
Reduction operators are and (&), nand (~&), or (|), nor (~|), xor (^), and xnor (~^, ^~).
Reduction operators take only one operand.
Reduction operators perform a bitwise operation on a single vector operand and yield a 1-bit result.
// X = 4'b1010
&X //Equivalent to 1 & 0 & 1 & 0. Results in 1'b0
|X//Equivalent to 1 | 0 | 1 | 0. Results in 1'b1
^X//Equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1'b0
//A reduction xor or xnor can be used for even or odd parity
//generation of a vector.
Shift Operators
Shift operators are right shift ( >>), left shift (<<), arithmetic right shift (>>>), and arithmetic left shift
(<<<).
Regular shift operators shift a vector operand to the right or the left by a specified number of bits.
// X = 4'b1100
Y = X >> 1; //Y is 4'b0110. Shift right 1 bit. 0 filled in MSB position.
Y = X << 1; //Y is 4'b1000. Shift left 1 bit. 0 filled in LSB position.
Y = X << 2; //Y is 4'b0000. Shift left 2 bits.
integer a, b, c; //Signed data types
a = 0;
b = -10; // 00111...10110 binary
c = a + (b >>> 3); //Results in -2 decimal, due to arithmetic shift
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 Concatenation Operator
The concatenation operator ( {, } ) provides a mechanism to append multiple operands.
The operands must be sized.
Unsized operands are not allowed because the size of each operand must be known for computation of the size
of the result.
Concatenations are expressed as operands within braces, with commas separating the operands.
Operands can be scalar nets or registers, vector nets or registers, bit-select, part-select, or sized constants.
// A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110
Y = {B , C} // Result Y is 4'b0010
Y = {A , B , C , D , 3'b001} // Result Y is 11'b10010110001
Y = {A , B[0], C[1]} // Result Y is 3'b101
Replication Operator
Repetitive concatenation of the same number can be expressed by using a replication constant.
A replication constant specifies how many times to replicate the number inside the brackets ( { } )
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} } // Result Y is 4'b1111
Y = { 4{A} , 2{B} } // Result Y is 8'b11110000
Y = { 4{A} , 2{B} , C } // Result Y is 8'b1111000010
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 Conditional Operator
The conditional operator(?:) takes three operands.
Usage: condition_expr ? true_expr : false_expr ;

The condition expression (condition_expr) is first evaluated.

If the result is true (logical 1), then the true_expr is evaluated.
If the result is false (logical 0), then the false_expr is evaluated.
If the result is x (ambiguous), then both true_expr and false_expr are evaluated
The action of a conditional operator is similar to a multiplexer. Alternately, it can be compared to the if-else
expression.
Example

//model functionality of a tristate buffer

assign addr_bus = drive_enable ? addr_out : 36'bz;
//model functionality of a 2-to-1 mux
assign out = control ? in1 : in0;

assign out =(A == 3)?( control ? x : y ):( control ? m : n);

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Examples
Example 1: 4 to 1 Multiplexer

Logic Diagram Truth Table

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METHOD 1 : 4-to-1 Multiplexer, Using Logic Equations

// Module 4-to-1 multiplexer using data flow. logic equation

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;

//Logic equation for out

assign out = (~s1 & ~s0 & i0)|

(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3) ;

endmodule

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METHOD 2 : 4-to-1 Multiplexer, Using Conditional Operators

// Module 4-to-1 multiplexer using data flow. Conditional operator.

module multiplexer4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;

// Use nested conditional operator

assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;

endmodule

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4-bit Full Adder
Method 1: dataflow operators

// Define a 4-bit full adder by using dataflow statements.

module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;

output c_out;
input[3:0] a, b;
input c_in;

// Specify the function of a full adder

assign {c_out, sum} = a + b + c_in;

endmodule

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Method 2: full adder with carry lookahead

Ai Bi Pi = Ai Bi
Gi Gi = Ai Bi

Pi
Ci

C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
Ci+1 Si C3 = G2 + P2 C2 = G2 P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 P3 G2 P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
Sumi = Pi Ci
Ci+1 = Gi + ( Pi Ci)

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module fulladd4(sum, c_out, a, b, c_in);
// Inputs and outputs
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
// Internal wires
wire p0,g0, p1,g1, p2,g2, p3,g3;
wire c4, c3, c2, c1;
// compute the p for each stage
assign p0 = a[0] ^ b[0],
p1 = a[1] ^ b[1],
p2 = a[2] ^ b[2],
p3 = a[3] ^ b[3];
// compute the g for each stage
assign g0 = a[0] & b[0],
g1 = a[1] & b[1],
g2 = a[2] & b[2],
g3 = a[3] & b[3];

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// compute the carry for each stage
// carry lookahead computation

assign c1 = g0 | (p0 & c_in),

c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),
c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |
(p3 & p2 & p1 & p0 & c_in);

// Compute Sum

assign sum[0] = p0 ^ c_in,

sum[1] = p1 ^ c1,
sum[2] = p2 ^ c2,
sum[3] = p3 ^ c3;

// Assign carry output

assign c_out = c4;

endmodule

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Ripple Counter

4-bit Ripple Carry Counter Negative Edge-Triggered D-flipflop with Clear

T-flipflop
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Verilog Code for Ripple Counter Verilog Code for T-flipflop

// Ripple counter // Edge-triggered T-flipflop. Toggles every clockcycle.

module T_FF(q, clk, clear);
module counter(Q , clock, clear);
// I/O ports
// I/O ports
output q;
output [3:0] Q; input clk, clear;
input clock, clear;
// Instantiate the edge-triggered DFF
// Instantiate the T flipflops // Complement of output q is fed back.
// Notice qbar not needed. Unconnected port.
T_FF tff0(Q[0], clock, clear);
T_FF tff1(Q[1], Q[0], clear); edge_dff ff1(q, ,~q, clk, clear);
T_FF tff2(Q[2], Q[1], clear); endmodule
T_FF tff3(Q[3], Q[2], clear);
endmodule

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Verilog Code for Edge-Triggered D-flipflop
assign sbar = ~(rbar & s),
// Edge-triggered D flipflop s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
module edge_dff(q, qbar, d, clk, clear); rbar = ~(r & cbar & d);

// Inputs and outputs // Output latch

assign q = ~(s & qbar),
output q,qbar; qbar = ~(q & r & cbar);
input d, clk, clear; endmodule
// Internal variables

wire s, sbar, r, rbar,cbar;

// dataflow statements
//Create a complement of signal clear
assign cbar = ~clear;

// Input latches; A latch is level

sensitive. An edge-sensitive
// flip-flop is implemented by using 3 SR
latches.
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Stimulus Module for Ripple Counter

// Top level stimulus module

module stimulus;

// Declare variables for stimulating input

reg CLOCK, CLEAR;
wire [3:0] Q;
initial
$monitor($time, " Count Q = %b Clear= %b", Q[3:0],CLEAR);

// Instantiate the design block counter

counter c1(Q, CLOCK, CLEAR);

// Stimulate the Clear Signal

initial
begin
CLEAR = 1'b1;
#34 CLEAR = 1'b0;
#200 CLEAR = 1'b1;
#50 CLEAR = 1'b0;
End

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// Set up the clock to toggle every 10 time units
initial
begin
CLOCK = 1'b0;
forever #10 CLOCK = ~CLOCK;
End

// Finish the simulation at time 400

initial
begin
#400 $finish;
end
endmodule

Simulated output:

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