Esp32 Hardware Design Guidelines en
Esp32 Hardware Design Guidelines en
Esp32 Hardware Design Guidelines en
Espressif Systems
June 28, 2017
About This Guide
The guidelines outline recommended design practices when developing standalone or add-on systems based
on the ESP32 series of products, including ESP32, the ESP-WROOM-32 module, and ESP32-DevKitC the
development board.
Related Resources
For additional documentation and resources on ESP32, please visit Espressif website: ESP32 Resources.
Release Notes
Date Version Release notes
2016.12 V1.0 First release.
2016.12 V1.1 Updated Table 4.
Updated Chapter Overview;
Updated Figure Function Block Diagram;
Updated Chapter Pin Definitions;
Updated Section Power Supply;
2017.03 V1.2
Updated Section RF;
Updated Figure ESP-WROOM-32 Pin Layout;
Updated Table ESP-WROOM-32 Pin Definitions;
Updated Section Notes.
Updated the notice to Table ESP32 Pin Description;
2017.03 V1.3
Added a note to Table ESP-WROOM-32 Pin Definitions.
Updated Section Strapping Pins;
Updated Figure ESP32 Pin Layout (for QFN 5*5);
2017.04 V1.4
Updated Figure ESP-WROOM-32 Module;
Updated Figure ESP32-DevKitC Pin Layout.
2017.04 V1.5 Added the ESP-WROOOM-32 modules dimensional tolerance.
Updated Figure ESP-WROOM-32 Pin Layout;
2017.05 V1.6
Added a note in Section 2.3 Strapping Pins.
2017.05 V1.7 Added a note to Section 4.1.1 ESP-WROOM-32 Overview.
Updated Section 3.1.2.1 Power-on Sequence;
Updated Section 3.1.4.1 External Clock Source (Compulsory);
2017.06 V1.8
Added a link to ESP32 Pin Lists;
Added Documentation Change Notification.
Changed the input power supply range of CPU/RTC IO to 1.8V ~ 3.6V;
2017.06 V1.9
Updated Section 3.1.1.1 Digital Power Supply.
1 Overview 7
1.1 Basic Protocols 7
1.1.1 Wi-Fi 7
1.1.2 Bluetooth 7
1.2 Application 8
1.3 Function Block Diagram 9
2 Pin Definitions 10
2.1 Pin Layout 10
2.2 Pin Description 11
2.3 Strapping Pins 13
4 Hardware Development 26
4.1 ESP-WROOM-32 Module 26
4.1.1 Overview 26
4.1.2 Pin Definition 27
4.1.3 Notes 29
4.2 ESP32-DevKitC 30
4.2.1 Overview 30
4.2.2 Schematics 31
4.2.2.1 Power Schematics 31
4.2.2.2 USB-UART Schematics 31
5 Applications 32
5.1 UART to Wi-Fi Smart Device 32
5.2 ESP32-Lyra Smart Audio Platform 32
List of Tables
1 Pin Description 11
2 Strapping Pins 14
3 ESP-WROOM-32 Pin Definitions 27
4 Pin Definition of UART Interfaces 32
List of Figures
1 Function Block Diagram 9
2 ESP32 Pin Layout (for QFN 6*6) 10
3 ESP32 Pin Layout (for QFN 5*5) 11
4 ESP32 Schematics 15
5 ESP32 Digital Power Supply Pins 16
6 ESP32 Analog Power Supply Pins 17
7 ESP32 Flash 18
8 ESP32 Crystal Oscillator 19
9 ESP32 Crystal Oscillator (RTC) 19
10 ESP32 RF Matching Schematics 19
11 ESP32 Sensor External Sampling Capacitor 20
12 ESP32 External Capacitor 20
13 ESP32 PCB Layout 21
14 ESP32 Crystal Oscillator Layout 22
15 ESP32 RF Layout 22
16 PAD/TV Box Layout 23
17 ESP-WROOM-32 Module 26
18 ESP-WROOM-32 Pin Layout 27
19 Top view of ESP32-DevKitC 30
20 ESP32-DevKitC Pin Layout 30
21 Power Schematics of ESP32-DevKitC 31
22 USB-UART Schematics 31
1. OVERVIEW
1. Overview
ESP32 is a single 2.4 GHz Wi-Fi and Bluetooth combo chip designed with TSMC ultra-low power 40 nm technology.
It is designed to achieve the best power performance and RF performance in a wide variety of applications and
different power profiles, with robustness, versatility and reliability.
ESP32 is a Wi-Fi plus Bluetooth System-on-a-Chip (SoC). With only 18 external components, it has the optimal
level of integration in the industry. It integrates the complete transmit/receive RF functionality including the antenna
switches, RF balun, power amplifier, low noise receive amplifier, filters, power management, and advanced calibra-
tion circuitries that allow the solution to dynamically adjust itself to external circuit imperfections. As such, the mass
production of ESP32-based solutions does not require expensive and specialized Wi-Fi testing equipment.
The ESP32 series of chips include ESP32-D0WDQ6, ESP32-D0WD, ESP32-D2WD and ESP32-S0WD. For details
of part number and ordering information, please refer to ESP32 Datasheet.
WMM-PS, UAPSD
Block ACK
Wi-Fi Direct (P2P), P2P Discovery, P2P Group Owner mode and P2P Power Management
1.1.2 Bluetooth
Compliant with Bluetooth v4.2 BR/EDR and BLE specification
ATT/GATT
HID
BLE Beacon
1.2 Application
Generic low-power IoT sensor hub
Music players
Wi-Fi-enabled toys
Loggers
Audio headsets
Home automation
Mesh network
Baby monitors
Wearable electronics
Security ID tags
Healthcare
Switch
Balun
Clock
I2C generator
Wi-Fi
I2S Wi-Fi MAC RF
baseband
transmit
SDIO
UART Core and memory
Cryptographic hardware
CAN 2 or 1 x Xtensa 32- acceleration
bit LX6 Microprocessors
ETH SHA RSA
IR ROM SRAM
AES RNG
PWM
Temperature
sensor RTC
Touch sensor
ULP Recovery
PMU
DAC coprocesser memory
ADC
Note:
Products in the ESP32 series differ from each other in terms of the number of CPUs they have and their support for
embedded flash. For details, please refer to ESP32 Datasheet.
2. Pin Definitions
VDD3P3_CPU
XTAL_N
GPIO22
XTAL_P
U0RXD
U0TXD
GPIO19
GPIO21
VDDA
VDDA
CAP2
CAP1
40
48
44
38
46
43
42
39
45
47
37
41
VDDA 1 36 GPIO23
LNA_IN 2 35 GPIO18
VDD3P3 3 34 GPIO5
VDD3P3 4 33 SD_DATA_1
SENSOR_VP 5 32 SD_DATA_0
SENSOR_CAPP 6 31 SD_CLK
ESP32
SENSOR_CAPN 7 49 GND 30 SD_CMD
SENSOR_VN 8 29 SD_DATA_3
CHIP_PU 9 28 SD_DATA_2
VDET_1 10 27 GPIO17
VDET_2 11 26 VDD_SDIO
32K_XP 12 25 GPIO16
13
14
15
16
17
18
19
20
21
22
23
24
32K_XN
GPIO25
GPIO26
GPIO27
MTMS
MTDI
VDD3P3_RTC
MTCK
MTDO
GPIO2
GPIO0
GPIO4
XTAL_N
GPIO22
XTAL_P
U0RXD
U0TXD
GPIO21
VDDA
VDDA
CAP2
CAP1
40
48
44
46
43
42
39
45
47
41
VDDA 1 38 GPIO19
LNA_IN 2 37 VDD3P3_CPU
VDD3P3 3 36 GPIO23
VDD3P3 4 35 GPIO18
SENSOR_VP 5 34 GPIO5
SENSOR_CAPP 6 33 SD_DATA_1
SENSOR_CAPN 7 32 SD_DATA_0
ESP32
SENSOR_VN 8 31 SD_CLK
49 GND
CHIP_PU 9 30 SD_CMD
VDET_1 10 29 SD_DATA_3
VDET_2 11 28 SD_DATA_2
32K_XP 12 27 GPIO17
32K_XN 13 26 VDD_SDIO
GPIO25 14 25 GPIO16
15
16
17
18
19
20
21
22
23
24
GPIO26
GPIO27
MTMS
MTDI
VDD3P3_RTC
MTCK
MTDO
GPIO2
GPIO0
GPIO4
Note:
For details on ESP32s part number and the corresponding packaging information, please refer to ESP32 Datasheet.
Notice:
GPIO36, GPIO37, GPIO38, GPIO39, GPIO34 and GPIO35 can only be used for input.
ESP32-D2WDs pins GPIO16, GPIO17, SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1 are used for
connecting the embedding flash, and are not recommended for other uses.
For complete ESP32 pin lists, please refer to the appendix in ESP32 Datasheet.
Software can read the value of these five bits from the register GPIO_STRAPPING.
During the chip power-on reset, the latches of the strapping pins sample the voltage level as strapping bits of 0
or 1, and hold these bits until the chip is powered down or shut down. The strapping bits configure the device
boot mode, the operating voltage of VDD_SDIO and other system initial settings.
Each strapping pin is connected with its internal pull-up/pull-down during the chip reset. Consequently, if a strap-
ping pin is unconnected or the connected external circuit is high-impendence, the internal weak pull-up/pull-down
will determine the default input level of the strapping pins.
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or apply the host
MCUs GPIOs to control the voltage level of these pins when powering on ESP32.
After reset, the strapping pins work as the normal functions pins.
Note:
Firmware can configure register bits to change the setting of Voltage of Internal LDO (VDD_SDIO) and Timing of
SDIO Slave after booting.
The embedded flash operates at 1.8V. For the ESP32 series of chips that contain embedded flash, the MTDI/G-
PIO12 should be pulled high.
While the high level of integration makes the PCB design and layout process simple, the performance of the system
strongly depends on system design aspects. To achieve the best overall system performance, please follow the
guidelines specified in this document for circuit design and PCB layout. All the common rules associated with
good PCB design still apply and this document is not an exhaustive list of good design practices.
Any basic ESP32 circuit design may be broken down into seven major sections:
Power supply
Flash
Crystal oscillator
RF
External capacitors
Pin19 and Pin37 are the power supply pins for RTC and CPU, respectively. The digital power supply operates
in a voltage range of 1.8V ~ 3.6V. We recommend adding extra filter capacitors close to the digital power supply
pins.
The internal LDO of VDD_SDIO can be used as the power supply (1.8V or the same voltage as VDD3P3_RTC) for
the external circuitry, with a maximum current of about 40 mA. The user can add a 1F filter capacitor close to
VDD_SDIO. When VDD_SDIO is tied to VDD3P3_RTC, the LDO will be disabled.
Pin1, Pin43 and Pin46 are the analog power supply pins. Pin3 and Pin4 are the power supply pins for the power
amplifiers. It should be noted that the sudden increase in current draw, when ESP32 is in transmission mode,
may cause a power rail collapse. Therefore, it is highly recommended to add another 0603 10 F capacitor to the
power trace, which can work in conjunction with the 0402 0.1 F capacitor.
Notice:
The operating voltage for ESP32 ranges from 2.3V to 3.6V. When using a single power supply, the
recommended voltage of the power supply is 3.3V, and its recommended output current is 500 mA or
more.
ESP32 uses a 3.3V system power supply. The chip should be activated after the power rails have stabilized. This
is achieved by delaying the activation of CHIP_PU (Pin9) by time T after the 3.3V rails have been brought up. The
recommended delay time (T) is given by the parameter of the RC circuit. For reference design, please refer to
Figure ESP-WROOM-32 Peripheral Schematics in the ESP-WROOM-32 Datasheet.
Notice:
If CHIP_PU is driven by a power management chip, then the power management chip controls the
ESP32 power state. When the power management chip turns on/off Wi-Fi through the high/low level
on GPIO, a pulse current may be generated. To avoid level instability on CHIP_PU, an RC delay (R=10
k, C=100 nF) circuit is required.
3.1.2.2 Reset
CHIP_PU serves as the reset pin of ESP32. ESP32 will power off when CHIP_PU is held low and the input level is
below 0.6V and stays for at least 200 s. To avoid reboots caused by external interferences, the CHIP_PU trace
should be as short as possible and routed away from the clock lines. A pull-up resistor and a ground capacitor
are highly recommended.
Notice:
CHIP_PU pin must not be left floating.
3.1.3 Flash
ESP32 can support up to four 16 MB external QSPI flash and SRAM chips. The demo flash used currently is an SPI
flash with 4 MB ROM, in an SOIC-8 (SOP-8) package. The VDD_SDIO acts as the power supply pin. Make sure you
select the appropriate flash according to the power voltage on VDD_SDIO. Users can add a 0402 serial resistor
to Pin21 SD_CLK and connect it to the Flash CLK pin. The resistor can reduce drive current, thus minimizing
crosstalk and external interference. The resistor may also be used to tweak the bus timing and sequence.
The ESP32 Wi-Fi/BT firmware can only support 40 MHz crystal oscillator for now.
Notice:
Defects in the craftsmanship of the crystal oscillators (for example, high frequency deviation) and unsta-
ble operating temperature may lead to the malfunction of ESP32, resulting in a decrease of the overall
performance.
ESP32 supports an external 32 kHz crystal oscillator to act as the RTC sleep clock.
Notice:
If the RTC source is not required, then Pin12 32K_XP and Pin13 32K_XN can be used as digital GPIOs.
3.1.5 RF
In the circuit design, a -type matching network is essential for antenna matching.
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
The first layer is the TOP layer for signal traces and components.
The second layer is the GND layer without signal traces being routed so as to ensure a complete GND plane.
The third layer is the POWER layer. It is acceptable to route signal traces on this layer, provided that there is
a complete GND plane under the RF and crystal oscillator.
The fourth layer is the BOTTOM layer, where power traces are routed. Placing any components on this layer
is not recommended.
The 3.3V power traces are highlighted in yellow in Figure 13. The width of these power traces should be larger
than 20 mil. Before power traces reach the analog power-supply pins (Pin 1, 3, 4, 43, 46), a 0603 10 F capacitor
and a 0402 0.1 F capacitor are required. As Figure 13 shows, C13 (10 F capacitor) is placed by the 3.3V stamp
hole, and C10 is placed as close as possible to the analog power-supply pin.
It is good practice to route the power traces on the fourth (bottom) layer. Vias are required for the power traces to
go through the layers and get connected to the pins on the top layer. The diameter of the drill should exceed the
width of the power traces. The diameter of the via pad should be 1.5 times that of the drill.
For the design of the crystal oscillator section, please refer to Figure 14. In addition, the following should be
noted:
The crystal oscillator should be placed far from the clock pin. The recommended gap is 2.7 mm. It is good
practice to add high-density ground via stitching around the clock trace for containing the high-frequency
clock signal.
There should be no vias for the clock input and output traces, which means that the traces cannot cross
layers.
The external regulating capacitor should be placed on the near left or right side of the crystal oscillator and
at the end of the clock trace.
Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The larger the copper area on the top layer is, the better.
As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example, power-switching converter components or unshielded inductors.
3.2.1.4 RF
The characteristic RF impedance must be 50. The ground plane on the adjacent layer needs to be complete.
Make sure you keep the width of the RF trace consistent, and do not branch the trace. The RF trace should be
as short as possible with dense ground via stitching around it for isolation.
However, there should be no vias for the RF trace. The RF trace should be routed at a 135 angle, or with circular
arcs if trace bends are required.
-type matching circuitry should be reserved on the RF trace and placed close to the chip.
No high-frequency signal traces should be routed close to the RF trace. The RF antenna should be placed away
from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks (SDIO_CLK), etc.
The digital signals between the CPU and DDR are the main producers of the high-frequency noise that interferes
with Wi-Fi radio. Therefore, the following should be noted with regards to the PCB design.
As can be seen in Figure 16, ESP32 should be placed near the edge of the PCB and away from the CPU
and DDR, the main high-frequency noise sources. The distance between the chip and the noise sources
decreases the interference and reduces the coupled noise.
It is suggested that a 200 series resistor is added to the six signal traces when ESP32 communicates with
the CPU via SDIO to decrease the drive current and any interference, and also to eliminate the sequencing
problem caused by the inconsistent length of the SDIO traces.
On-board PCB antenna is not recommended, as it receives much interference and coupling noise, both of
which impact the RF performance. We suggest that you use an external antenna which should be directed
away from the PCB board via a cable, in order to weaken the high frequency interference with Wi-Fi.
The high-frequency signal traces between the CPU and associated memory should be routed strictly ac-
cording to the routing guidelines (please refer to the DDR trace routing guidelines). We recommend that you
add ground vias around the CLK traces separately, and around the parallel data or address buses.
The GND of the Wi-Fi circuit and that of other high-power devices should be separated and connected
through wires if there are high-power components, such as motors, in the design.
The antenna should be kept away from high-frequency noise sources, such as LCD, HDMI, Camera Sensor,
USB, etc.
Generally, the ripple should be <100 mV when ESP32 sends 11n MCS7 packets, and < 120 mV when ESP32
sends 11b 11m packets.
Solution:
Add a 10 F filter capacitor to the branch of the power trace (the branch powering the ESP32 analog power
pin). The 10 F capacitor should be as close to the analog power pin as possible for small and stable current
ripples.
Solution:
This problem is caused by improper layout and can be solved by re-layout. Please see Chapter 3.2 for de-
tails.
3.2.3.3 Q: When ESP32 sends data packages, the power value is much higher or lower than the target
power value, and the EVM is relatively poor.
Analysis:
The disparity between the tested value and the target value may be due to signal reflection caused by the impedance
mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance mismatch will
affect the working state of the internal PA, making the PA prematurely access the saturated region in an abnormal
way. The EVM becomes poor as the signal distortion happens.
Solution:
Match the antennas impedance with the reserved -type circuit on the RF trace, so that impedance of the antenna
as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.
Solution:
Keep the antenna away from crystal oscillators. Do not route high-frequency signal traces close to the RF trace.
High performance digital circuitry should be placed away from the RF block on large board designs. Please see
Chapter 3.2 for details.
4. Hardware Development
Note:
* For details on the part number of the ESP32 series, please refer to ESP32 Datasheet.
The size of the module is 180.2 mm x 25.50.2 mm x 2.80.15 mm. The flash used is in an SOP8-208 mil
package. The on-board PCB antenna has a gain of 2 dBi. Figure 18 shows the dimensions and pin layout of this
module.
18.000.2
6.00
Keepout Zone
1.500.1
1 GND GND 38
1.27
2 3V3 IO23 37
3 EN IO22 36
4 SENSOR_VP 4.000.1
TXD0 35
25.500.2
5 SENSOR_VN RXD0 34
6 IO34 IO21 33
6.300.2
7 IO35 NC 32
1:GND 4.000.1
8 IO32 IO19 31
9 IO33 IO18 30
10 IO25 IO5 29
11 IO26 IO17 28
12 IO27 7.300.2 IO16 27
13 IO14 IO4 26
CMD
IO15
SD0
GND
SD2
SD3
IO13
CLK
SD1
IO2
0.90 14 IO12 IO0 25
Unit: mm
20
24
22
23
18
16
19
21
15
17
0.45
0.800.1 PCB
25.500.2
Note:
There is a large ground pad on the bottom of ESP-WROOM-32 and it is recommended that users connect it to ground
for better heat dissipation.
Note:
* Pins SCK/CLK, SDO/SD0, SDI/SD1, SHD/SD2, SWP/SD3 and SCS/CMD, namely, GPIO6 to GPIO11 are connected
to the integrated SPI flash on ESP-WROOM-32 and are not recommended for other uses.
4.1.3 Notes
The module uses one single pin as the power supply pin. The user can connect the module to a 3.3V power
supply. The 3.3V power supply works both for the analog circuit and the digital circuit.
The EN pin is used for enabling the Wi-Fi functionality. Set the EN pin high for normal working mode.
The SMD Module features two working modes: the UART Download mode and the Flash Boot mode. In
the UART Download mode, firmware can be downloaded into the flash memory or the internal memory by
configuring the flash download tool. If the firmware is burnt into the internal memory, it can only run this time
when the module is powered on. Once the module is powered down, the internal memory will clear up.
However, if the firmware is burnt into the flash, it will be stored and can be recalled at any time.
Lead the GND RXD TXD pins out and connect them to a USB-to-TTL tool for firmware download, log-printing
and communication.
By default the initial firmware has already been downloaded in the flash. If users need to re-download the firmware,
they should follow the steps below:
3. Power on the module and check through the serial terminal if the UART Download mode is enabled.
4. Download the firmware to flash using the ESP Flash Download Tool.
5. After downloading, pull IO0 high to enable the SPI Boot mode.
6. Power on the module again. The chip will read and execute the firmware during initialization.
Notice:
During the whole process, users can check the status of the chip with the log printed through UART. If
the firmware cannot be downloaded or executed, users can check if the working mode is normal during
the chip initialization by looking at the log.
The serial tool cannot be opened for both the log-print and flash-download tools simultaneously.
Please download the ESP Flash Download Tool from Espressifs website: Flash Download Tool.
4.2 ESP32-DevKitC
4.2.1 Overview
ESP32-DevKitC is a low-footprint, minimal system development board which is powered by our latest ESP-
WROOM-32. The dimensions of the board are shown in Figure 19.
48.2 mm
18.0 mm 27.9 mm
55.0 mm
All pins of ESP-WROOM-32 are led out to the pin headers on both sides for easy interfacing. ESP32-DevKitC
features all the functions that are supported by ESP32. Users can connect these pins to peripherals as needed.
The interfaces are shown in Figure 20. For more details, please see Section 4.1.2 ESP-WROOM-32 Pin Defini-
tion.
3V3 GND
EN IO23
SVP IO22
SVN TXD0
IO34 RXD0
IO35 IO21
IO32 GND
IO33 IO19
IO25 IO18
IO26 IO5
IO27 IO17
IO14 IO16
IO12 IO4
GND IO0
IO13 IO2
SD2 IO15
SD3 SD1
CMD SD0
5V CLK
4.2.2 Schematics
4.2.2.1 Power Schematics
5. Applications
Support for multiple audio formats including WMA, ALAC, AAC, FLAC, OPUS, MP3, WAV, and OGG
Support for multiple wireless audio standards including DLNA, AirPlay and QPlay
Support for multiple cloud platforms including Ximalaya FM, YunOS and Amazon
Support for multiple distribution network protocols including ESP-TOUCH, ALINK, JoyLink3.0 and AirKiss