I) Xilinx ISE Simulator Quick Start Tutorial

Getting Started
For Windows users, start ISE from the Start menu by selecting:
1. Start _ Programs _ Xilinx ISE 14.5 _ Project Navigator
2. The ISE Project Navigator opens. The Project Navigator lets you manage the sources
and processes in your ISE project.
3. All of the tasks in the Quick Start Tutorial are managed from within Project
Navigator.

4. Another way to open the Xilinx is Double click on this shortcut

placed on desktop
Stopping and Restarting a Session
1. At any point during this tutorial you can stop your session and continue at a later time.
2. To stop the session:
a. Save all source files you have opened in other applications.
b. Exit the software (ISE and other applications).
3. The current status of the ISE project is maintained when exiting the software.
4. To restart your session, start the ISE software again. ISE displays the contents and
state of your project with the last saved changes.
Accessing Help
At any time during the tutorial, you can access online help for additional information
about a variety of topics and procedures in the ISE software as well as related tools.
1. To open Help you may do either of the following:
2. Press F1 to view Help for the specific tool or function that you have selected or
highlighted.
3. Launch the ISE Help Contents from the Help menu. It contains information about
creating and maintaining your complete design flow in ISE.
Creating a New Project in ISE
In this section, you will create a new ISE project. A project is a collection of all files
necessary to create and to download a design to a selected FPGA or CPLD device
To create a new project:
1. Select File > New Project. The New Project Wizard appears.
2. First, enter a location (directory path) for the new project.
3. Type the project name in the Project Name field. When you type project name in the
Project. When you give the project name you have to follow the rules are mentioned
below
a. The First letter should be alphabetic.
b. Don’t give space between the names. Instead of space
you can use underscore (_).
4. Name field, a project name subdirectory is created automatically in the directory path
you selected.
5. Select HDL from the Top-Level Module Type list, indicating that the top-level file in
your project will be HDL, rather than Schematic or EDIF.
6. Click Next to move to the project properties page.

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Fill in the properties in the table as shown below
Device Family: Automotive 9500XL
Device: Automotive xa9500xl
Package: *
Speed Grade: .*
Top-Level Module Type: HDL
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)

Fig.I.1 Device Properties for new project

Click Next to proceed to the Create New Source window in the New Project Wizard.
At the end of the next section, your new project will be created.
Creating an HDL Source
In this section, you will create a top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the
“Creating a VHDL Source” section below

1. This simple AND Gate design has two inputs: a and b. This design has one output
called c
2. Click New Source in the New Project Wizard to add one new source to your project.
3. Select VHDL Module as the source type in the New Source dialog box.
4. Type the file name (and gate) in that file name column.
5. Verify that the Add to project checkbox is selected.
6. Click Next.
7. Define the ports for your VHDL source.

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 Fig.I.2 selecting source type

Fig.I.3 Entities defining

 In the Port Name column, type the port names on three separate rows: a, b and c.
 In the Direction column, indicate whether each port is an input, output, or inout.
 For a, b select in from the list. For c select out from the list.

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 1. Click next in the Define VHDL Source dialog box.
2. Click Finish in the New Source Information dialog box to complete the new source
file template.
3. Click Next in the New Project Wizard.
4. Click Next again.
5. Click Finish in the New Project Information dialog box.
6. ISE creates and displays the new project in the Sources in Project window and adds
the andgate.vhd file to the project.
7. Double-click on the andgate.vhd file in the Sources in Project window to open the
VHDL file in the r.

The andgate.vhd file contains:

o Header information.
o Library declaration and use statements.
o Entity declaration for the counter and an empty
architecture statement.
1. In the header section, fill in the following fields:
Design Name: andgate.vhd
Project Name: and gate
Dependencies: None
Note: It is good design practice to fill in the header section in all source files.
2. Below the end process statement, enter the following line:
C <= A and B;
3. Save the file by selecting File > Save.

Checking the Syntax of the New Counter Module

When the source files are complete, the next step is to check the syntax of the design.
Syntax errors and typos can be found using this step.
i. Select the counter design source in the ISE Sources window to display the related
processes in the Processes for Source window.
ii. Click the “+” next to the Synthesize-XST process to expand the hierarchy.
iii. Double-click the Check Syntax process.
iv. When an ISE process completes, you will see a status indicator next to the process
name.
 If the process completed successfully, a green check mark appears.
 If there were errors and the process failed, a red X appears.
 A yellow exclamation point means that the process completed successfully, but
some warnings occurred.
 An orange question mark means the process is out of date and should be run
again.
v. Look in the Console tab of the Transcript window and read the output and status
messages produced by any process that you run.

Caution! You must correct any errors found in your source files. If you continue without
valid syntax, you will not be able to simulate or synthesize your design.

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 Fig.I.4 check syntax for VHDL program

After Completion Synthesize change the option Source for “Implementation” to

“Simulation”

Fig.I.5 Changing from Implementation to Simulation

• Click on the Project from menu bar and select “new source”.
• Then below mentioned table will appear in that select a Test Bench and
click on next.

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 Fig.I.6 Selecting Test bench

Fig.I.7 Finishing Test bench

Then Test bench program windows will appear. In that we have to remove the below
mentioned program line for no clock generation programs like Logic gates, decoders and
encoders, multiplexers, de-multiplexers.
Constant <clock>_period: Time: = 10 ns;

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 -- Clock process definitions
<Clock>_process: process
Begin
<Clock> <= '0';
Wait for <clock>_period/2;
<Clock> <= '1';
Wait for <clock>_period/2;
End process;
There no changes in clock generation lines in test bench when a clock is present as
inputs (for flip flops and counters & registers).For clock as input the clock process definition
is
-- Clock period definitions
constant clk1_period : time := 100 ns;
-- Clock process definitions
clk1_process :process
begin
clk1 <= '0';
wait for clk1_period/2;
clk1 <= '1';
wait for clk1_period/2;
end process;

Fig.I.8 Removing constant clock period from Test bench program

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 Fig.I.8 Removing clock process definition from Test bench program

After removing the clock process definition and constant clock period we have to write a
below mentioned small logic in a process to generate the time wave forms for given input
variables.

stim_proc: process—Process Name

--Input Variable declarations
begin
a<='1';b<='1';
wait for 100 ns;
a<='0';b<='1';
wait for 100 ns;
a<='1';b<='0';
wait for 100 ns;
a<='0';b<='0';
wait for 100 ns;

End process;--Process Ending

We have to give just assign the input values in the test bench as we mentioned in the VLSI
code. No need to rewrite the logic once again in the test bench.

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 Fig.I.10 Writing a logic to generate time period values for input variables

i. After that we have to double click on the “Behavioral Check Syntax” for checking
any errors in test bench program.
ii. If there are no errors in the program then it shows a Tick mark (√) in green colour.
iii. If there are any errors in the program then it shows a cross mark(X) with red colour.
iv. Then we have to check the where the errors are placed in the program and correct it.
v. After completion check syntax we have to double click on the Simulate Behavior
Model then the output wave form will generated
vi. Then a new window will appear in that output wave forms are appearing.
vii. To view the full wave forms then click on the zoom to full view option as shown in
the picture below.

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 Fig.I.11 Output Wave form for given test bench

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 1) REALIZATION OF LOGIC GATES
1.1 Aim: - To write a Verilog HDL code for all logic gate’s and simulate the code to verify
the output

1.2 Apparatus:-
1. Personal computer
2. Xilinx ISE Simulator
1.3 Theory:-
1.3.1 AND Gate:
 A Logic AND Gate is a type of digital logic gate that has an output which is normally
at logic level "0" and only goes "HIGH" to a logic level "1" when ALL of its inputs
are at logic level "1".
 The output of a Logic AND Gate only returns "LOW" again when ANY of its inputs
are at a logic level "0".
 The logic or Boolean expression given for a logic AND gate is that for Logical
Multiplication which is denoted by a single dot or full stop symbol, (.) giving us the
Boolean expression of: C =A.B

1.3.2 OR Gate:
 A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an
output which is normally at logic level "0" and only goes "HIGH" to a logic level "1"
when one or more of its inputs are at logic level "1".
 The output, of a Logic OR Gate only returns "LOW" again when ALL of its inputs
are at a logic level "0".
 The logic or Boolean expression given for a logic OR gate is that for Logical Addition
which is denoted by a plus sign, (+) giving us the Boolean expression of: C = A+B .

1.3.3 NOT Gate:

 The digital Logic NOT Gate is the most basic of all the logical gates and is
sometimes referred to as an Inverting Buffer or simply a Digital Inverter.
 It is a single input device which has an output level that is normally at logic level "1"
and goes "LOW" to a logic level "0" when its single input is at logic level "1", in
other words it "inverts" (complements) its input signal.
 The output from a NOT gate only returns "HIGH" again when its input is at logic
level "0" giving us the Boolean expression of: C = A` .

1.3.3 NAND Gate:

 The Logic NAND Gate is a combination of the digital logic AND gate with that of an
inverter or NOT gate connected together in series.
 The NAND (Not - AND) gate has an output that is normally at logic level "1" and
only goes "LOW" to logic level "0" when ALL of its inputs are at logic level "1".
 The Logic NAND Gate is the reverse or "Complementary" form of the AND gate we
have seen previously.

1.3.4 NOR Gate:

 The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic OR
gate with that of an inverter or NOT gate connected together in series.

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  The NOR (Not - OR) gate has an output that is normally at logic level "1" and only
goes "LOW" to logic level "0" when ANY of its inputs are at logic level "1".
 The Logic NOR Gate is the reverse or "Complementary" form of the OR gate we
have seen previously.

1.3.5 XOR Gate:

 The Exclusive-OR Gate function or Ex-OR, if A = "1", OR B = "1", then the output
from the digital gate must also be at a logic level "1" and because of this, this type of
logic gate is known as an exclusive-OR function.
 If the two inputs are equal, then the output will be “0”.

1.3.6 XNOR Gate:

 The Exclusive-NOR Gate function or Ex-NOR for short, is a digital logic gate that is
the reverse or complementary form of the Exclusive-OR.
 The Exclusive-NOR gate is a combination of the Exclusive-OR gate and the NOT
gate.
 It has an output that is normally at logic level "0" when ANY of its inputs are at logic
level "1".

1.4 Logic Gate Symbols:

Fig.1.1 Logic gate symbol

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1.5 Pin Diagrams of all logic gates:

Fig.1.2 Logic gate IC Pin Diagrams

1.6 Truth Table of all logic gates:-

Tab 1.1 All Logic gates Truth Tabel

INPUT OUTPUT
A B AND OR NOT NAND NOR XOR XNOR
A B
0 0 0 1 1 1 1 0 0 1
0 1 0 0 1 0 1 1 1 0
1 0 0 0 0 1 1 1 1 0
1 1 1 0 0 0 0 1 0 1

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1.7 Verilog HDL Code for All Logic Gates :-

module logic_gates( input a,b,

output and_gate,
or_gate,
not_gate,
nand_gate,
nor_gate,
xor_gate,
xnor_gate);

and n1(and_gate,a,b);
or n2(or_gate,a,b);
not n3(not_gate,a);
nand n4(nand_gate,a,b);
nor n5(nor_gate,a,b);
xor n6(xor_gate,a,b);
xnor n7(xnor_gate,a,b);

endmodule

1.8 Verilog HDL Code for All Logic Gates using assign:-

module logic_gates_assign( input a,b,

output and_gate,
or_gate,
not_gate,
nand_gate,
nor_gate,
xor_gate,
xnor_gate);

assign and_gate = a & b;

assign or_gate = a | b;
assign not_gate = ~a ;
assign nand_gate = ~(a & b);
assign nor_gate = ~(a | b);
assign xor_gate = a ^ b;
assign xnor_gate = a ~^ b;

endmodule

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1.9 VHDL Test Bench Code for All Logic Gates:
module assign_tb;

// Inputs
reg a;
reg b;
// Outputs
wire and_gate;
wire or_gate;
wire not_gate;
wire nand_gate;
wire nor_gate;
wire xor_gate;
wire xnor_gate;
// Instantiate the Unit Under Test (UUT)
logic_gates_assign uut (
.a(a),
.b(b),
.and_gate(and_gate),
.or_gate(or_gate),
.not_gate(not_gate),
.nand_gate(nand_gate),
.nor_gate(nor_gate),
.xor_gate(xor_gate),
.xnor_gate(xnor_gate)
);
initial begin
#100 a = 1'b0;b = 1'b0;
#100 a = 1'b0;b = 1'b1;
#100 a = 1'b1;b = 1'b0;
#100 a = 1'b1;b = 1'b1;
end
endmodule

1.10 Output Waveform:-

Fig.1.3 All Logic Gates gate output Waveform

1.11 Result:-

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 The Verilog HDL code for all logic gates are simulated and the waveforms are
verified

1.12 VIVA Questions:

1. Implement the following function using VHDL coding (Try to minimize if you can)
F (A, B, C, D) = (A`+B+C). (A+B` +D`). (B+C` +D`). (A+B+C +D).
2. What will be the no. of rows in the truth table of N variables?
3. What are the advantages of VHDL?
4. Design XOR gate using behavioral model?
5. Implement the following function using VHDL code f=AB+CD.
6. What are the differences between half adder and full adder?
7. What are the advantages of minimizing the logical expressions?
8. What does a combinational circuit mean?

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 2)3 to 8 DECODER- 74138
2.1 Aim: - To Write a VHDL code and to Simulate 3-to-8 Decoder (IC-74138).

2.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
2.3 Theory:-
 The 74138 is commercially available 3-to-8 decoder.\
 It accepts three binary inputs (A, B, C) and when enabled, provides 8 individual
active low outputs (Y0-Y7).
 The device has 3-enable inputs: two active low (G2A, G2B) and one active high (G1).
 Here 3 inputs are decoded into outputs, when enabled.
 Each output represent one of the minterms of the 3-input variables.

2.4 Logic Diagram of 3-to-8 Decoder:-

Fig.2.1 Logic Diagram of 3x8 Decoder

2.4 Pin Diagram of 3-to-8 Decoder IC74X138:-

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 Fig.2.2 3-to-8 Decoder(IC74X138) Pin diagram

2.5 Truth Table of 3-to-8 Decoder:

Table.2.1 Decoder truth table
Enable Inputs Enable Outputs Decoded

S.No g1 g2a-1 g2b-1 A B C Output

1 0 X X X X X 11111111

2 1 1 X X X X 11111111

3 1 X 1 X X X 11111111

4 1 0 0 0 0 0 01111111

5 1 0 0 0 0 1 10111111

6 1 0 0 0 1 0 11011111

7 1 0 0 0 1 1 11101111

8 1 0 0 1 0 0 11110111

9 1 0 0 1 0 1 11111011

10 1 0 0 1 1 0 11111101

11 1 0 0 1 1 1 11111110

2.6 VHDL Code for 3x8 Decoder:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder3X8 is
port (g1, g2a_1, g2b_1 : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0);
y_l : out STD_LOGIC_VECTOR (0 to 7));
end decoder3X8;
architecture behavioral of decoder3X8 is
begin
process (a,g1,g2a_1,g2b_1)
begin
if (g1 and not g2a_1 and not g2b_1)='1'then
if a <= "000"then y_l<= "01111111";
elsif a <= "001"then y_l <= "10111111";
elsif a <= "010"then y_l<= "11011111";
elsif a <= "011"then y_l <= "11101111";
elsif a <= "100"then y_l <= "11110111";

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 elsif a <= "101"then y_l <= "11111011";
elsif a <= "110"then y_l <= "11111101";
elsif a <= "111"then y_l <= "11111110";
else y_l<= "11111111";
end if;
else y_l <= "11111111";
end if;
end process;
end behavioral;

2.7 VHDL Test Bench Code for 3x8 Decoder:

library ieee;
use ieee.std_logic_1164.all;

entity decoder_test is
end decoder_test;

architecture behavior of decoder_test is

-- component declaration for the unit under test (uut)

component decoder_prg
port(a : in std_logic_vector(0 to 2);
g1 : in std_logic;
g2a : in std_logic;
g2b : in std_logic;
y : out std_logic_vector(0 to 7));
end component;
--inputs
signal a:std_logic_vector(0 to 2):=(others =>'0');
signal g1 : std_logic := '0';
signal g2a : std_logic := '0';
signal g2b : std_logic := '0';

--outputs
signal y : std_logic_vector(0 to 7);
begin
-- instantiate the unit under test (uut)
uut: decoder_prg port map (
a => a,
g1 => g1,
g2a=> g2a,
g2b=> g2b,
y => y);
-- stimulus process
stim_proc: process
begin
g1<='1';g2a<='1';g2b<='1';
wait for 100ns;
g1<='1';g2a<='0';g2b<='0';

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 a<="000";
wait for 100ns;
a<="001";
wait for 100ns;
a<="010";
wait for 100ns;
a<="011";
wait for 100ns;
a<="100";
wait for 100ns;
a<="101";
wait for 100ns;
a<="110";
wait for 100ns;
a<="111";
wait for 100ns;
end process;
end;
2.8 Output Waveform:-

Fig.2.3 Decoder output waveform

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2.9 Result:-

VHDL code for 3 to 8 decoder 74138 in behavioral style is written and simulated
using Xilinx 14.5 version and output is observed

2.10 VIVA Questions:

1. Write the behavioral code for the IC 74x138.

2. Write the VHDL code for the IC 74x138 using CASE statement.
3. Write the VHDL code for the IC 74x138 using WITH statement.
4. Write the VHDL code for the IC 74x138 using WHEN--ELSE statement.
5. Write the structural program for IC 74x138.
6. What does priority encoder mean?
7. How many decoders are needed to construct 4X16 decoder?
8. What is the difference between decoder and encoder?
9. Write the syntax for exit statement?
10. Explain briefly about next statement?
11. How to specify the delay in VHDL program?

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 3) 8x1 Multiplexer-74151 & 2-Line to 4-Line Demultiplexer-74155
3.1) 8x1 Multiplexer-74151
3.1.1 Aim: To Write a VHDL code and to Simulate 8 x 1 Multiplexer (74x151)
3.1.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
3.1.3 Theory:-
 The 74151 is a 8-to-1 Multiplexer.
 It has 8 inputs and it provides 2 outputs, one is active high, the other one is active low.
It has 3 selection inputs C, B and A which select one of the 8 inputs.
 The 74151 is provided with active low enable input.
 In this for each input combinations output is not specified in 1s and 0s.
 Multiplexer is a data switch, it does not generate any data of its own, but it simply
passes external input data from selected input to the output.

3.1.3 Logic Diagram of 8-to-1 Multiplexer:-

Fig.3.1.1 8x1 Multiplexer Logic diagram

3.1.4 Pin Diagram of 8-to-1

Multiplexer IC74151:

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 Fig.3.1.2 Pin diagram Multiplexer(IC 74151)

3.1.5 Truth Table of 8-to-1 Multiplexer:-

Table.3.3.1 Multiplexer truth table

INPUT OUTPUT
SELECTION ENABLE Y W
A B C E
X X X 1 X X
0 0 0 0 D0 D0
0 0 1 0 D1 D1
0 1 0 0 D2 D2
0 1 1 0 D3 D3
1 0 0 0 D4 D4
1 0 1 0 D5 D5
1 1 0 0 D6 D6
1 1 1 0 D7 D7

3.1.6 VHDL Code for Multiplexer-74151:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux151 is
port (I :in STD_LOGIC_VECTOR (7 downto 0);
S :in STD_LOGIC_VECTOR (2 downto 0);
en_l:in STD_LOGIC;
y :inout STD_LOGIC;
ybar :out STD_LOGIC);
end mux151;

architecture mux151 of mux151 is

begin
process (D,s,en_l)
begin
if en_l='0' then
case s is
when "000" => y <= D(0);
when "001" => y <= D(1);
when "010" => y <= D(2);
when "011" => y <= D(3);
when "100" => y <= D(4);

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 when "101" => y <= D(5);
when "110" => y <= D(6);
when "111" => y <= D(7);
when others=>null;
end case;
else y <= '0';
end if;
end process;
ybar<= not y;
end mux151;

3.1.7 VHDL Test Bench Code for 8-to1-Multiplexer_74151:-

library ieee;
use ieee.std_logic_1164.all;

entity mux8x1_tb is
end mux8x1_tb;

architecture behavior of mux8x1_tb is

--component declaration for the unit under test (uut)

component mux151
port( d : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
en : in std_logic;
y : inout std_logic;
w : out std_logic);
end component;
--inputs
signal d:std_logic_vector(7 downto 0):=(others=>'0');
signal s:std_logic_vector(2 downto 0):=(others=>'0');
signal en : std_logic := '1';

--bidirs
signal y : std_logic;
--outputs
signal w : std_logic;

begin
-- instantiate the unit under test (uut)
uut: mux151 port map (
d => d,
s => s,
en => en,
y => y,
w => w);

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 -- stimulus process
stim_proc: process
begin
wait for 100 ns;
en<='0';d<="01010101";
s<="000";
wait for 100 ns;
s<="001";
wait for 100 ns;
s<="010";
wait for 100 ns;
s<="011";
wait for 100 ns;
s<="100";
wait for 100 ns;
s<="101";
wait for 100 ns;
s<="110";
wait for 100 ns;
s<="111";
wait for 100 ns;
wait;
end process;
end;

3.1.8 Output Waveform:-

Fig.3.1.3 Multiplexer output Waveform

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3.1.9 Result:-

VHDL code for 8x1 multiplexer 74151 in behavioral style is written and simulated
using Xilinx 14.5 version and output is observed

3.2)2-Lines to 4-Line Demultiplexer-74155

3.2.1 Aim: To Write a VHDL code and to Simulate 2-line to 4-line Demultiplexer-74155

3.2.2 Apparatus:-

1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
3.2.3 Theory:-
 The 74155 is dual 1-line-to-4-line de-multiplexers with individual strobes.
 When both sections are enabled by the strobes, the common binary address inputs
sequentially select and route associated input data to the appropriate output of each
section.
 The individual strobes permit activating or inhibiting each of the 4-bit sections is
desired.

3.2.4 Logic Diagram of 2-line to 4-line De-multiplexer-(IC74155):-

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 Fig.3.2.1 Logic diagram of de-multiplexer

3.2.5 Pin Diagram of 2-line to 4-line De-multiplexer (IC -74155):-

Fig.3.2.2 Pin diagram of de-multiplexer (IC74155)

3.2.6 Truth Table of 2-line to 4-line Demultiplexer-74155:-

Table.3.2.1 De-Multiplexer truth table

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3.2.7 VHDL Code for 2-line to 4-line Demultiplexer-74155:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux is
port( c1, c2: in std_logic;
g1_l, g2_l: in std_logic;
sel: in std_logic_vector(1 downto 0);
y1, y2: out std_logic_vector(3 downto 0));
end demux;
architecture demux of demux is
begin
process( c1, c2, g1_l, g2_l, sel)
begin
y1 <= "1111"; y2<= "1111";
if( g1_l = '0') then
case sel is
when "00" => y1(0) <= c1;
when "01" => y1(1) <= c1;
when "10" => y1(2) <= c1;
when "11" => y1(3) <= c1;

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 when others=> null;
end case;
end if;
if( g2_l = '0') then
case sel is
when "00" => y2(0) <=c2;
when "01" => y2(1) <=c2;
when "10" => y2(2) <=c2;
when "11" => y2(3) <=c2;
when others=> null;
end case;
end if;
end process;
end demux;

3.2.8 VHDL Test Bench Code for 2-line to 4-line Demultiplexer-74155:-

library ieee;
use ieee.std_logic_1164.all;

entity demux_tb is
end demux_tb;

architecture behavior of demux_tb is

-- component declaration for the unit under test (uut)
component demux
port(c1 : in std_logic;
c2 : in std_logic;
g1_l : in std_logic;
g2_l : in std_logic;
sel : in std_logic_vector(1 downto 0);
y1 : out std_logic_vector(3 downto 0);
y2 : out std_logic_vector(3 downto 0)
);
end component;

--inputs
signal c1 : std_logic := '0';
signal c2 : std_logic := '1';
signal g1_l : std_logic := '0';
signal g2_l : std_logic := '1';
signal sel :std_logic_vector(1 downto 0):= (others => '0');

--outputs
signal y1 : std_logic_vector(3 downto 0);
signal y2 : std_logic_vector(3 downto 0);

begin

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 -- instantiate the unit under test (uut)
uut: demux port map (
c1 => c1,
c2 => c2,
g1_l => g1_l,
g2_l => g2_l,
sel => sel,
y1 => y1,
y2 => y2
);

-- stimulus process
stim_proc: process
begin
c1<='1';c2<='0';
g1_l<='1';g2_l<='0';
wait for 500 ns;
c1<='0';c2<='1';
g1_l<='0';g2_l<='1';
wait for 500 ns;
end process;
sel_pro: process
begin
sel<="00";
wait for 100 ns;
sel<="01";
wait for 100 ns;
sel<="10";
wait for 100 ns;
sel<="11";
wait for 100 ns;
end process;

end;

3.2.9 Output Waveform:-

Fig.3.2.3 De-Multiplexer Output Waveform

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3.2.10 Result:-
VHDL code for 2-line to 4-line demux 74155 in behavioral style is written and
simulated using Xilinx 14.5 version and output is observed

3.2.11 VIVA Questions:

1. Write the behavioral code for the IC 74x151.
2. Write the VHDL code for the IC 74x151 using IF statement.
3. Write the VHDL code for the IC 74x151 using WITH statement.
4. Write the VHDL code for the IC 74x151 using WHEN--ELSE statement.
5. Write the structural program for IC 74x151.
6. Implement 16X1 multiplexer using structural model
7. Write the applications of multiplexer and de-multiplexer?
8. Explain the execution steps of subprogram?
9. Write the syntax of package declaration & package body

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 4) 4-BIT COMPARATOR(IC 74x85)
4.1 Aim: - To Write a VHDL code and to Simulate 4-Bit Comparator (IC74x85).
4.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
4.3 Theory:-
 These 4-bit magnitude comparators perform comparison of straight binary or BCD
codes.
 Three fully-decoded decisions about two, 4-bit words (A, B) are made and are
externally available at three outputs.
 These devices are fully expandable to any number of bits without external gates.
Words of greater length may be compared by connecting comparators in cascade.
 The A < B, A > B, and A = B outputs of a stage handling less-significant bits are
connected to the corresponding inputs of the next stage handling more-significant bits.
 The stage handling the least-significant bits must have a high-level voltage applied to
the A = B input.

4.4 Logic Diagram of 4-Bit Comparator:-

Fig.4.1 4-Bit Comparator

4.5 Truth Table of 4-Bit Comparator:

Table 4.1 Comparator truth table

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4.6 Logic Diagram of IC 74X85:-

Fig.4.1 Comparator(IC 74X85) Pin diagram

4.7 VHDL Code for 4-Bit Comparator (7485):-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp is
port (altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a,b:in STD_LOGIC_VECTOR(3downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC);
end comp;
architecture comp of comp is
begin

process(a,b,agtbin,aeqbin,altbin)

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 begin
agtbout<='0';
aeqbout<='0';
altbout<='0';
if aeqbin='1' then
if a=b then
aeqbout<='1';
elsif (a>b) then
agtbout<='1';
elsif (a<b) then
altbout<='1';
end if;
end if;
end process ;
end Comp;

4.8 VHDL Test Bench Code for 4-Bit Comparator (7485):-

library ieee;
use ieee.std_logic_1164.all;

entity compr_tb is
end compr_tb;

architecture behavior of compr_tb is

component comp
port( altbin : in std_logic;
aeqbin : in std_logic;
agtbin : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
agtbout : out std_logic;
aeqbout : out std_logic;
altbout : out std_logic);
end component;

--inputs
signal altbin : std_logic := '1';
signal aeqbin : std_logic := '1';
signal agtbin : std_logic := '1';
signal a :std_logic_vector (3 downto 0):= (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');

--outputs
signal agtbout : std_logic;
signal aeqbout : std_logic;
signal altbout : std_logic;

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 begin
-- instantiate the unit under test (uut)

uut: comp port map (altbin => altbin,

aeqbin => aeqbin,
agtbin => agtbin,
a => a,
b => b,
agtbout => agtbout,
aeqbout => aeqbout,
altbout => altbout);
-- stimulus process
stim_proc: process
begin
a<="1111";b<="0101";
wait for 100 ns;
a<="0000";b<="0101";
wait for 100 ns;
a<="0100";b<="0100";
wait for 100 ns;
a<="1010";b<="1000";
wait for 100 ns;
a<="1000";b<="0101";
wait for 100 ns;
a<="1000";b<="1000";
wait for 100 ns;
altbin <='0';
aeqbin <='0';
agtbin <='0';
wait;
end process;
end;

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4.9 Output Waveform:-

Fig.4.3 Comparator output waveform

4.10 Result:-

VHDL code for 4bit comparator 74x85 in behavioral style is written and simulated
using Xilinx 14.5 version and output is observed

4.11 VIVA Questions:

1. Write the dataflow model for the IC 74x85.
2. Write the VHDL code for the IC 74x85 using CASE statement.
3. Write the VHDL code for the IC 74x85 using WITH statement.
4. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement.
5. Write the structural program for IC 74x85.
6. How many 4-bit comparators are needed to construct 12-bit comparator?
7. What does a digital comparator mean?
8. Design a 2-bit comparator using gates?
9. Explain the phases of a simulation?
10. Explain briefly about wait statement?
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 5) D FLIP FLOP (IC7474)

5.1 Aim: - To Write a VHDL code D Flip- Flop IC7474

5.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
5.3 Theory:-
 This device contains two independent positive-edge-triggered D-type flip-flops
 A low level at the preset or clear inputs set or resets the output regardless of the levels
of the other inputs.
 When preset and clear are inactive, data at the D flip-flop inputare transferred to the
output on the positive going edge of the clock pulse.

5.4 Logic Diagram of D-Flip flop:-

Fig.5.1 D-flip flop Block diagram

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5.5 Pin diagram of IC7474:

Fig.5.2 D-flip flop (7474) Pin Diagram

5.6 Truth Table of D-flip flop:-

Table.5.1 D-flip flop truth table

5.7 VHDL Code for D-Flip Flop(IC 7474):-

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff7474 is
Port (clk1,clk2: in STD_LOGIC;
clr_l1,clr_l2: in STD_LOGIC;
pr_l1,pr_l2: in STD_LOGIC;
d1,d2: in STD_LOGIC;
q1,qbar1: out STD_LOGIC;
q2,qbar2 : out STD_LOGIC);
end dff7474;
architecture Behavioral of dff7474 is
begin
p1: process (clk1, clr_l1, pr_l1, d1)
begin
if (pr_l1 ='0' and clr_l1 ='0') then
q1<= '1'; qbar1 <= '1';
elsif (pr_l1 = '0') then
q1<= '1'; qbar1 <= '0';
elsif (clr_l1 = '0') then

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 q1<= '0'; qbar1 <= '1';
elsif(pr_l1 ='1' and clr_l1 ='1'and(clk1'event and clk1 ='1'))
then
q1<= d1; qbar1 <= not d1;
end if;
end process;

p2: process (clk2, clr_l2, pr_l2, d2)

begin
if (pr_l2 ='0' and clr_l2 ='0') then
q2<= '1'; qbar2 <= '1';
elsif (pr_l2 = '0') then
q2<= '1'; qbar2 <= '0';
elsif (clr_l2 = '0') then
q2<= '0'; qbar2 <= '1';
elsif(pr_l2 ='1' and clr_l2 ='1' and(clk2'event and clk2=
'1')) then
q2<= d2; qbar2 <= not d2;
end if;
end process;
end Behavioral;

5.8 VHDL Test Bench Code for D-Flip Flop:-

library ieee;
use ieee.std_logic_1164.all;

entity tb_2 is
end tb_2;

architecture behavior of tb_2 is

-- component declaration for the unit under test (uut)

component dff7474
port(clk1 : in std_logic;
clk2 : in std_logic;
clr_l1 : in std_logic;
clr_l2 : in std_logic;
pr_l1 : in std_logic;
pr_l2 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
q1 : out std_logic;
qbar1 : out std_logic;
q2 : out std_logic;
qbar2 : out std_logic);
end component;

--inputs

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 signal clk1 : std_logic := '0';
signal clk2 : std_logic := '0';
signal clr_l1 : std_logic := '0';
signal clr_l2 : std_logic := '0';
signal pr_l1 : std_logic := '0';
signal pr_l2 : std_logic := '0';
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';

--outputs
signal q1 : std_logic;
signal qbar1 : std_logic;
signal q2 : std_logic;
signal qbar2 : std_logic;

-- clock period definitions

constant clk1_period : time := 50 ns;
constant clk2_period : time := 100 ns;

begin

-- instantiate the unit under test (uut)

uut: dff7474 port map (
clk1 => clk1,
clk2 => clk2,
clr_l1 => clr_l1,
clr_l2 => clr_l2,
pr_l1 => pr_l1,
pr_l2 => pr_l2,
d1 => d1,
d2 => d2,
q1 => q1,
qbar1 => qbar1,
q2 => q2,
qbar2 => qbar2);

-- clock process definitions

clk1_process :process
begin
clk1 <= '1';
wait for clk1_period/2;
clk1 <= '0';
wait for clk1_period/2;
end process;

clk2_process :process
begin
clk2 <= '1';
wait for clk2_period/2;

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 clk2 <= '0';
wait for clk2_period/2;
end process;

-- stimulus process
data_proc: process
begin
d1<='1','0' after 500 ns;
wait for 500 ns;
d2<='1','0' after 500 ns;
wait for 500 ns;
end process;

clear_proc: process
begin
clr_l1<='1','0' after 250 ns;
wait for 250 ns;
clr_l2<='1','0' after 250 ns;
wait for 250 ns;
end process;

preset_proc: process
begin
pr_l1<='1','0' after 250 ns;
wait for 250 ns;
pr_l2<='1','0' after 250 ns;
wait for 250 ns;
end process;
end;

5.9 Output Waveform:-

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 .

Fig.5.3 D-flip flop output waveform

5.10 Result:-
VHDL code for D-flip flop- 7474 in behavioral style is written and simulated using
Xilinx 14.5 version and output is observed

5.11 VIVA QUESTIONS:

1. Write the dataflow code for the IC 74x74.

2. What is the difference between sequential and combinational circuit?
3. What is a flip-flop?
4. Explain the functions of preset and clear inputs in flip-flop?
5. What is meant by a clocked flip-flop?
6. What is meant by excitation table?
7. What is the difference between flip-flop and latch?
8. What are the various methods used for triggering flip-flops?
9. Explain level triggered flip-flop?

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 6) DECADE COUNTER(IC 74x90)
6.1 Aim: - To Write a VHDL code and to Simulate decade counter(IC 74x90).

6.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
6.3 Theory:
 Each of these monolithic counters contains four master slave flip-flops and additional
gating to provide a divide-by two counter and a three-stage binary counter for which
the count cycle length is divide-by-five for the DM74LS90.
 All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-
nine inputs for use in BCD nine’s complement applications.
 To use their maximum count length (decade or four bit binary), the B input is
connected to the QA output.
 The input count pulses are applied to input A and the outputs are as described in the
appropriate truth table.
 A symmetrical divide-by-ten count can be obtained from the DM74LS90 counters by
connecting the QD output to the A input and applying the input count to the B input
which gives a divide-by-ten square wave at output QA.

6.4 Logic Diagram of Decade Counter:-

Fig.6.1 Logic diagram of Decade Counter

6.5 Pin Diagram of IC7490:-

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 Fig.6.2 IC 7490 Pin Diagram

6.6 Truth Table:-

Table.6.1Truth table of decade counter

6.7 VHDL Code for Decade Counter(IC7490):-

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dec_counter is
port (clk : in std_logic;
r0_1,r0_2: in std_logic;
r9_1,r9_2 : in std_logic;
q : out std_logic_vector (3 downto 0));
end dec_counter;

architecture behavioral of dec_counter is

signal count: std_logic_vector (3 downto 0);
begin
process (clk,r0_1,r0_2,r9_1,r9_2, count)
begin
if (r0_1 and r0_2)= '1' then
count <= "0000";
elsif (r9_1 and r9_2)= '1' then
count <= "1001";
elsif (clk'event and clk = '0') then
count <= count + 1;
if (count=9)then count <="0000";
end if;
end if;

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 q <= count;
end process;
end behavioral;

6.8 VHDL Test Bench Code for Decade Counter:

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is

-- component declaration for the unit under test (uut)

component dec_counter
port(
clk : in std_logic;
r0_1 : in std_logic;
r0_2 : in std_logic;
r9_1 : in std_logic;
r9_2 : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end component;

--inputs
signal clk : std_logic := '1';
signal r0_1 : std_logic := '1';
signal r0_2 : std_logic := '0';
signal r9_1 : std_logic := '1';
signal r9_2 : std_logic := '0';

--outputs
signal q : std_logic_vector(3 downto 0);

-- clock period definitions

constant clk_period : time := 50 ns;

begin

-- instantiate the unit under test (uut)

uut: dec_counter port map (
clk => clk,
r0_1 => r0_1,
r0_2 => r0_2,
r9_1 => r9_1,
r9_2 => r9_2,
q => q
);

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 -- clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- stimulus process
stim_proc: process
begin
r0_1<='0';r0_2<='0';r9_1<='1';r9_2<='1';
wait for 100 ns;
r0_1<='1';r0_2<='1';r9_1<='0';r9_2<='0';
wait for 100 ns;
r0_1<='0';r0_2<='1';r9_1<='0';r9_2<='0';
wait ;
end process;

end;
6.9 Output Waveform:-

Fig.6.3 Decade counter output Waveform

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6.10 Result:-
VHDL code for decode counter (IC 74x09) in behavioral style is written and
simulated using Xilinx 14.5 version and output is observed

6.11 VIVA Questions:-

1. What is a counter?
2. What are the asynchronous inputs?
3. To restrict the count value of a counter, if takes the help of inputs.
4. To restrict the count value of a counter, if takes the help of inputs
5. Define mod up counter
6. Define mod up counter
7. Difference between mod up counter and mod up counter

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 7)4 -BIT BINARY COUNTER (IC 7493)
7.1 Aim: - To Write a VHDL code and to Simulate 4 -bit binary counter(IC 74x93).
7.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
7.3 Theory:-

 The counter contains four master slave flip-flops and additional gating to provide a
divide-by two counter and a three-stage binary counter for which the count cycle
length is divide-by-eight for the 93A.
 All of these counters have a gated zero reset.
 To use their maximum count length (decade or four-bit binary), the B input is
connected to the QA output.
 The input count pulses are applied to input A and the outputs are as described in the
appropriate truth table.
 A symmetrical divide-by-ten count can be obtained from the 90A counters by
connecting the QD output to the A input and applying the input count to the B input
which gives a divide-by-ten square wave at output QA.

7.4 Logic Diagram of Binary Counter:-

Fig.7.1Binary counter Logic diagram

7.5 Truth Table of Binary Counter:

Table.7.1 Truth table for binary counter

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7.6Pin diagram of IC-7493:-

Fig.7.2Binary Counter(7493) Pin Diagram

7.7 VHDL Code for 4-Bit Binary Counter:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity counter is
Port ( r0_1,r0_2,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is

signal count: STD_LOGIC_VECTOR (3 downto 0);
begin

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 process (r0_1, r0_2, clk, count)
begin
if (r0_1 = '1' and r0_2 = '1') then
count <= "0000";
elsif (clk'event and clk = '1') then
if (r0_1 = '0') then
count <= count + 1;
elsif (r0_2 = '0') then
count <= count + 1;
end if;
end if;
q <= count;
end process;
end Behavioral;

7.8 VHDL Test Bench Code for 4-Bit Binary Counter:

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;
architecture behavior of tb is

-- component declaration for the unit under test(uut)

component counter
port( r0_1 : in std_logic;
r0_2 : in std_logic;
clk : in std_logic;
q : out std_logic_vector(3 downto 0));
end component;

--inputs
signal r0_1 : std_logic := '1';
signal r0_2 : std_logic := '1';
signal clk : std_logic := '0';
--outputs
signal q : std_logic_vector(3 downto 0);
--clock period definitions
constant clk_period : time := 50 ns;
begin
-- instantiate the unit under test (uut)
uut: counter
port map (r0_1 => r0_1,
r0_2 => r0_2,
clk => clk,
q => q);
-- clock process definitions
clk_process :process

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 begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;

-- stimulus process
stim_proc: process
begin
wait for 100 ns;
r0_1 <= '0';r0_2 <= '0';
wait ;
end process;end;

7.9 Output Waveform:

Fig. 7.3 Binary counter output waveform

7.10 Result:-

VHDL code for 4-Bit binary counter (IC7493) in behavioral style is written and
simulated using Xilinx 14.5 version and output is observed

7.11 VIVA Questions:

1. What is the difference between decade counter and 4 bit counter?

2. What is meant by a modulus of a counter?
3. Write the behavioral code for IC74X93?
4. Explain the operation of IC74X93?
5. Write the syntax for component instantiation?
6. What is net list?
7. Briefly explain about generics?

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 8) SHIFT REGISTER (IC 7495)
8.1 Aim: - To Write a VHDL code and to Simulate shift register.( IC 74x95)
8.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
8.3 Theory:
 The 7495 has parallel and serial inputs, parallel outputs, mode control and two clock
inputs.
 The register has three modes of operation.
i. Parallel (broadside) load
ii. Shift right
iii. Shift left.
 Parallel loading is accomplished by applying the 4-bits of data and taking the mode
control input high. The data is loaded in to the associated flip-flops and appears at the
outputs after the high to low transition of the clock-2 input. During loading, the entry
of serial data is inhibited.
 Shift right operation is accomplished on the high-to-low transition of clock 1 when
the mode control is low.
 Shift left operation is accomplished on the high-to-low transition of clock 2 when the
mode control is high by connecting the output of each flip-flop to the parallel input of
the previous flip-flop (QD to input C,etc) and the serial data is entered at the input D.

8.4 Logic Diagram of Shift Register:

Fig.8.1 Logic diagram of Shift Register

8.5 Truth Table:-

Table.8.1 Shift register truth table

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8.6 Pin diagram of IC7495:

Fig.8.2 Pin diagram of IC-7495

8.7 VHDL Code for Shift Register (IC7495):-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_register_7495 is
Port ( clk1,clk2 : in STD_LOGIC;
m_s,sd : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (3 downto 0);
q : inout STD_LOGIC_VECTOR (3 downto 0));
end shift_register_7495;

architecture Behavioral of shift_register_7495 is

begin
process(clk1,clk2,m_s,sd)
begin
if(m_s='0') then
if(clk1'event and clk1='0') then
q<= sd & q(3 downto 1);

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 end if;
elsif(m_s='1') then
if(clk2'event and clk2='0') then
q<=d(3)& d(2)&d(1)&d(0) ;
end if;
end if;
end process;
end Behavioral;

8.8 VHDL Test Bench Code for Shift Register (IC7495):-:-

library ieee;
use ieee.std_logic_1164.all;

entity shift_register_tb is
end shift_register_tb;

architecture behavior of shift_register_tb is

-- component declaration for the unit under test (uut)

component shift_register_7495
port(clk1 : in std_logic;
clk2 : in std_logic;
m_s : in std_logic;
sd : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end component;

--inputs
signal clk1 : std_logic := '0';
signal clk2 : std_logic := '0';
signal m_s : std_logic := '0';
signal sd : std_logic := '0';
signal d : std_logic_vector(3 downto 0):=(others => '0');

--bidirs
signal q : std_logic_vector(3 downto 0);
-- clock period definitions
constant clk1_period : time := 50 ns;
constant clk2_period : time := 50 ns;

begin
-- instantiate the unit under test (uut)
uut: shift_register_7495 port map (
clk1 => clk1,
clk2 => clk2,
m_s => m_s,
sd => sd,

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 d => d,
q => q);

-- clock process definitions

clk1_process :process
begin
clk1 <= '0';
wait for clk1_period/2;
clk1 <= '1';
wait for clk1_period/2;
end process;
clk2_process :process
begin
clk2 <= '0';
wait for clk2_period/2;
clk2 <= '1';
wait for clk2_period/2;
end process;
mode_proc: process
begin
m_s<='1';sd<='0';
wait for clk1_period*4;
m_s<='0';sd<='1';
wait for clk1_period*4;
end process;
data_proc:process
begin
d<="0001";
wait for 150ns;
d<="0010";
wait for 150ns;
d<="0011";
wait for 150ns;
d<="0100";
wait for 150ns;
d<="0101";
wait for 150ns;
d<="0110";
wait for 150ns;
d<="0111";
wait for 150ns;
d<="1000";
end process;
end;

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8.9 Output Waveform:-

Fig.8.3 Shift Register Output Waveform

8.10 Result:-

VHDL code for Shift Register (IC7495) in behavioral style is written and simulated
using Xilinx 14.5 version and output is observed

8.11 VIVA Questions:

1. Write the behavioral code for IC 74x95.

2. What is a shift register?
3. Write some applications of shift register?
4. Explain briefly about BLOCK?
5. Write the syntax for function?
6. Write the syntax for procedure?
7. How to define variable in VHDL?
8. Write the syntax for CASE statement?
9. What is the advantage of case statement over if-else statement?
10. Write the difference between with-select and when-else statement?

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 9) UNIVERSAL SHIFT REGISTER(IC 74194/195).
9.1 Aim: - To Write a VHDL code and to Simulate universal shift register(IC 74x194).

9.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
9.3 Theory:-

 The 74194 is a bi-directional shift registers contains parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating mode control inputs and a direct
overriding clear line.
 The register has 4-distict mode of operations.
i. Inhibit Clock (do nothing)
ii. Shift Right (in the direction QA toward QD)
iii. Shift Left (in the direction QD toward QA)
iv. Parallel (broad side) load
 Parallel Load is accomplished by applying the 4-bits of data and taking both mode
control inputs (S0, S1) high. The data are loaded in to the associated flip flops and
appear at the output after positive transition of the clock inputs. During loading, serial
data flow is inhibited.
 Shift right is accomplished with the raising edge of the clock pulse when S0 I s high
and S1 is low. Serial data for this mode is entered at the shift –right data input. When
S0 is low and S1 is high, at shifts left and new data is entered at the shift-left serial
input.
 Clocking of the Shift Register is inhibited when both modes control inputs are low.
The mode controls of 74194 should be changed while the clock input is high.

9.4 Logic Diagram of Universal Shift Register:-

Fig.9.1 Logic diagram of USR

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9.5 Truth Table:-
Table 9.1 truth table of USR

9.6 Pin Diagram IC 74194

Fig 9.2 Pin Diagram IC 74194

9.7 VHDL Code for Universal Shift Register(IC 74194):-

library IEEE;
use IEEE.std_logic_1164.all;

entity shift194 is
port (clk : in STD_LOGIC;
dsr,dsl : in STD_LOGIC;
clr_l : in STD_LOGIC;
S:in STD_LOGIC_VECTOR(1 downto 0);
d: in STD_LOGIC_VECTOR (3 downto 0);
q: inout STD_LOGIC_VECTOR (3 downto 0));
end shift194;

architecture shift194 of shift194 is

begin

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 process(clk,s,clr_l)
begin
if clr_l='0' then
q<=(others=>'0');
elsif clr_l='1' then
if(clk'event and clk='1') then
case s is
when"00" =>q<=q;
when"01"=>q<=q(2 downto 0) & dsr;
when"10" =>q<=dsl & q(3 downto 1);
when"11" =>q<=d(3)& d(2)& d(1)& d(0);
when others=>null;
end case;
end if;
end if;
end process;
end shift194;

9.8 VHDL Test Bench Code for USR (74194):-

library ieee;
use ieee.std_logic_1164.all;

entity shift194_tb is
end shift194_tb;

architecture behavior of shift194_tb is

-- component declaration for the unit under test (uut)

component shift194
port(clk : in std_logic;
dsr : in std_logic;
dsl : in std_logic;
clr_l : in std_logic;
s : in std_logic_vector(1 downto 0);
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end component;

--inputs
signal clk : std_logic := '0';
signal dsr : std_logic := '0';
signal dsl : std_logic := '0';
signal clr_l : std_logic := '0';
signal s: std_logic_vector(1 downto 0):= (others => '1');
signal d : std_logic_vector(3 downto 0) := (others => '1');

--bidirs
signal q : std_logic_vector(3 downto 0);

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 -- clock period definitions
constant clk_period : time := 50 ns;
begin
-- instantiate the unit under test (uut)
uut: shift194 port map (clk => clk,
dsr => dsr,
dsl => dsl,
clr_l => clr_l,
s => s,
d => d,
q => q);

-- clock process definitions

clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;

sel_proc: process
begin
s<="00";wait for 250 ns;
s<="01";wait for 250 ns;
s<="10";wait for 250 ns;
s<="11";wait for 250 ns;
end process;

data_proc: process
begin
wait for 200 ns;
d<="1101";clr_l<='1';dsr<='1';dsl<='1';
wait for 200 ns;
d<="1001";clr_l<='1';dsr<='0';dsl<='1';
wait for 200 ns;
d<="0101";clr_l<='1';dsr<='1';dsl<='0';
wait for 200 ns;
d<="0111";clr_l<='1';dsr<='0';dsl<='0';
wait for 200 ns;
end process;
end;

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9.9 Output Waveform:-

Fig.9.3 USR output waveform

9.10 Result:-
VHDL code for Universal shift register in behavioral style is written and simulated
using Xilinx 14.5 version and output is observed

9.11 VIVA Questions:

1. Write the behavioral code for IC 74x95.

2. What is a shift register?
3. Write some applications of shift register?
4. Explain briefly about BLOCK?
5. Write the syntax for function?
6. Write the syntax for procedure?
7. How to define variable in VHDL?
8. Write the syntax for CASE statement?
9. What is the advantage of case statement over if-else statement?
10. Write the difference between with-select and when-else statement?

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 10) READ AND WRITE OPERATIONS OF RAM (IC 74X189)
10.1 Aim:-To Write a VHDL code and to Simulate read and write operations of Random
Access Memory(IC 74X189)

10.2 Apparatus:-
1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5

10.3 Theory:

The behavior of the 74189 circuit is controlled by just two active-low control lines,
namely the chip select and read/write inputs:

 CS=1: the data outputs are tri-stated and the clock signal for the latches in the
memory matrix is disabled.
 CS=0, Read/nWrite=1: the data outputs are enabled and driven with the contents of
the currently addressed memory word. When the address input is changed, the
contents of the newly selected memory word will appear on the data outputs, delayed
by the memory access time.
 CS=0, Read/nWrite=0: the clock signal of the currently addressed memory latches is
enabled, so that the values on the data input bus is copied into the selected memory
word (transparent latches). Also, the data outputs are enabled. Switch the Read/nWrite
signal back to the high (1) state to store the data.

10.4 Logic Diagram of RAM:-

Fig.10.1 Logic k diagram of RAM

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10.5 Truth Table:-

Table.10.1 Truth table of RAM

10.6 Pin Diagram of IC74189:-

Fig.10.2 Pin diagram of RAM (IC74189)

10.7 VHDL Code for RAM (74189) Read & Write Operation:-

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dm74189 is
port (a: in std_logic_vector (3 downto 0);
d: in std_logic_vector (3 downto 0);
cs_bar : in std_logic;
we_bar : in std_logic;
q: out std_logic_vector (3 downto 0));
end dm74189;

architecture ram of dm74189 is

type ram_type is array (0 to 15) of std_logic_vector (3 downto
0);
signal temp:ram_type;
begin

write: process(cs_bar,we_bar,a,d)
begin

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 if(cs_bar='0'and we_bar='0') then
temp(conv_integer(a))<=d;
end if;
end process write;

read : process (cs_bar,we_bar,a,d)

variable v1:std_logic_vector (3 downto 0);
begin
if(cs_bar='0'andwe_bar='1')then
v1:=temp(conv_integer(a));
else
v1:=(v1'range =>'z');
end if;
q<= v1;
end process read;
end ram;

10.8 VHDL Code for RAM(74189) Read & Write Operation:-

library ieee;
use ieee.std_logic_1164.all;

entity ram_tb is
end ram_tb;

architecture behavior of ram_tb is

-- component declaration for the unit under test (uut)

component dm74189
port(a : in std_logic_vector(3 downto 0);
d : in std_logic_vector(3 downto 0);
cs_bar : in std_logic;
we_bar : in std_logic;
q : out std_logic_vector(3 downto 0));
end component;
--inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal d : std_logic_vector(3 downto 0) := (others => '0');
signal cs_bar : std_logic := '0';
signal we_bar : std_logic := '0';

--outputs
signal q : std_logic_vector(3 downto 0);

begin

-- instantiate the unit under test (uut)

uut: dm74189 port map (a => a,
d => d,

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 cs_bar => cs_bar,
we_bar => we_bar,
q => q);

-- stimulus process
data_proc: process
begin
wait for 100 ns;
a<="1010";d<="1111";
wait for 100 ns;
a<="1110";d<="1001";
wait for 100 ns;
a<="1011";d<="1000";
wait for 100 ns;
end process;

read_write_proc: process
begin
wait for 500 ns;
we_bar<='1';
wait;
end process;
end;

10.9 Output Waveform:-

Fig.10.3 Read and Write operation of RAM output Waveform

10.10 Result:-
VHDL code for Read and Write operation of RAM is written and simulated using Xilinx
14.5 version and output is observed

10.11 VIVA Questions:

1. What is a Read and Write operation?
2. Write some applications of Read and Write operation?
3. What is RAM
4. Write syntax for

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 11. ALU DESIGN(IC 74381)
11.1 Aim:- To write a VHDL code and to Simulate Arithmetic Logic Unit.
11.2 Apparatus:-

1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5
11.3 ALU Operation:-

The 'F381 performs three arithmetic and three logic operations on two 4-bit
words, A and B. Two additional select input codes force the function outputs LOW or HIGH.
Carry propagate and generate outputs are provided for use with the 'F182 carry look ahead
generator for high-speed expansion to longer word lengths.
Features
 Low input loading minimizes drive requirements
 Performs six arithmetic and logic functions
 Selectable LOW (clear) and HIGH (preset) functions
Carry generate and propagate outputs for use with carry.

11.4 Block Diagram of ALU:-

Fig.11.1 Block diagram of ALU

11.5 Pin Diagram :-

Fig.11.2 Pin diagram of ALU (74381)

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11.6 Truth Table:-

Table 11.1 ALU Truth table

11.7 VHDL Code for ALU Design(IC 74381):-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity IC74381 is
port (a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
s: in STD_LOGIC_VECTOR (2 downto 0);
cin: in STD_LOGIC;
f:out STD_LOGIC_VECTOR (3 downto 0));
end IC74381;
architecture Behavioral of IC74381 is
begin
process(a,b,cin,s)
begin
case s is
when "000" =>f<="0000";
when "001" =>f<= b-a-1+cin;
when "010" =>f<= a-b-1+cin;
when "011" =>f<= a+b+cin;
when "100" =>f<= a xor b;
when "101" =>f<= a or b;
when "110" =>f<= a and b;
when “111” =>f<= "1111";
when others =>f<= "UUUU";
end case;
end process;
end Behavioral;

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11.8 VHDL Test Bench Code for ALU:-

library ieee;
use ieee.std_logic_1164.all;

entity alu_tb is
end alu_tb;

architecture behavior of alu_tb is

-- component declaration for the unit under test (uut)

component ic74381
port(a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : in std_logic_vector(2 downto 0);
cin : in std_logic;
f : out std_logic_vector(3 downto 0));
end component;
--inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal s : std_logic_vector(2 downto 0) := (others => '0');
signal cin : std_logic := '0';

--outputs
signal f : std_logic_vector(3 downto 0);

begin
-- instantiate the unit under test (uut)
uut: ic74381 port map ( a => a,
b => b,
s => s,
cin => cin,
f => f );
-- stimulus process
input_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a<="0000";b<="0001";cin<='1';
wait for 100 ns;
a<="0010";b<="0101";cin<='0';
wait for 100 ns;
a<="1001";b<="1001";cin<='1';
wait for 100 ns;
a<="1110";b<="1111";cin<='1';
wait for 100 ns;
end process;

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 sel_proc: process
begin
s<="000";
wait for 100 ns;
s<="001";
wait for 100 ns;
s<="010";
wait for 100 ns;
s<="011";
wait for 100 ns;
s<="100";
wait for 100 ns;
s<="101";
wait for 100 ns;
s<="110";
wait for 100 ns;
s<="111";
wait for 100 ns;
end process;
end;

11.9 Output Waveforms:

Fig.11.3 ALU output waveform

11.10 Result:-
VHDL code for ALU in behavioral style is written and simulated using Xilinx 14.5
version and output is observed

11.11 VIVA Questions:-

1. What is ALU?
2. What are the applications of ALU?

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