What is NAND Flash Memory?

March ‘03

File Memory Marketing & Promotion Department

Memory Division
TOSHIBA Semiconductor Company

Copyright © 2003 Toshiba Corporation. All rights reserved.

 NAND Flash Memory Concept

/CE
„ Suitable for file storage /RE
/WE
R/BY
CLE
- File memory architecture ALE

System Bus
/WP
- Page programming (512 bytes/page) NAND
Flash
„ High performance I/O1 - I/O8

- High speed programming and erasing

„ Low cost
- Small chip size based on NAND Structure CLE

- Small pin count /CE

/WE
„ Easy memory expansion
ALE

- Simple interface by command control I/O 1-8 CMD Add Add Add

Command Address Input

Input
 NAND vs. NOR - Cell Structure

NAND NOR
Bit line
Word line Contact

Word line

Cell Unit Cell

Array Unit Cell

Source line Source line

2F
2F
Layout 2F 5F

Cross-
section
Cell size 4F2 10F2
 NAND / NOR Characteristics

NAND NOR
Capacity ~ 1Gbit (2chips/pkg) ~ 128Mbit
Power Supply 2.7-3.6V 2.3-3.6V
I/O x8 x8/x16
50ns(serial access cycle) 70ns(30pF, 2.3V)
Access Time 25µs(random access) 65ns(30pF, 2.7V)

Program 8µs/Byte
Speed (typ.) 200µs/512Byte 4.1ms/512Byte
Erase 2ms/Block (16KB) 700ms/Block
Speed(typ.)
Prog+Erase(typ.) 33.6ms / 64KB 1.23s/Block (main:64KB)
 NAND Flash Memory Block Diagram

ex.256Mb NAND Flash Memory

t
8bi (512+16Byte) Bit Line
Basic unit
Register SG (D)

WL1
WL2
WL3
32page/Block
WL4
Page
～
～ ～
～
(WL30)

Cell Array Redundant Cell

(WL31)
(WL32)
Array
SG (S)
512Byte 16Byte

256Mb NAND Flash

Page Size : 512+16 Bytes
Block Size : 16KBytes
# of Blocks : 2048 Blocks
 NAND Flash Memory Basic Function (1)

Read
Register
High Speed
Serial Read
1page Read

< Timing Chart>

CE low

ALE

CLE

WE

RE
Command DN DN+1 D527
I/O1~8 00H Col Row1 Row2

R/B Address Address Address Wait(tR) Data-Out Data-Out Data-Out

N
(ex. 256Mb NAND Flash Memory)
 NAND Flash Memory Basic Function (2)

Program
Register
Data Input

1page
Program
Page

Block
< Timing Chart >
CE low

ALE

CLE

WE

RE high
Command Command
I/O1~8 80H Col Row1 Row2 D0 D1 D527 10H
Wait(tPROG)
R/B Address Address Address Data-In Data-In Data-In
(ex. 256Mb NAND Flash Memory)
 NAND Flash Memory Basic Function (3)

Erase
Register

Block Erase
(32page)

< Timing Chart >

CE low

ALE

CLE

WE

RE high
Command Command

I/O1~8 60H Row1 Row2 D0H

Wait(tERASE)
R/B Address Address
(ex. 256Mb NAND Flash Memory)
 NAND Flash Control in System

< Required Items >

1. NAND Flash File Management

- Bad Block Management
- Wear Leveling Treatment

2. ECC Support
- 1 bit/page error correction
and 2bit/page error detection**

* ECC : Error Correction Code

* * : 2LC NAND Flash 1bit/page ECC
 Invalid block detection at Incoming

Number of valid blocks at shipping

Start
Type. Min. Max.
Block No = 1
TC58V64 1014 1024

TC58128 1004 1024 Fail

Read Check
TC58256 2008 2048 Block No. = Block
Pass
Bad Block *1
No. + 1
TC58512 4016 4096
No
TH58100 8032 8192 Block No. = Last Block
Yes

Invalid blocks have to be detected by End

bad block test flow before erasing. < Read Check >
Read the 1st page of each block. If byte 517 of
• Invalid block : include “0” data. This “0” the 1st page is not FF (Hex), define the block as
a bad block. The 1st block in the device is
data may be lost by erasing. guaranteed to be good at time of shipment.
• Valid block : has only “1” data.
*1 : No erase operation is allowed to bad blocks
 NAND Flash Memory Basic Specification

0.16um

TC58V64BFT TC58128AFT TC58256AFT TC58512FT TH58100FT

64Mb 128Mb 256Mb 512Mb 1Gb

Density (8M+256K)x8 (16M+512K)x8 (32M+1M)x8 (64M+2M)x8 (128M+4M)x8

Operation voltage 2.7V-3.6V ← ← ← ←

Page size ( program unit ) 512B+16B ← ← ← ←

Block size ( erase unit ) 8KB+256B 16KB+512B ← ← ←
Number of Pages per Block 16 32 ← ← ←
Number of Blocks 1024 1024 2048 4096 8192

Number of Address cycle 3 ← ← 4 ←

Random access time ( us ) 25us (max.)

Serial access time ( ns ) 50ns (min.)

Package 400mil / 0.8mm

TSOP type II TSOP I 48-P-1220-0.50
 2 Type Read Function

Type 1 (TSOP Package)

Sequential Read
/CE (00H)
0 527
/WE

/RE A

R/B N Busy
M Data Output
I/O 00H
Sequential Read (1)
Start-address input Sequential Read

Type 2 (BGA/MCP Package)

/CE don’t care No Sequential Read
/CE M 527

/WE

/RE Select
page
N Cell
R/B Busy array
N
M Data Output
I/O 00H Figure 3. Read mode (1)
operation
Start-address input

Next Add. Input

 TSOP Package

Package Type TSOP-II 44-P-400-0.8 TSOP-I 48-P-1220-0.50

VSS VCC NC 1 48 NC
1 44 NC 2 47 NC
CLE 2 43 CE NC 3 46 NC
NC 4 45 NC
ALE 3 42 RE NC 5 44 I/O8
WE OP 6 42 I/O7
4 41 R/B R/B 7 42 I/O6
WP OP RE 8 41 I/O5
5 40 CE 9 40 NC
NC 10 39 NC
NC 11 38 NC
(L ) Vcc 12 37
Top View Vss 13 36
Vcc ( L )
Vss
NC 14 35 NC
NC 15 34 NC
I/O 1 18 27 I/O 8 CLE 16 33 NC
ALE 17 32 I/O4
I/O 2 19 26 I/O 7 WE 18 31 I/O3
I/O 3 20 25 WP 19 30 I/O2
I/O 6 NC 20 29 I/O1
I/O 4 21 24 I/O 5 NC 21 28 NC
NC 22 27 NC
VSS 22 23 VCC NC 23 26 NC
NC 24 25 NC
(W) (W)

12.0(L) x 20.0(W) x 1.2 (max) mm

Package 18.41(L) x 11.76(W) x 1.2 (max) mm
Single

dimensions 128Mbit : TC58128AFT

64Mbit : TC58V64BFT 256Mbit : TC58256AFT
&
512Mbit : TC58512FT
Close
Stacked

section View 12.0(L) x 20.0(W) x 1.2 (max) mm

& 1Gbit : TH58100FT
Memory P/N
 CSP Outline Drawing
256M/128M NAND Flash CSP Package Size
Design rule
0.16um 0.13um
256M : 9mm X 11mm 7mm X 10mm
128M : 7mm X 10mm 7mm X 10mm
( 7x10 : no dummy ball )

1.6
Bottom View
Top View 0.8

5.6
11

0.8
1.6
9
4.0

: Contact Balls
1.2max
: Index Mark Ball

: Dummy Balls
0.47 typ.
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